implement .ll and .bc support for nsw/nuw on shl and exact on lshr/ashr.
Factor some code better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125006 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/LangRef.html b/docs/LangRef.html
index f799749..dbe3853 100644
--- a/docs/LangRef.html
+++ b/docs/LangRef.html
@@ -3684,7 +3684,10 @@
<h5>Syntax:</h5>
<pre>
- <result> = shl <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = shl <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = shl nuw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = shl nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = shl nuw nsw <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -3704,6 +3707,14 @@
vectors, each vector element of <tt>op1</tt> is shifted by the corresponding
shift amount in <tt>op2</tt>.</p>
+<p>If the <tt>nuw</tt> keyword is present, then the shift produces a
+ <a href="#trapvalues">trap value</a> if it shifts out any non-zero bits. If
+ the <tt>nsw</tt> keywrod is present, then the shift produces a
+ <a href="#trapvalues">trap value</a> if it shifts out any bits that disagree
+ with the resultant sign bit. As such, NUW/NSW have the same semantics as
+ they would if the shift were expressed as a mul instruction with the same
+ nsw/nuw bits in (mul %op1, (shl 1, %op2)).</p>
+
<h5>Example:</h5>
<pre>
<result> = shl i32 4, %var <i>; yields {i32}: 4 << %var</i>
@@ -3723,7 +3734,8 @@
<h5>Syntax:</h5>
<pre>
- <result> = lshr <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = lshr <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = lshr exact <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -3743,6 +3755,11 @@
vectors, each vector element of <tt>op1</tt> is shifted by the corresponding
shift amount in <tt>op2</tt>.</p>
+<p>If the <tt>exact</tt> keyword is present, the result value of the
+ <tt>lshr</tt> is a <a href="#trapvalues">trap value</a> if any of the bits
+ shifted out are non-zero.</p>
+
+
<h5>Example:</h5>
<pre>
<result> = lshr i32 4, 1 <i>; yields {i32}:result = 2</i>
@@ -3762,7 +3779,8 @@
<h5>Syntax:</h5>
<pre>
- <result> = ashr <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = ashr <ty> <op1>, <op2> <i>; yields {ty}:result</i>
+ <result> = ashr exact <ty> <op1>, <op2> <i>; yields {ty}:result</i>
</pre>
<h5>Overview:</h5>
@@ -3783,6 +3801,10 @@
the arguments are vectors, each vector element of <tt>op1</tt> is shifted by
the corresponding shift amount in <tt>op2</tt>.</p>
+<p>If the <tt>exact</tt> keyword is present, the result value of the
+ <tt>ashr</tt> is a <a href="#trapvalues">trap value</a> if any of the bits
+ shifted out are non-zero.</p>
+
<h5>Example:</h5>
<pre>
<result> = ashr i32 4, 1 <i>; yields {i32}:result = 2</i>