commit f19b8b018be4b0478f741bf35287db3488fda8d6
author Benjamin Kramer <benny.kra@googlemail.com> Tue May 21 08:51:09 2013 +0000
committer Benjamin Kramer <benny.kra@googlemail.com> Tue May 21 08:51:09 2013 +0000
tree badb6014825a9a7bd8bc2e9dcaf7a4aa37ce5972
parent 275428fe4abd4bd690456d29c7c54143d653cb4f

DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.

Fixes PR16083.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/TargetLowering.cpp

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 36add03..e8b6c04 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1162,7 +1162,8 @@
       }
 
       // Make sure we're not losing bits from the constant.
-      if (MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
+      if (MinBits > 0 &&
+          MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
         EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
         if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
           // Will get folded away.