implement a trivial readme entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44380 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 608cc4c..8cf5452 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -262,6 +262,9 @@
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ // We have target-specific dag combine patterns for the following nodes:
+ // ARMISD::FMRRD - No need to call setTargetDAGCombine
+
setStackPointerRegisterToSaveRestore(ARM::SP);
setSchedulingPreference(SchedulingForRegPressure);
setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
@@ -1510,6 +1513,27 @@
// ARM Optimization Hooks
//===----------------------------------------------------------------------===//
+/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
+static SDOperand PerformFMRRDCombine(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI) {
+ // fmrrd(fmdrr x, y) -> x,y
+ SDOperand InDouble = N->getOperand(0);
+ if (InDouble.getOpcode() == ARMISD::FMDRR)
+ return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
+ return SDOperand();
+}
+
+SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ switch (N->getOpcode()) {
+ default: break;
+ case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
+ }
+
+ return SDOperand();
+}
+
+
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 93971c5..39e2383 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -78,6 +78,8 @@
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
+ SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+
virtual const char *getTargetNodeName(unsigned Opcode) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index 1fb7750..da249b7 100644
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -574,21 +574,3 @@
//===---------------------------------------------------------------------===//
-Easy ARM microoptimization (with -mattr=+vfp2):
-
-define i64 @i(double %X) {
- %Y = bitcast double %X to i64
- ret i64 %Y
-}
-
-compiles into:
-
-_i:
- fmdrr d0, r0, r1
- fmrrd r0, r1, d0
- bx lr
-
-This just needs a target-specific dag combine to merge the two ARMISD nodes.
-
-
-//===---------------------------------------------------------------------===//