Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index a7899c8..ce308ee 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -26,6 +26,10 @@
def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
+def SDT_PPCvperm : SDTypeProfile<1, 3, [
+ SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
+]>;
+
//===----------------------------------------------------------------------===//
// PowerPC specific DAG Nodes.
//
@@ -46,6 +50,7 @@
def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
def PPClve_x : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
+def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
@@ -118,15 +123,6 @@
return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
}], HI16>;
-/*
-// Example of a legalize expander: Only for PPC64.
-def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
- [(set f64:$tmp , (FCTIDZ f64:$src)),
- (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
- (store f64:$tmp, i32:$tmpFI),
- (set i64:$dst, (load i32:$tmpFI))],
- Subtarget_PPC64>;
-*/
//===----------------------------------------------------------------------===//
// PowerPC Flag Definitions.
@@ -956,7 +952,9 @@
Requires<[FPContractions]>;
def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
- "vperm $vD, $vA, $vC, $vB", VecFP, []>;
+ "vperm $vD, $vA, $vC, $vB", VecFP,
+ [(set VRRC:$vD,
+ (PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC))]>;
// VX-Form instructions. AltiVec arithmetic ops.
@@ -1153,6 +1151,13 @@
def : Pat<(v4i32 (load xoaddr:$src)),
(v4i32 (LVX xoaddr:$src))>;
+def : Pat<(v16i8 (load xoaddr:$src)),
+ (v16i8 (LVX xoaddr:$src))>;
+
+
+def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
+ (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
+
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(v4i32 (PPClve_x xoaddr:$src)),