commit f2764c89083183e0e5da800af18b23bc67937734
author Jim Grosbach <grosbach@apple.com> Fri Aug 19 19:53:51 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Fri Aug 19 19:53:51 2011 +0000
tree 1b8d2a1b5612d426e6e125432efae50c69b557d7
parent b86e2dbf61425b195ac5c281e480d9f4414377af

Tidy up. Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138067 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenInstruction.cpp

diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index 86a377b..751326c 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -432,8 +432,8 @@
 
     if (!T.getRegisterClass(InstOpRec)
         .contains(T.getRegBank().getReg(ADI->getDef())))
-      throw TGError(Loc, "fixed register " +ADI->getDef()->getName()
-                    + " is not a member of the " + InstOpRec->getName() +
+      throw TGError(Loc, "fixed register " + ADI->getDef()->getName() +
+                    " is not a member of the " + InstOpRec->getName() +
                     " register class!");
 
     if (!Result->getArgName(AliasOpNo).empty())