diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 5a2b4ed..31a784e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -844,23 +844,31 @@
     case ISD::SRCVALUE:
       break;
     case ISD::CopyToReg: {
-      unsigned InReg;
-      if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
-        InReg = R->getReg();
+      unsigned SrcReg;
+      SDOperand SrcVal = Node->getOperand(2);
+      if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
+        SrcReg = R->getReg();
       else
-        InReg = getVR(Node->getOperand(2), VRBaseMap);
+        SrcReg = getVR(SrcVal, VRBaseMap);
+      
       unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
-      if (InReg != DestReg)  {// Coalesced away the copy?
-        const TargetRegisterClass *TRC = 0;
-        // Get the target register class
-        if (TargetRegisterInfo::isVirtualRegister(InReg))
-          TRC = RegInfo.getRegClass(InReg);
-        else
-          TRC =
-            TRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
-                                            InReg);
-        TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
-      }
+      if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
+        break;
+      
+      const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
+      // Get the register classes of the src/dst.
+      if (TargetRegisterInfo::isVirtualRegister(SrcReg))
+        SrcTRC = RegInfo.getRegClass(SrcReg);
+      else
+        SrcTRC = TRI->getPhysicalRegisterRegClass(SrcVal.getValueType(),SrcReg);
+
+      if (TargetRegisterInfo::isVirtualRegister(DestReg))
+        DstTRC = RegInfo.getRegClass(DestReg);
+      else
+        DstTRC = TRI->getPhysicalRegisterRegClass(
+                                            Node->getOperand(1).getValueType(),
+                                                  DestReg);
+      TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
       break;
     }
     case ISD::CopyFromReg: {
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 01a7cd4..3c12fa1 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1465,7 +1465,7 @@
     }
   }
   
-  // Moving ST(0) to/from a register turns into FpGET_ST0_32 etc.
+  // Moving from ST(0) turns into FpGET_ST0_32 etc.
   if (SrcRC == &X86::RSTRegClass) {
     // Copying from ST(0).  FIXME: handle ST(1) also
     assert(SrcReg == X86::ST0 && "Can only copy from TOS right now");
@@ -1481,6 +1481,23 @@
     BuildMI(MBB, MI, get(Opc), DestReg);
     return;
   }
+
+  // Moving to ST(0) turns into FpSET_ST0_32 etc.
+  if (DestRC == &X86::RSTRegClass) {
+    // Copying to ST(0).  FIXME: handle ST(1) also
+    assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
+    unsigned Opc;
+    if (SrcRC == &X86::RFP32RegClass)
+      Opc = X86::FpSET_ST0_32;
+    else if (SrcRC == &X86::RFP64RegClass)
+      Opc = X86::FpSET_ST0_64;
+    else {
+      assert(SrcRC == &X86::RFP80RegClass);
+      Opc = X86::FpSET_ST0_80;
+    }
+    BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
+    return;
+  }
   
   cerr << "Not yet supported!";
   abort();
diff --git a/test/CodeGen/X86/inline-asm-fpstack.ll b/test/CodeGen/X86/inline-asm-fpstack.ll
index e4a76b4..1e308d9 100644
--- a/test/CodeGen/X86/inline-asm-fpstack.ll
+++ b/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -10,4 +10,20 @@
         ret double %tmp85
 }
 
+define void @test3(x86_fp80 %X) {
+        call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X)
+        ret void
+}
+
+define void @test4(double %X) {
+        call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %X)
+        ret void
+}
+
+define void @test5(double %X) {
+        %Y = add double %X, 123.0
+        call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %Y)
+        ret void
+}
+