| commit | b7f06f46a176b2f19349d44581b0523297c8efb9 | [log] [tgz] |
|---|---|---|
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | Sun Nov 04 19:34:49 2001 +0000 |
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | Sun Nov 04 19:34:49 2001 +0000 |
| tree | b6a8073951335e67849887cc6b5a31b82ce3f826 | |
| parent | 8e7f4091695aad705f84398ede1fccc3796b1fad [diff] |
Fixed instruction information for RDCCR and WRCCR. Fixed selection to create a TmpInstruction for each integer CC register (since it is an implicit side-effect, unlike FP CC registers which are explicit operands). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1120 91177308-0d34-0410-b5e6-96231b3b80d8