Add a second vector type to the VRRC register class, and fix some patterns
so that tablegen can infer all types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24746 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 4ec8fe3..225017c 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -946,11 +946,11 @@
(srl GPRC:$rS, (sub 32, GPRC:$rB))),
(RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
-def : Pat<(zext GPRC:$in),
+def : Pat<(i64 (zext GPRC:$in)),
(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
-def : Pat<(anyext GPRC:$in),
+def : Pat<(i64 (anyext GPRC:$in)),
(OR4To8 GPRC:$in, GPRC:$in)>;
-def : Pat<(trunc G8RC:$in),
+def : Pat<(i32 (trunc G8RC:$in)),
(OR8To4 G8RC:$in, G8RC:$in)>;
// SHL