commit f4ecc68efa92c06e2de1937f2a6408f57318ee3f
author Bob Wilson <bob.wilson@apple.com> Mon Sep 28 14:30:20 2009 +0000
committer Bob Wilson <bob.wilson@apple.com> Mon Sep 28 14:30:20 2009 +0000
tree 858643786c87f2b6432334784f20184f2e04bdd8
parent 16c012d9a28fe4db3ee081192a587ad7f30d4cc2

Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82988 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARM.h

diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h
index e95dfc0..487ce1d 100644
--- a/lib/Target/ARM/ARM.h
+++ b/lib/Target/ARM/ARM.h
@@ -92,7 +92,8 @@
   }
 }
 
-FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM);
+FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
+                               CodeGenOpt::Level OptLevel);
 
 FunctionPass *createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
                                        MachineCodeEmitter &MCE);

lib/Target/ARM/ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index d165a09..53f2282 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -49,8 +49,9 @@
   const ARMSubtarget *Subtarget;
 
 public:
-  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
-    : SelectionDAGISel(tm), TM(tm),
+  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
+                           CodeGenOpt::Level OptLevel)
+    : SelectionDAGISel(tm, OptLevel), TM(tm),
     Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
   }
 
@@ -1566,6 +1567,7 @@
 /// createARMISelDag - This pass converts a legalized DAG into a
 /// ARM-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
-  return new ARMDAGToDAGISel(TM);
+FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
+                                     CodeGenOpt::Level OptLevel) {
+  return new ARMDAGToDAGISel(TM, OptLevel);
 }

lib/Target/ARM/ARMTargetMachine.cpp

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 045df15..dcb64c5 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -86,7 +86,7 @@
 // Pass Pipeline Configuration
 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
                                            CodeGenOpt::Level OptLevel) {
-  PM.add(createARMISelDag(*this));
+  PM.add(createARMISelDag(*this, OptLevel));
   return false;
 }