* Rename MethodPass class to FunctionPass
- Rename runOnMethod to runOnFunction
* Transform getAnalysisUsageInfo into getAnalysisUsage
- Method is now const
- It now takes one AnalysisUsage object to fill in instead of 3 vectors
to fill in
- Pass's now specify which other passes they _preserve_ not which ones
they modify (be conservative!)
- A pass can specify that it preserves all analyses (because it never
modifies the underlying program)
* s/Method/Function/g in other random places as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2333 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index f10bf3c..adc8903 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -1480,26 +1480,23 @@
//---------------------------------------------------------------------------
namespace {
- class InstructionSchedulingWithSSA : public MethodPass {
+ class InstructionSchedulingWithSSA : public FunctionPass {
const TargetMachine ⌖
public:
inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
- // getAnalysisUsageInfo - We use LiveVarInfo...
- virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
- Pass::AnalysisSet &Destroyed,
- Pass::AnalysisSet &Provided) {
- Requires.push_back(MethodLiveVarInfo::ID);
- Destroyed.push_back(MethodLiveVarInfo::ID);
+ // getAnalysisUsage - We use LiveVarInfo...
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired(MethodLiveVarInfo::ID);
}
- bool runOnMethod(Function *F);
+ bool runOnFunction(Function *F);
};
} // end anonymous namespace
bool
-InstructionSchedulingWithSSA::runOnMethod(Function *M)
+InstructionSchedulingWithSSA::runOnFunction(Function *M)
{
if (SchedDebugLevel == Sched_Disable)
return false;
@@ -1544,8 +1541,6 @@
}
-MethodPass*
-createInstructionSchedulingWithSSAPass(const TargetMachine &tgt)
-{
+Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) {
return new InstructionSchedulingWithSSA(tgt);
}
diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
index e9e4245..0518aef 100644
--- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
+++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
@@ -1,6 +1,6 @@
-//===-- MethodLiveVarInfo.cpp - Live Variable Analysis for a Function -----===//
+//===-- FunctionLiveVarInfo.cpp - Live Variable Analysis for a Function ---===//
//
-// This is the interface to method level live variable information that is
+// This is the interface to function level live variable information that is
// provided by live variable analysis.
//
//===----------------------------------------------------------------------===//
@@ -39,10 +39,10 @@
//-----------------------------------------------------------------------------
-// Performs live var analysis for a method
+// Performs live var analysis for a function
//-----------------------------------------------------------------------------
-bool MethodLiveVarInfo::runOnMethod(Function *Meth) {
+bool MethodLiveVarInfo::runOnFunction(Function *Meth) {
M = Meth;
if (DEBUG_LV) std::cerr << "Analysing live variables ...\n";
@@ -149,12 +149,12 @@
//-----------------------------------------------------------------------------
// Following functions will give the LiveVar info for any machine instr in
-// a method. It should be called after a call to analyze().
+// a function. It should be called after a call to analyze().
//
// Thsese functions calucluates live var info for all the machine instrs in a
// BB when LVInfo for one inst is requested. Hence, this function is useful
// when live var info is required for many (or all) instructions in a basic
-// block. Also, the arguments to this method does not require specific
+// block. Also, the arguments to this function does not require specific
// iterators.
//-----------------------------------------------------------------------------
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 0b680ab..c22ede9 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -40,14 +40,14 @@
// RegisterAllocation pass front end...
//----------------------------------------------------------------------------
namespace {
- class RegisterAllocator : public MethodPass {
+ class RegisterAllocator : public FunctionPass {
TargetMachine &Target;
public:
inline RegisterAllocator(TargetMachine &T) : Target(T) {}
- bool runOnMethod(Function *F) {
+ bool runOnFunction(Function *F) {
if (DEBUG_RA)
- cerr << "\n******************** Method "<< F->getName()
+ cerr << "\n******************** Function "<< F->getName()
<< " ********************\n";
PhyRegAlloc PRA(F, Target, &getAnalysis<MethodLiveVarInfo>(),
@@ -58,17 +58,14 @@
return false;
}
- virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
- Pass::AnalysisSet &Destroyed,
- Pass::AnalysisSet &Provided) {
- Requires.push_back(cfg::LoopInfo::ID);
- Requires.push_back(MethodLiveVarInfo::ID);
- Destroyed.push_back(MethodLiveVarInfo::ID);
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired(cfg::LoopInfo::ID);
+ AU.addRequired(MethodLiveVarInfo::ID);
}
};
}
-MethodPass *getRegisterAllocator(TargetMachine &T) {
+Pass *getRegisterAllocator(TargetMachine &T) {
return new RegisterAllocator(T);
}
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index a46f2ef..83e5487 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -4,10 +4,10 @@
// LLVM. The code in this file assumes that the specified module has already
// been compiled into the internal data structures of the Module.
//
-// This code largely consists of two LLVM Pass's: a MethodPass and a Pass. The
-// MethodPass is pipelined together with all of the rest of the code generation
-// stages, and the Pass runs at the end to emit code for global variables and
-// such.
+// This code largely consists of two LLVM Pass's: a FunctionPass and a Pass.
+// The FunctionPass is pipelined together with all of the rest of the code
+// generation stages, and the Pass runs at the end to emit code for global
+// variables and such.
//
//===----------------------------------------------------------------------===//
@@ -197,7 +197,7 @@
// SparcFunctionAsmPrinter Code
//===----------------------------------------------------------------------===//
-struct SparcFunctionAsmPrinter : public MethodPass, public AsmPrinter {
+struct SparcFunctionAsmPrinter : public FunctionPass, public AsmPrinter {
inline SparcFunctionAsmPrinter(std::ostream &os, const TargetMachine &t)
: AsmPrinter(os, t) {}
@@ -206,7 +206,7 @@
return false;
}
- virtual bool runOnMethod(Function *F) {
+ virtual bool runOnFunction(Function *F) {
startFunction(F);
emitFunction(F);
endFunction(F);
@@ -410,7 +410,7 @@
} // End anonymous namespace
-Pass *UltraSparc::getMethodAsmPrinterPass(PassManager &PM, std::ostream &Out) {
+Pass *UltraSparc::getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out){
return new SparcFunctionAsmPrinter(Out, *this);
}
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index 12c86b8..0e80179 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -128,7 +128,7 @@
// returned in `minstrVec'. Any temporary registers (TmpInstruction)
// created are returned in `tempVec'.
//
- virtual void CreateCodeToLoadConst(Function* method,
+ virtual void CreateCodeToLoadConst(Function *F,
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& minstrVec,
@@ -141,7 +141,7 @@
// The generated instructions are returned in `minstrVec'.
// Any temp. registers (TmpInstruction) created are returned in `tempVec'.
//
- virtual void CreateCodeToCopyIntToFloat(Function* method,
+ virtual void CreateCodeToCopyIntToFloat(Function* F,
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& minstr,
@@ -152,7 +152,7 @@
// `val' to an integer value `dest' by copying to memory and back.
// See the previous function for information about return values.
//
- virtual void CreateCodeToCopyFloatToInt(Function* method,
+ virtual void CreateCodeToCopyFloatToInt(Function* F,
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& minstr,
@@ -161,7 +161,7 @@
// create copy instruction(s)
virtual void CreateCopyInstructionsByType(const TargetMachine& target,
- Function* method,
+ Function* F,
Value* src,
Instruction* dest,
std::vector<MachineInstr*>& minstr) const;
@@ -224,7 +224,7 @@
// ======================== Private Methods =============================
// The following methods are used to color special live ranges (e.g.
- // method args and return values etc.) with specific hardware registers
+ // function args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation.
//
void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
@@ -251,7 +251,7 @@
unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
- // The following 3 methods are used to find the RegType (see enum above)
+ // The following 3 methods are used to find the RegType (see enum above)
// of a LiveRange, Value and using the unified RegClassID
int getRegType(const LiveRange *LR) const;
int getRegType(const Value *Val) const;
@@ -272,7 +272,7 @@
// The following 2 methods are used to order the instructions addeed by
- // the register allocator in association with method calling. See
+ // the register allocator in association with function calling. See
// SparcRegInfo.cpp for more details
//
void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
@@ -344,7 +344,7 @@
virtual int getZeroRegNum() const;
// getCallAddressReg - returns the reg used for pushing the address when a
- // method is called. This can be used for other purposes between calls
+ // function is called. This can be used for other purposes between calls
//
unsigned getCallAddressReg() const;
@@ -357,7 +357,7 @@
// The following methods are used to color special live ranges (e.g.
- // method args and return values etc.) with specific hardware registers
+ // function args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation for Sparc.
//
void suggestRegs4MethodArgs(const Function *Meth,
@@ -499,16 +499,16 @@
UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
public:
- int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
- int getMinStackFrameSize () const { return MinStackFrameSize; }
- int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; }
- int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; }
- bool argsOnStackHaveFixedSize () const { return true; }
+ int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
+ int getMinStackFrameSize() const { return MinStackFrameSize; }
+ int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
+ int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
+ bool argsOnStackHaveFixedSize() const { return true; }
//
// These methods compute offsets using the frame contents for a
- // particular method. The frame contents are obtained from the
- // MachineCodeInfoForMethod object for the given method.
+ // particular function. The frame contents are obtained from the
+ // MachineCodeInfoForMethod object for the given function.
//
int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
bool& growUp) const
@@ -623,7 +623,7 @@
virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
private:
- Pass *getMethodAsmPrinterPass(PassManager &PM, std::ostream &Out);
+ Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out);
Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
Pass *getEmitBytecodeToAsmPass(std::ostream &Out);
};
diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index 2dad572..17cd73b 100644
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -21,11 +21,11 @@
namespace {
-class InsertPrologEpilogCode : public MethodPass {
+class InsertPrologEpilogCode : public FunctionPass {
TargetMachine &Target;
public:
InsertPrologEpilogCode(TargetMachine &T) : Target(T) {}
- bool runOnMethod(Function *F) {
+ bool runOnFunction(Function *F) {
MachineCodeForMethod &mcodeInfo = MachineCodeForMethod::get(F);
if (!mcodeInfo.isCompiledAsLeafMethod()) {
InsertPrologCode(F);
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index de778e2..306b85a 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -126,21 +126,21 @@
// Native code generation for a specified target.
//===---------------------------------------------------------------------===//
-class ConstructMachineCodeForFunction : public MethodPass {
+class ConstructMachineCodeForFunction : public FunctionPass {
TargetMachine &Target;
public:
inline ConstructMachineCodeForFunction(TargetMachine &T) : Target(T) {}
- bool runOnMethod(Function *F) {
+ bool runOnFunction(Function *F) {
MachineCodeForMethod::construct(F, Target);
return false;
}
};
-class InstructionSelection : public MethodPass {
+class InstructionSelection : public FunctionPass {
TargetMachine &Target;
public:
inline InstructionSelection(TargetMachine &T) : Target(T) {}
- bool runOnMethod(Function *F) {
+ bool runOnFunction(Function *F) {
if (SelectInstructionsForMethod(F, Target)) {
cerr << "Instr selection failed for function " << F->getName() << "\n";
abort();
@@ -149,12 +149,12 @@
}
};
-struct FreeMachineCodeForFunction : public MethodPass {
+struct FreeMachineCodeForFunction : public FunctionPass {
static void freeMachineCode(Instruction *I) {
MachineCodeForInstruction::destroy(I);
}
- bool runOnMethod(Function *F) {
+ bool runOnFunction(Function *F) {
for (Function::iterator FI = F->begin(), FE = F->end(); FI != FE; ++FI)
for (BasicBlock::iterator I = (*FI)->begin(), E = (*FI)->end();
I != E; ++I)
@@ -197,7 +197,7 @@
// allowing machine code representations for functions to be free'd after the
// function has been emitted.
//
- PM.add(getMethodAsmPrinterPass(PM, Out));
+ PM.add(getFunctionAsmPrinterPass(PM, Out));
PM.add(new FreeMachineCodeForFunction()); // Free stuff no longer needed
// Emit Module level assembly after all of the functions have been processed.