MMX argument passing fixes:
On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
On Darwin / Linux x86-32, v1i64 values are passed in memory.
On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50257 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td
index 8a580df..b2a02e4 100644
--- a/lib/Target/X86/X86CallingConv.td
+++ b/lib/Target/X86/X86CallingConv.td
@@ -133,12 +133,20 @@
// The first 8 FP/Vector arguments are passed in XMM registers.
CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
- CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
+ CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
- // The first 8 MMX vector arguments are passed in GPRs.
- CCIfType<[v8i8, v4i16, v2i32, v1i64],
- CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
+ // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
+ // registers on Darwin.
+ CCIfType<[v8i8, v4i16, v2i32],
+ CCIfSubtarget<"isTargetDarwin()",
+ CCIfSubtarget<"hasSSE2()",
+ CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
+ // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
+ CCIfType<[v1i64],
+ CCIfSubtarget<"isTargetDarwin()",
+ CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
+
// Integer/FP values get stored in stack slots that are 8 bytes in size and
// 8-byte aligned if there are no more registers to hold them.
CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
@@ -211,12 +219,19 @@
// The first 8 FP/Vector arguments are passed in XMM registers.
CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
- CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
+ CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
- // The first 8 MMX vector arguments are passed in GPRs.
- CCIfType<[v8i8, v4i16, v2i32, v1i64],
- CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
-
+ // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
+ // registers on Darwin.
+ CCIfType<[v8i8, v4i16, v2i32],
+ CCIfSubtarget<"isTargetDarwin()",
+ CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
+
+ // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
+ CCIfType<[v1i64],
+ CCIfSubtarget<"isTargetDarwin()",
+ CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
+
// Integer/FP values get stored in stack slots that are 8 bytes in size and
// 8-byte aligned if there are no more registers to hold them.
CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
@@ -242,9 +257,15 @@
// The first 3 float or double arguments, if marked 'inreg' and if the call
// is not a vararg call and if SSE2 is available, are passed in SSE registers.
- CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], CCIfSubtarget<"hasSSE2()",
+ CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
+ CCIfSubtarget<"hasSSE2()",
CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
+ // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
+ // registers if the call is not a vararg call.
+ CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32],
+ CCAssignToReg<[MM0, MM1, MM2]>>>,
+
// Integer/Float values get stored in stack slots that are 4 bytes in
// size and 4-byte aligned.
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
@@ -264,8 +285,7 @@
// __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
// passed in the parameter area.
- CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>
-]>;
+ CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
def CC_X86_32_C : CallingConv<[
// Promote i8/i16 arguments to i32.
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a0fd3d9..3894960 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1207,13 +1207,25 @@
RC = X86::FR32RegisterClass;
else if (RegVT == MVT::f64)
RC = X86::FR64RegisterClass;
- else {
- assert(MVT::isVector(RegVT));
- if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
- RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
- RegVT = MVT::i64;
- } else
- RC = X86::VR128RegisterClass;
+ else if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 128)
+ RC = X86::VR128RegisterClass;
+ else if (MVT::isVector(RegVT)) {
+ assert(MVT::getSizeInBits(RegVT) == 64);
+ if (!Is64Bit)
+ RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
+ else {
+ // Darwin calling convention passes MMX values in either GPRs or
+ // XMMs in x86-64. Other targets pass them in memory.
+ if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
+ RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
+ RegVT = MVT::v2i64;
+ } else {
+ RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
+ RegVT = MVT::i64;
+ }
+ }
+ } else {
+ assert(0 && "Unknown argument type!");
}
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);