ptx: add set.p instruction and related changes to predicate execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127577 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PTX/PTX.h b/lib/Target/PTX/PTX.h
index 6572791..49045cd 100644
--- a/lib/Target/PTX/PTX.h
+++ b/lib/Target/PTX/PTX.h
@@ -31,7 +31,7 @@
};
enum Predicate {
- PRED_IGNORE = 0,
+ PRED_NORMAL = 0,
PRED_NEGATE = 1
};
} // namespace PTX
diff --git a/lib/Target/PTX/PTXAsmPrinter.cpp b/lib/Target/PTX/PTXAsmPrinter.cpp
index 8b5ed45..087d4f9 100644
--- a/lib/Target/PTX/PTXAsmPrinter.cpp
+++ b/lib/Target/PTX/PTXAsmPrinter.cpp
@@ -410,7 +410,7 @@
DEBUG(dbgs() << "predicate: (" << reg << ", " << predOp << ")\n");
- if (reg && predOp != PTX::PRED_IGNORE) {
+ if (reg != PTX::NoRegister) {
O << '@';
if (predOp == PTX::PRED_NEGATE)
O << '!';
diff --git a/lib/Target/PTX/PTXInstrInfo.cpp b/lib/Target/PTX/PTXInstrInfo.cpp
index 8c2145d..0aebc82 100644
--- a/lib/Target/PTX/PTXInstrInfo.cpp
+++ b/lib/Target/PTX/PTXInstrInfo.cpp
@@ -100,10 +100,7 @@
bool PTXInstrInfo::isPredicated(const MachineInstr *MI) const {
int i = MI->findFirstPredOperandIdx();
- if (i == -1)
- llvm_unreachable("missing predicate operand");
- return MI->getOperand(i).getReg() ||
- MI->getOperand(i+1).getImm() != PTX::PRED_IGNORE;
+ return i != -1 && MI->getOperand(i).getReg() != PTX::NoRegister;
}
bool PTXInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
@@ -143,7 +140,29 @@
// If the specified instruction defines any predicate or condition code
// register(s) used for predication, returns true as well as the definition
// predicate(s) by reference.
- return false;
+
+ switch (MI->getOpcode()) {
+ default:
+ return false;
+ case PTX::SETPEQu32rr:
+ case PTX::SETPEQu32ri:
+ case PTX::SETPNEu32rr:
+ case PTX::SETPNEu32ri:
+ case PTX::SETPLTu32rr:
+ case PTX::SETPLTu32ri:
+ case PTX::SETPLEu32rr:
+ case PTX::SETPLEu32ri:
+ case PTX::SETPGTu32rr:
+ case PTX::SETPGTu32ri:
+ case PTX::SETPGEu32rr:
+ case PTX::SETPGEu32ri: {
+ const MachineOperand &MO = MI->getOperand(0);
+ assert(MO.isReg() && RI.getRegClass(MO.getReg()) == &PTX::PredsRegClass);
+ Pred.push_back(MO);
+ Pred.push_back(MachineOperand::CreateImm(PTX::PRED_NORMAL));
+ return true;
+ }
+ }
}
// static helper routines
@@ -151,8 +170,8 @@
MachineSDNode *PTXInstrInfo::
GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
DebugLoc dl, EVT VT, SDValue Op1) {
- SDValue predReg = DAG->getRegister(0, MVT::i1);
- SDValue predOp = DAG->getTargetConstant(PTX::PRED_IGNORE, MVT::i1);
+ SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
+ SDValue predOp = DAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32);
SDValue ops[] = { Op1, predReg, predOp };
return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops));
}
@@ -160,8 +179,8 @@
MachineSDNode *PTXInstrInfo::
GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) {
- SDValue predReg = DAG->getRegister(0, MVT::i1);
- SDValue predOp = DAG->getTargetConstant(PTX::PRED_IGNORE, MVT::i1);
+ SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
+ SDValue predOp = DAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32);
SDValue ops[] = { Op1, Op2, predReg, predOp };
return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops));
}
@@ -169,6 +188,6 @@
void PTXInstrInfo::AddDefaultPredicate(MachineInstr *MI) {
if (MI->findFirstPredOperandIdx() == -1) {
MI->addOperand(MachineOperand::CreateReg(0, /*IsDef=*/false));
- MI->addOperand(MachineOperand::CreateImm(PTX::PRED_IGNORE));
+ MI->addOperand(MachineOperand::CreateImm(PTX::PRED_NORMAL));
}
}
diff --git a/lib/Target/PTX/PTXInstrInfo.td b/lib/Target/PTX/PTXInstrInfo.td
index 0657994..a5f82f1 100644
--- a/lib/Target/PTX/PTXInstrInfo.td
+++ b/lib/Target/PTX/PTXInstrInfo.td
@@ -269,6 +269,18 @@
[(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
}
+multiclass PTX_SETP<RegisterClass RC, string regclsname, Operand immcls,
+ CondCode cmp, string cmpstr> {
+ def rr
+ : InstPTX<(outs Preds:$d), (ins RC:$a, RC:$b),
+ !strconcat("setp.", cmpstr, ".", regclsname, "\t$d, $a, $b"),
+ [(set Preds:$d, (setcc RC:$a, RC:$b, cmp))]>;
+ def ri
+ : InstPTX<(outs Preds:$d), (ins RC:$a, immcls:$b),
+ !strconcat("setp.", cmpstr, ".", regclsname, "\t$d, $a, $b"),
+ [(set Preds:$d, (setcc RC:$a, imm:$b, cmp))]>;
+}
+
multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
def rr32 : InstPTX<(outs RC:$d),
(ins MEMri32:$a),
@@ -343,6 +355,11 @@
// Instructions
//===----------------------------------------------------------------------===//
+///===- Integer Arithmetic Instructions -----------------------------------===//
+
+defm ADD : INT3<"add", add>;
+defm SUB : INT3<"sub", sub>;
+
///===- Floating-Point Arithmetic Instructions ----------------------------===//
// Standard Binary Operations
@@ -397,12 +414,14 @@
// TODO: Allow the rounding mode to be selectable through llc.
defm FMAD : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>;
+///===- Comparison and Selection Instructions -----------------------------===//
-
-///===- Integer Arithmetic Instructions -----------------------------------===//
-
-defm ADD : INT3<"add", add>;
-defm SUB : INT3<"sub", sub>;
+defm SETPEQu32 : PTX_SETP<RRegu32, "u32", i32imm, SETEQ, "eq">;
+defm SETPNEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETNE, "ne">;
+defm SETPLTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULT, "lt">;
+defm SETPLEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETULE, "le">;
+defm SETPGTu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGT, "gt">;
+defm SETPGEu32 : PTX_SETP<RRegu32, "u32", i32imm, SETUGE, "ge">;
///===- Logic and Shift Instructions --------------------------------------===//
@@ -475,6 +494,10 @@
// defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
// TODO: Do something with st.param if/when it is needed.
+def CVT_u32_pred
+ : InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
+ [(set RRegu32:$d, (zext Preds:$a))]>;
+
///===- Control Flow Instructions -----------------------------------------===//
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {