Be more clever about regclasses in ScheduleDAGSDNodes::EmitCopyFromReg.
If two uses of a CopyFromReg want different regclasses, first try a common
sub-class, then fall back on the copy emitted in AddRegisterOperand. There is
no need for an assert here. The cross-class joiner usually cleans up nicely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79193 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 12b5d14..17684f5 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -81,11 +81,11 @@
if (!UseRC)
UseRC = RC;
else if (RC) {
- if (UseRC->hasSuperClass(RC))
- UseRC = RC;
- else
- assert((UseRC == RC || RC->hasSuperClass(UseRC)) &&
- "Multiple uses expecting different register classes!");
+ const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
+ // If multiple uses expect disjoint register classes, we emit
+ // copies in AddRegisterOperand.
+ if (ComRC)
+ UseRC = ComRC;
}
}
}