remove explicit isStore flags that are now inferrable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45653 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 83d448b..4611a3e 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -278,7 +278,6 @@
"ldr $dst, $addr", []>;
} // isLoad
-let isStore = 1 in {
def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
[(store GPR:$src, t_addrmode_s4:$addr)]>;
@@ -295,6 +294,7 @@
"str $src, $addr",
[(store GPR:$src, t_addrmode_sp:$addr)]>;
+let isStore = 1 in {
// Special instruction for spill. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),