* Added instruction property hasCtrlDep for those which r/w control-flow
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24586 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 46a1b47..d4b83f4 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -163,6 +163,7 @@
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+ bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
InstrItinClass Itinerary; // Execution steps used for scheduling.
}