Revert the SelectionDAG optimization that makes
it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT. On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable. So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 9432a74..918db9d 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1775,9 +1775,8 @@
ArgValues.push_back(Root);
// Return the new list of results.
- std::vector<MVT> RetVT(Op.Val->value_begin(),
- Op.Val->value_end());
- return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
+ return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+ ArgValues.size());
}
/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
@@ -2557,8 +2556,8 @@
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
- SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
- &ResultVals[0], ResultVals.size());
+ SDOperand Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0],
+ ResultVals.size());
return Res.getValue(Op.ResNo);
}
@@ -2753,8 +2752,7 @@
};
SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
SDOperand OutOps[] = { Load, Store };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- OutOps, 2);
+ return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2);
}
SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
@@ -2796,8 +2794,7 @@
};
SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4);
SDOperand OutOps[] = { Load, Store };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- OutOps, 2);
+ return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2);
}
SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
@@ -2829,8 +2826,7 @@
};
SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
SDOperand OutOps[] = { Load, Store };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
- OutOps, 2);
+ return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2);
}
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
@@ -3134,8 +3130,7 @@
SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
SDOperand OutOps[] = { OutLo, OutHi };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
- OutOps, 2);
+ return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2);
}
SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
@@ -3163,8 +3158,7 @@
SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
SDOperand OutOps[] = { OutLo, OutHi };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
- OutOps, 2);
+ return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2);
}
SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
@@ -3192,8 +3186,7 @@
SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
Tmp4, Tmp6, ISD::SETLE);
SDOperand OutOps[] = { OutLo, OutHi };
- return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
- OutOps, 2);
+ return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2);
}
//===----------------------------------------------------------------------===//