diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index bd7d924..526964b 100644
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -1,10 +1,10 @@
 //===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements the MRegisterInfo interface.
@@ -38,6 +38,6 @@
       Allocatable[*I] = true;
   }
   return Allocatable;
-}  
+}
 
 } // End llvm namespace
diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp
index 395f25e..3c71fdc 100644
--- a/lib/Target/TargetData.cpp
+++ b/lib/Target/TargetData.cpp
@@ -1,10 +1,10 @@
 //===-- TargetData.cpp - Data size & alignment routines --------------------==//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines target properties related to datatype size/offset/alignment
@@ -43,7 +43,7 @@
   StructSize = 0;
 
   // Loop over each of the elements, placing them in memory...
-  for (StructType::element_iterator TI = ST->element_begin(), 
+  for (StructType::element_iterator TI = ST->element_begin(),
          TE = ST->element_end(); TI != TE; ++TI) {
     const Type *Ty = *TI;
     unsigned char A;
@@ -95,7 +95,7 @@
 TargetData::TargetData(const std::string &TargetName,
                        bool isLittleEndian, unsigned char PtrSize,
                        unsigned char PtrAl, unsigned char DoubleAl,
-                       unsigned char FloatAl, unsigned char LongAl, 
+                       unsigned char FloatAl, unsigned char LongAl,
                        unsigned char IntAl, unsigned char ShortAl,
                        unsigned char ByteAl, unsigned char BoolAl) {
 
@@ -205,7 +205,7 @@
     Size = Layout->StructSize; Alignment = Layout->StructAlignment;
     return;
   }
-    
+
   default:
     assert(0 && "Bad type for getTypeInfo!!!");
     return;
diff --git a/lib/Target/TargetFrameInfo.cpp b/lib/Target/TargetFrameInfo.cpp
index 07c1663..7255b32 100644
--- a/lib/Target/TargetFrameInfo.cpp
+++ b/lib/Target/TargetFrameInfo.cpp
@@ -1,10 +1,10 @@
 //===-- TargetFrameInfo.cpp - Implement machine frame interface -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // Implements the layout of a stack frame on the target machine.
@@ -22,7 +22,7 @@
 //===--------------------------------------------------------------------===//
 
 // This method adjusts a stack offset to meet alignment rules of target.
-int 
+int
 TargetFrameInfo::adjustAlignment(int unalignedOffset, bool growUp,
                                  unsigned align) const {
   abort();
@@ -33,7 +33,7 @@
 // function.  The frame contents are obtained from the MachineFunction object
 // for the given function.  The rest must be implemented by the
 // machine-specific subclass.
-// 
+//
 int
 TargetFrameInfo::getIncomingArgOffset(MachineFunction& mcInfo, unsigned argNum)
   const {
@@ -55,7 +55,7 @@
   return 0;
 }
 
-int 
+int
 TargetFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& growUp)
   const {
   abort();
@@ -68,7 +68,7 @@
   return 0;
 }
 
-int 
+int
 TargetFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo, bool& growUp)
   const {
   abort();
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index c0ae56b..677f36d 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -1,10 +1,10 @@
 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetInstrInfo class.
@@ -20,7 +20,7 @@
 namespace llvm {
   // External object describing the machine instructions Initialized only when
   // the TargetMachine class is created and reset when that class is destroyed.
-  // 
+  //
   // FIXME: UGLY SPARCV9 HACK!
   const TargetInstrDescriptor* TargetInstrDescriptors = 0;
 }
@@ -49,13 +49,13 @@
       // NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
       // SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
       // See CreateUIntSetInstruction in SparcInstrInfo.cpp.
-      
+
       // Now check if the constant fits
       if (intValue <= (int64_t) maxImmedValue &&
 	  intValue >= -((int64_t) maxImmedValue+1))
 	return true;
     }
-  
+
   return false;
 }
 
diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index fc7530a..8e96576 100644
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -1,10 +1,10 @@
 //===-- TargetMachine.cpp - General Target Information ---------------------==//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file describes the general parts of a Target machine.
@@ -32,7 +32,7 @@
     cl::desc("Print generated machine code"),
     cl::location(PrintMachineCode), cl::init(false));
 
-  cl::opt<bool, true> 
+  cl::opt<bool, true>
     DisableFPElim("disable-fp-elim",
                   cl::desc("Disable frame pointer elimination optimization"),
                   cl::location(NoFramePointerElim),
diff --git a/lib/Target/TargetMachineRegistry.cpp b/lib/Target/TargetMachineRegistry.cpp
index b5a3a55..f753a8c 100644
--- a/lib/Target/TargetMachineRegistry.cpp
+++ b/lib/Target/TargetMachineRegistry.cpp
@@ -1,10 +1,10 @@
 //===-- TargetMachineRegistry.cpp - Target Auto Registration Impl ---------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file exposes the RegisterTarget class, which TargetMachine
@@ -62,7 +62,7 @@
     return 0;
   } else if (UsableTargets.size() == 1)
     return UsableTargets.back().second;
-  
+
   // Otherwise, take the best target, but make sure we don't have to equally
   // good best targets.
   std::sort(UsableTargets.begin(), UsableTargets.end());
@@ -91,7 +91,7 @@
     return 0;
   } else if (UsableTargets.size() == 1)
     return UsableTargets.back().second;
-  
+
   // Otherwise, take the best target.  If there is a tie, just pick one.
   unsigned MaxQual = UsableTargets.front().first;
   const Entry *MaxQualTarget = UsableTargets.front().second;
@@ -101,7 +101,7 @@
       MaxQual = UsableTargets[i].first;
       MaxQualTarget = UsableTargets[i].second;
     }
-  
+
   return MaxQualTarget;
 }
-                                    
+
diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp
index b2f66db..940dab0 100644
--- a/lib/Target/TargetSchedInfo.cpp
+++ b/lib/Target/TargetSchedInfo.cpp
@@ -1,10 +1,10 @@
 //===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file implements the generic part of a Scheduler description for a
@@ -21,7 +21,7 @@
 
 resourceId_t llvm::CPUResource::nextId = 0;
 static std::vector<CPUResource*> *CPUResourceMap = 0;
-  
+
 CPUResource::CPUResource(const std::string& resourceName, int maxUsers)
     : rname(resourceName), rid(nextId++), maxNumUsers(maxUsers) {
   if(!CPUResourceMap)
@@ -45,8 +45,8 @@
 RUConflict(const std::vector<resourceId_t>& fromRVec,
 	   const std::vector<resourceId_t>& toRVec)
 {
-  
-  unsigned fN = fromRVec.size(), tN = toRVec.size(); 
+
+  unsigned fN = fromRVec.size(), tN = toRVec.size();
   unsigned fi = 0, ti = 0;
 
   while (fi < fN && ti < tN) {
@@ -62,14 +62,14 @@
 
 
 static CycleCount_t
-ComputeMinGap(const InstrRUsage &fromRU, 
+ComputeMinGap(const InstrRUsage &fromRU,
 	      const InstrRUsage &toRU)
 {
   CycleCount_t minGap = 0;
-  
+
   if (fromRU.numBubbles > 0)
     minGap = fromRU.numBubbles;
-  
+
   if (minGap < fromRU.numCycles) {
     // only need to check from cycle `minGap' onwards
     for (CycleCount_t gap=minGap; gap <= fromRU.numCycles-1; gap++) {
@@ -85,7 +85,7 @@
         }
     }
   }
-  
+
   return minGap;
 }
 
@@ -114,11 +114,11 @@
 {
   assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
 	 && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
-  
+
   // First, compute common resource usage info for each class because
   // most instructions will probably behave the same as their class.
   // Cannot allocate a vector of InstrRUsage so new each one.
-  // 
+  //
   std::vector<InstrRUsage> instrRUForClasses;
   instrRUForClasses.resize(numSchedClasses);
   for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) {
@@ -126,7 +126,7 @@
     instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
     instrRUForClasses[sc].setTo(classRUsages[sc]);
   }
-  
+
   computeInstrResources(instrRUForClasses);
   computeIssueGaps(instrRUForClasses);
 }
@@ -138,21 +138,21 @@
 {
   int numOpCodes =  mii->getNumOpcodes();
   instrRUsages.resize(numOpCodes);
-  
+
   // First get the resource usage information from the class resource usages.
   for (MachineOpCode op = 0; op < numOpCodes; ++op) {
     InstrSchedClass sc = getSchedClass(op);
     assert(sc < numSchedClasses);
     instrRUsages[op] = instrRUForClasses[sc];
   }
-  
+
   // Now, modify the resource usages as specified in the deltas.
   for (unsigned i = 0; i < numUsageDeltas; ++i) {
     MachineOpCode op = usageDeltas[i].opCode;
     assert(op < numOpCodes);
     instrRUsages[op].addUsageDelta(usageDeltas[i]);
   }
-  
+
   // Then modify the issue restrictions as specified in the deltas.
   for (unsigned i = 0; i < numIssueDeltas; ++i) {
     MachineOpCode op = issueDeltas[i].opCode;
@@ -173,14 +173,14 @@
   // First, compute issue gaps between pairs of classes based on common
   // resources usages for each class, because most instruction pairs will
   // usually behave the same as their class.
-  // 
+  //
   int* classPairGaps =
     static_cast<int*>(alloca(sizeof(int) * numSchedClasses * numSchedClasses));
   for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
     for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) {
       int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
                                        instrRUForClasses[toSC]);
-      classPairGaps[fromSC*numSchedClasses + toSC] = classPairGap; 
+      classPairGaps[fromSC*numSchedClasses + toSC] = classPairGap;
     }
 
   // Now, for each pair of instructions, use the class pair gap if both
@@ -191,7 +191,7 @@
 
   for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
     for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) {
-      int instrPairGap = 
+      int instrPairGap =
         (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
         ? classPairGaps[getSchedClass(fromOp)*numSchedClasses + getSchedClass(toOp)]
         : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
@@ -208,23 +208,23 @@
 void InstrRUsage::setTo(const InstrClassRUsage& classRU) {
   sameAsClass	= true;
   isSingleIssue = classRU.isSingleIssue;
-  breaksGroup   = classRU.breaksGroup; 
+  breaksGroup   = classRU.breaksGroup;
   numBubbles    = classRU.numBubbles;
-  
+
   for (unsigned i=0; i < classRU.numSlots; i++) {
     unsigned slot = classRU.feasibleSlots[i];
     assert(slot < feasibleSlots.size() && "Invalid slot specified!");
     this->feasibleSlots[slot] = true;
   }
-  
+
   numCycles   = classRU.totCycles;
   resourcesByCycle.resize(this->numCycles);
-  
+
   for (unsigned i=0; i < classRU.numRUEntries; i++)
     for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
 	 c < NC; c++)
       this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
-  
+
   // Sort each resource usage vector by resourceId_t to speed up conflict
   // checking
   for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
@@ -234,11 +234,11 @@
 // Add the extra resource usage requirements specified in the delta.
 // Note that a negative value of `numCycles' means one entry for that
 // resource should be deleted for each cycle.
-// 
+//
 void InstrRUsage::addUsageDelta(const InstrRUsageDelta &delta) {
   int NC = delta.numCycles;
   sameAsClass = false;
-  
+
   // resize the resources vector if more cycles are specified
   unsigned maxCycles = this->numCycles;
   maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1);
@@ -246,7 +246,7 @@
     this->resourcesByCycle.resize(maxCycles);
     this->numCycles = maxCycles;
   }
-    
+
   if (NC >= 0)
     for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
       this->resourcesByCycle[c].push_back(delta.resourceId);