R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 02d6fab..6d73590 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -70,6 +70,28 @@
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
setOperationAction(ISD::UREM, MVT::i32, Expand);
+
+ int types[] = {
+ (int)MVT::v2i32,
+ (int)MVT::v4i32
+ };
+ size_t NumTypes = sizeof(types) / sizeof(*types);
+
+ for (unsigned int x = 0; x < NumTypes; ++x) {
+ MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
+ //Expand the following operations for the current type by default
+ setOperationAction(ISD::ADD, VT, Expand);
+ setOperationAction(ISD::AND, VT, Expand);
+ setOperationAction(ISD::MUL, VT, Expand);
+ setOperationAction(ISD::OR, VT, Expand);
+ setOperationAction(ISD::SHL, VT, Expand);
+ setOperationAction(ISD::SRL, VT, Expand);
+ setOperationAction(ISD::SRA, VT, Expand);
+ setOperationAction(ISD::SUB, VT, Expand);
+ setOperationAction(ISD::UDIV, VT, Expand);
+ setOperationAction(ISD::UREM, VT, Expand);
+ setOperationAction(ISD::XOR, VT, Expand);
+ }
}
//===---------------------------------------------------------------------===//
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index cf349a8..18e83e8 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -38,30 +38,11 @@
setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
- setOperationAction(ISD::ADD, MVT::v4i32, Expand);
- setOperationAction(ISD::AND, MVT::v4i32, Expand);
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
- setOperationAction(ISD::MUL, MVT::v2i32, Expand);
- setOperationAction(ISD::MUL, MVT::v4i32, Expand);
- setOperationAction(ISD::OR, MVT::v4i32, Expand);
- setOperationAction(ISD::OR, MVT::v2i32, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
- setOperationAction(ISD::SHL, MVT::v4i32, Expand);
- setOperationAction(ISD::SHL, MVT::v2i32, Expand);
- setOperationAction(ISD::SRL, MVT::v4i32, Expand);
- setOperationAction(ISD::SRL, MVT::v2i32, Expand);
- setOperationAction(ISD::SRA, MVT::v4i32, Expand);
- setOperationAction(ISD::SRA, MVT::v2i32, Expand);
- setOperationAction(ISD::SUB, MVT::v4i32, Expand);
- setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
- setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
- setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
- setOperationAction(ISD::UREM, MVT::v4i32, Expand);
setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
- setOperationAction(ISD::XOR, MVT::v4i32, Expand);
- setOperationAction(ISD::XOR, MVT::v2i32, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Expand);
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index e70c7de..9d4cfef 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -65,36 +65,6 @@
setOperationAction(ISD::ADD, MVT::i64, Legal);
setOperationAction(ISD::ADD, MVT::i32, Legal);
- setOperationAction(ISD::ADD, MVT::v4i32, Expand);
- setOperationAction(ISD::ADD, MVT::v2i32, Expand);
-
- setOperationAction(ISD::AND, MVT::v2i32, Expand);
- setOperationAction(ISD::AND, MVT::v4i32, Expand);
-
- setOperationAction(ISD::MUL, MVT::v2i32, Expand);
- setOperationAction(ISD::MUL, MVT::v4i32, Expand);
-
- setOperationAction(ISD::OR, MVT::v2i32, Expand);
- setOperationAction(ISD::OR, MVT::v4i32, Expand);
-
- setOperationAction(ISD::SHL, MVT::v2i32, Expand);
- setOperationAction(ISD::SHL, MVT::v4i32, Expand);
- setOperationAction(ISD::SRL, MVT::v4i32, Expand);
- setOperationAction(ISD::SRL, MVT::v2i32, Expand);
- setOperationAction(ISD::SRA, MVT::v4i32, Expand);
- setOperationAction(ISD::SRA, MVT::v2i32, Expand);
-
- setOperationAction(ISD::SUB, MVT::v2i32, Expand);
- setOperationAction(ISD::SUB, MVT::v4i32, Expand);
-
- setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
- setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
-
- setOperationAction(ISD::UREM, MVT::v2i32, Expand);
- setOperationAction(ISD::UREM, MVT::v4i32, Expand);
-
- setOperationAction(ISD::XOR, MVT::v2i32, Expand);
- setOperationAction(ISD::XOR, MVT::v4i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);