repair x86 performance, dejagnu problems from previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35245 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index e0d6740..71923b6 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -883,7 +883,8 @@
/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
/// and GV works for isLegalAddressImmediate _and_ both can be applied
/// simultaneously to the same instruction.
- virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV) const;
+ virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
+ const Type* Ty) const;
//===--------------------------------------------------------------------===//
// Div utility functions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 83bca75..718d983 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1969,8 +1969,8 @@
/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
/// and GV works for isLegalAddressImmediate _and_ both can be applied
/// simultaneously to the same instruction.
-bool TargetLowering::isLegalAddressScaleAndImm(int64_t S,
- GlobalValue *GV) const {
+bool TargetLowering::isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
+ const Type* Ty) const {
return false;
}
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 17a41c5..2521e3b 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1392,8 +1392,8 @@
/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
/// and GV works for isLegalAddressImmediate _and_ both can be applied
/// simultaneously to the same instruction.
-bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S,
- GlobalValue *GV) const {
+bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
+ const Type* Ty) const {
return false;
}
diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 1675e9c..2c2a2cd 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -109,7 +109,8 @@
/// isLegalAddressScaleAndImm - Return true if S works for
/// IsLegalAddressScale and GV works for isLegalAddressImmediate _and_
/// both can be applied simultaneously to the same instruction.
- virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV) const;
+ virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
+ const Type *Ty) const;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1174482..e178646 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4064,6 +4064,22 @@
}
}
+/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
+/// and V works for isLegalAddressImmediate _and_ both can be applied
+/// simultaneously to the same instruction.
+bool X86TargetLowering::isLegalAddressScaleAndImm(int64_t S, int64_t V,
+ const Type* Ty) const {
+ return isLegalAddressScale(S, Ty) && isLegalAddressImmediate(V, Ty);
+}
+
+/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
+/// and GV works for isLegalAddressImmediate _and_ both can be applied
+/// simultaneously to the same instruction.
+bool X86TargetLowering::isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
+ const Type* Ty) const {
+ return isLegalAddressScale(S, Ty) && isLegalAddressImmediate(GV);
+}
+
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 120da0f..3ed8d18 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -349,6 +349,18 @@
/// type.
virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
+ /// isLegalAddressScaleAndImm - Return true if S works for
+ /// IsLegalAddressScale and V works for isLegalAddressImmediate _and_
+ /// both can be applied simultaneously to the same instruction.
+ virtual bool isLegalAddressScaleAndImm(int64_t S, int64_t V,
+ const Type *Ty) const;
+
+ /// isLegalAddressScaleAndImm - Return true if S works for
+ /// IsLegalAddressScale and GV works for isLegalAddressImmediate _and_
+ /// both can be applied simultaneously to the same instruction.
+ virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
+ const Type *Ty) const;
+
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask