CellSPU: Fix mnemonic typo in pattern; "shlqbyi" -> "shlqby".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59998 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 0b95474..6e64cae 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -177,7 +177,9 @@
setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+#if 0
setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
+#endif
// SPU has no intrinsics for these particular operations:
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 1d7800e..227b672 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -1982,7 +1982,7 @@
// not by bits. See notes above on SHLQBI.
class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
- RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
+ RI7Form<0b11111011100, OOL, IOL, "shlqby\t$rT, $rA, $rB",
RotateShift, pattern>;
class SHLQBYVecInst<ValueType vectype>: