commit fc91114a2e622776d003d121eebc3c1b79f418f3
author Evan Cheng <evan.cheng@apple.com> Mon Mar 22 18:40:50 2010 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Mar 22 18:40:50 2010 +0000
tree 7fcb89b264a8308892d5969340b9229801d9a90f
parent 052ba45bf85a3cdffdbdd016a78bafe03ed40e82

80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99195 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/ScheduleDAGInstrs.cpp

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index e532ade..1906bf0 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -528,7 +528,8 @@
   MachineInstr *DefMI = Def->getInstr();
   int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
   if (DefIdx != -1) {
-    int DefCycle = InstrItins.getOperandCycle(DefMI->getDesc().getSchedClass(), DefIdx);
+    int DefCycle = InstrItins.getOperandCycle(DefMI->getDesc().getSchedClass(),
+                                              DefIdx);
     if (DefCycle >= 0) {
       MachineInstr *UseMI = Use->getInstr();
       const unsigned UseClass = UseMI->getDesc().getSchedClass();