commit fce587e58b88d1a10921c09acc6951b2e38d76f6
author Andrew Lenharth <andrewl@lenharth.org> Wed Jun 29 00:39:17 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Wed Jun 29 00:39:17 2005 +0000
tree 33251cc3385e7d180c94f2105a95027533be4f56
parent c7989cef9d5cff8172bec2fb2dd9e41d6d3b4221

support more relocations for stores also


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22306 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 112872c..eef0d84 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -855,6 +855,13 @@
   case Alpha::LDL: return Alpha::LDLr;
   case Alpha::LDBU: return Alpha::LDBUr;
   case Alpha::LDWU: return Alpha::LDWUr;
+  case Alpha::STB: return Alpha::STBr;
+  case Alpha::STW: return Alpha::STWr;
+  case Alpha::STL: return Alpha::STLr;
+  case Alpha::STQ: return Alpha::STQr;
+  case Alpha::STS: return Alpha::STSr;
+  case Alpha::STT: return Alpha::STTr;
+
   }
 }
 
@@ -2302,7 +2309,24 @@
         j = getFunctionOffset(BB->getParent()->getFunction());
       }
 
-      if(Address.getOpcode() == ISD::FrameIndex) {
+      if (GlobalAddressSDNode *GASD = 
+          dyn_cast<GlobalAddressSDNode>(Address)) {
+        if (GASD->getGlobal()->isExternal()) {
+          Tmp2 = SelectExpr(Address);
+          if (EnableAlphaLSMark)
+            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
+        } else {
+          Tmp2 = MakeReg(MVT::i64);
+          AlphaLowering.restoreGP(BB);
+          BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
+            .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
+          if (EnableAlphaLSMark)
+            BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+          BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
+            .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
+        }
+      } else if(Address.getOpcode() == ISD::FrameIndex) {
         if (EnableAlphaLSMark)
           BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
         BuildMI(BB, Opc, 3).addReg(Tmp1)

lib/Target/Alpha/AlphaInstrInfo.td

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 25f47b6..b7489fb 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -350,6 +350,17 @@
 //Load quad, rellocated literal form
 def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
 
+//Stores, int
+def STBr : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB) !gprellow">; // Store byte
+def STWr : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB) !gprellow">; // Store word
+def STLr : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB) !gprellow">; // Store longword
+def STQr : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB) !gprellow">; //Store quadword
+
+//Stores, float
+def STSr : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
+def STTr : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
+
+
 //Branches, int
 def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
 def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero