misched: Better handling of invalid latencies in the machine model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166107 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/TargetSchedule.cpp b/lib/CodeGen/TargetSchedule.cpp
index 7a6e260..6a096a1 100644
--- a/lib/CodeGen/TargetSchedule.cpp
+++ b/lib/CodeGen/TargetSchedule.cpp
@@ -58,6 +58,14 @@
return MI->isTransient() ? 0 : 1;
}
+// The machine model may explicitly specify an invalid latency, which
+// effectively means infinite latency. Since users of the TargetSchedule API
+// don't know how to handle this, we convert it to a very large latency that is
+// easy to distinguish when debugging the DAG but won't induce overflow.
+static unsigned convertLatency(int Cycles) {
+ return Cycles >= 0 ? Cycles : 1000;
+}
+
/// If we can determine the operand latency from the def only, without machine
/// model or itinerary lookup, do so. Otherwise return -1.
int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
@@ -178,7 +186,7 @@
const MCWriteLatencyEntry *WLEntry =
STI->getWriteLatencyEntry(SCDesc, DefIdx);
unsigned WriteID = WLEntry->WriteResourceID;
- unsigned Latency = WLEntry->Cycles;
+ unsigned Latency = convertLatency(WLEntry->Cycles);
if (!UseMI)
return Latency;
@@ -219,7 +227,7 @@
// Lookup the definition's write latency in SubtargetInfo.
const MCWriteLatencyEntry *WLEntry =
STI->getWriteLatencyEntry(SCDesc, DefIdx);
- Latency = std::max(Latency, WLEntry->Cycles);
+ Latency = std::max(Latency, convertLatency(WLEntry->Cycles));
}
return Latency;
}