commit fe05d98c253676d1ae6e0f03efde6b75fdae105d
author Andrew Trick <atrick@apple.com> Wed Oct 03 23:06:25 2012 +0000
committer Andrew Trick <atrick@apple.com> Wed Oct 03 23:06:25 2012 +0000
tree f60826629a442cb274bdad112a707241e65175f1
parent d494a3bfc5a4c9a335775669cfd6d804bc88d00a

Cleanup TableGen subtarget emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenSchedule.cpp

diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index e54202e..15af7a8 100644
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -72,9 +72,6 @@
   // Infer new SchedClasses from SchedVariant.
   inferSchedClasses();
 
-  DEBUG(for (unsigned i = 0; i < SchedClasses.size(); ++i)
-          SchedClasses[i].dump(this));
-
   // Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and
   // ProcResourceDefs.
   collectProcResources();
@@ -475,7 +472,7 @@
            RWI != RWE; ++RWI) {
         const CodeGenProcModel &ProcModel =
           getProcModel((*RWI)->getValueAsDef("SchedModel"));
-        dbgs() << "InstrRW on " << ProcModel.ModelName << " for " << InstName;
+        dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
         IdxVec Writes;
         IdxVec Reads;
         findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),