Restore minor deletion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70892 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
index 848f45e..8ca8590 100644
--- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
+++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
@@ -3262,11 +3262,12 @@
// Assumes in correct section after the entry point.
EmitLabel("func_begin", ++SubprogramCount);
- // Emit label for the implicitly defined dbg.stoppoint at the start of
- // the function.
- if (!Lines.empty()) {
- const SrcLineInfo &LineInfo = Lines[0];
- Asm->printLabel(LineInfo.getLabelID());
+ DebugLoc FDL = MF->getDefaultDebugLoc();
+ if (!FDL.isUnknown()) {
+ DebugLocTuple DLT = MF->getDebugLocTuple(FDL);
+ unsigned LabelID = RecordSourceLine(DLT.Line, DLT.Col,
+ DICompileUnit(DLT.CompileUnit));
+ Asm->printLabel(LabelID);
}
if (TimePassesIsEnabled)
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index afcda1f..f710051 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -333,11 +333,6 @@
unsigned Col = SPI->getColumn();
unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
setCurDebugLoc(DebugLoc::get(Idx));
- if (DW && DW->ShouldEmitDwarfDebug()) {
- unsigned ID = DW->RecordSourceLine(Line, Col, CU);
- const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
- BuildMI(MBB, DL, II).addImm(ID);
- }
}
return true;
}
@@ -402,7 +397,7 @@
CompileUnit.getGV(), Line, 0)));
if (DW && DW->ShouldEmitDwarfDebug()) {
- unsigned LabelID = DW->RecordSourceLine(Line, 0, CompileUnit);
+ unsigned LabelID = MMI->NextLabelID();
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
BuildMI(MBB, DL, II).addImm(LabelID);
DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
@@ -414,10 +409,9 @@
} else {
// Record the source line.
unsigned Line = Subprogram.getLineNumber();
- setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
+ MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
CompileUnit.getGV(), Line, 0)));
if (DW && DW->ShouldEmitDwarfDebug()) {
- DW->RecordSourceLine(Line, 0, CompileUnit);
// llvm.dbg.func_start also defines beginning of function scope.
DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index acdb043..fc45bbd 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -3980,7 +3980,7 @@
MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0)));
if (DW && DW->ShouldEmitDwarfDebug()) {
- unsigned LabelID = DW->RecordSourceLine(Line, 0, CompileUnit);
+ unsigned LabelID = DAG.getMachineModuleInfo()->NextLabelID();
DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
getRoot(), LabelID));
DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
@@ -3992,10 +3992,9 @@
} else {
// Record the source line.
unsigned Line = Subprogram.getLineNumber();
- setCurDebugLoc(DebugLoc::get(
+ MF.setDefaultDebugLoc(DebugLoc::get(
MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0)));
if (DW && DW->ShouldEmitDwarfDebug()) {
- DW->RecordSourceLine(Line, 0, CompileUnit);
// llvm.dbg.func_start also defines beginning of function scope.
DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
}
diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp
index 6406b1c..dd36bdd 100644
--- a/lib/CodeGen/StackSlotColoring.cpp
+++ b/lib/CodeGen/StackSlotColoring.cpp
@@ -232,61 +232,54 @@
int SS = li->getStackSlotIndex();
if (!UsedColors[SS])
continue;
- // Get the largest common sub- register class of all the stack slots that
- // are colored to this stack slot.
- const TargetRegisterClass *RC = 0;
- for (unsigned j = 0, ee = RevMap[SS].size(); j != ee; ++j) {
- int RSS = RevMap[SS][j];
- const TargetRegisterClass *RRC = LS->getIntervalRegClass(RSS);
- if (!RC)
- RC = RRC;
- else
- RC = getCommonSubClass(RC, RRC);
- }
- // If it's not colored to another stack slot, try coloring it
- // to a "free" register.
- if (!RC)
- continue;
- unsigned Reg = VRM->getFirstUnusedRegister(RC);
- if (!Reg)
- continue;
- bool IsSafe = true;
+ // These slots allow to share the same registers.
+ bool AllColored = true;
+ SmallVector<unsigned, 4> ColoredRegs;
for (unsigned j = 0, ee = RevMap[SS].size(); j != ee; ++j) {
int RSS = RevMap[SS][j];
+ const TargetRegisterClass *RC = LS->getIntervalRegClass(RSS);
+ // If it's not colored to another stack slot, try coloring it
+ // to a "free" register.
+ if (!RC) {
+ AllColored = false;
+ continue;
+ }
+ unsigned Reg = VRM->getFirstUnusedRegister(RC);
+ if (!Reg) {
+ AllColored = false;
+ continue;
+ }
if (!AllMemRefsCanBeUnfolded(RSS)) {
- IsSafe = false;
- break;
+ AllColored = false;
+ continue;
+ } else {
+ DOUT << "Assigning fi#" << RSS << " to " << TRI->getName(Reg) << '\n';
+ ColoredRegs.push_back(Reg);
+ SlotMapping[RSS] = Reg;
+ SlotIsReg.set(RSS);
+ Changed = true;
}
}
- if (!IsSafe)
- // Try color the next spill slot.
- continue;
- DOUT << "Assigning fi#" << SS << " to " << TRI->getName(Reg)
- << ", which in turn means...\n";
// Register and its sub-registers are no longer free.
- VRM->setRegisterUsed(Reg);
- // If reg is a callee-saved register, it will have to be spilled in
- // the prologue.
- MRI->setPhysRegUsed(Reg);
- for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
- VRM->setRegisterUsed(*AS);
- MRI->setPhysRegUsed(*AS);
+ while (!ColoredRegs.empty()) {
+ unsigned Reg = ColoredRegs.back();
+ ColoredRegs.pop_back();
+ VRM->setRegisterUsed(Reg);
+ // If reg is a callee-saved register, it will have to be spilled in
+ // the prologue.
+ MRI->setPhysRegUsed(Reg);
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
+ VRM->setRegisterUsed(*AS);
+ MRI->setPhysRegUsed(*AS);
+ }
}
// This spill slot is dead after the rewrites
- MFI->RemoveStackObject(SS);
-
- // Remember all these FI references will have to be unfolded.
- for (unsigned j = 0, ee = RevMap[SS].size(); j != ee; ++j) {
- int RSS = RevMap[SS][j];
- DOUT << " Assigning fi#" << RSS << " to " << TRI->getName(Reg) << '\n';
- SlotMapping[RSS] = Reg;
- SlotIsReg.set(RSS);
+ if (AllColored) {
+ MFI->RemoveStackObject(SS);
+ ++NumEliminated;
}
-
- ++NumEliminated;
- Changed = true;
}
DOUT << '\n';
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index f2f6ab0..29637b9 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
@@ -51,6 +52,7 @@
bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
TII = mf.getTarget().getInstrInfo();
+ TRI = mf.getTarget().getRegisterInfo();
MF = &mf;
ReMatId = MAX_STACK_SLOT+1;
@@ -73,6 +75,13 @@
SpillSlotToUsesMap.resize(8);
ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1-
TargetRegisterInfo::FirstVirtualRegister);
+
+ allocatableRCRegs.clear();
+ for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+ E = TRI->regclass_end(); I != E; ++I)
+ allocatableRCRegs.insert(std::make_pair(*I,
+ TRI->getAllocatableSet(mf, *I)));
+
grow();
return false;
diff --git a/lib/CodeGen/VirtRegMap.h b/lib/CodeGen/VirtRegMap.h
index 91c8322..507557d 100644
--- a/lib/CodeGen/VirtRegMap.h
+++ b/lib/CodeGen/VirtRegMap.h
@@ -32,6 +32,7 @@
class MachineInstr;
class MachineFunction;
class TargetInstrInfo;
+ class TargetRegisterInfo;
class VirtRegMap : public MachineFunctionPass {
public:
@@ -47,8 +48,11 @@
private:
const TargetInstrInfo *TII;
-
+ const TargetRegisterInfo *TRI;
MachineFunction *MF;
+
+ DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
+
/// Virt2PhysMap - This is a virtual to physical register
/// mapping. Each virtual register is required to have an entry in
/// it; even spilled virtual registers (the register mapped to a
@@ -466,7 +470,7 @@
unsigned getFirstUnusedRegister(const TargetRegisterClass *RC) {
int Reg = UnusedRegs.find_first();
while (Reg != -1) {
- if (RC->contains(Reg))
+ if (allocatableRCRegs[RC][Reg])
return (unsigned)Reg;
Reg = UnusedRegs.find_next(Reg);
}