Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h
index c66150b..a9e4637 100644
--- a/include/llvm/MC/MCSubtargetInfo.h
+++ b/include/llvm/MC/MCSubtargetInfo.h
@@ -34,7 +34,8 @@
const unsigned *ForwardingPathes; // Forwarding pathes
unsigned NumFeatures; // Number of processor features
unsigned NumProcs; // Number of processors
- uint64_t FeatureBits; // Feature bits for current CPU
+
+ uint64_t FeatureBits; // Feature bits for current CPU + FS
public:
void InitMCSubtargetInfo(StringRef CPU, StringRef FS,
@@ -54,6 +55,14 @@
/// feature string), recompute and return feature bits.
uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
+ /// ToggleFeature - Toggle a feature and returns the re-computed feature
+ /// bits. This version does not change the implied bits.
+ uint64_t ToggleFeature(uint64_t FB);
+
+ /// ToggleFeature - Toggle a feature and returns the re-computed feature
+ /// bits. This version will also change all implied bits.
+ uint64_t ToggleFeature(StringRef FS);
+
/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
///
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
diff --git a/include/llvm/MC/SubtargetFeature.h b/include/llvm/MC/SubtargetFeature.h
index fccff03..1a7dc92 100644
--- a/include/llvm/MC/SubtargetFeature.h
+++ b/include/llvm/MC/SubtargetFeature.h
@@ -82,6 +82,12 @@
/// Adding Features.
void AddFeature(const StringRef String, bool IsEnabled = true);
+ /// ToggleFeature - Toggle a feature and returns the newly updated feature
+ /// bits.
+ uint64_t ToggleFeature(uint64_t Bits, const StringRef String,
+ const SubtargetFeatureKV *FeatureTable,
+ size_t FeatureTableSize);
+
/// Get feature bits of a CPU.
uint64_t getFeatureBits(const StringRef CPU,
const SubtargetFeatureKV *CPUTable,
diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h
index 1686703..679b612 100644
--- a/include/llvm/Target/TargetRegistry.h
+++ b/include/llvm/Target/TargetRegistry.h
@@ -36,6 +36,7 @@
class MCInstrInfo;
class MCRegisterInfo;
class MCStreamer;
+ class MCSubtargetInfo;
class TargetAsmBackend;
class TargetAsmLexer;
class TargetAsmParser;
@@ -69,6 +70,9 @@
StringRef TT);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
+ typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
+ StringRef CPU,
+ StringRef Features);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &CPU,
@@ -79,8 +83,7 @@
const std::string &TT);
typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
const MCAsmInfo &MAI);
- typedef TargetAsmParser *(*AsmParserCtorTy)(StringRef TT,
- StringRef CPU, StringRef Features,
+ typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI,
MCAsmParser &P);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
@@ -137,6 +140,10 @@
/// if registered.
MCRegInfoCtorFnTy MCRegInfoCtorFn;
+ /// MCSubtargetInfoCtorFn - Constructor function for this target's
+ /// MCSubtargetInfo, if registered.
+ MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
+
/// TargetMachineCtorFn - Construction function for this target's
/// TargetMachine, if registered.
TargetMachineCtorTy TargetMachineCtorFn;
@@ -262,6 +269,22 @@
return MCRegInfoCtorFn();
}
+ /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
+ ///
+ /// \arg Triple - This argument is used to determine the target machine
+ /// feature set; it should always be provided. Generally this should be
+ /// either the target triple from the module, or the target triple of the
+ /// host if that does not exist.
+ /// \arg CPU - This specifies the name of the target CPU.
+ /// \arg Features - This specifies the string representation of the
+ /// additional target features.
+ MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
+ StringRef Features) const {
+ if (!MCSubtargetInfoCtorFn)
+ return 0;
+ return MCSubtargetInfoCtorFn(Triple, CPU, Features);
+ }
+
/// createTargetMachine - Create a target specific machine implementation
/// for the specified \arg Triple.
///
@@ -299,12 +322,11 @@
///
/// \arg Parser - The target independent parser implementation to use for
/// parsing and lexing.
- TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
- StringRef Features,
+ TargetAsmParser *createAsmParser(MCSubtargetInfo &STI,
MCAsmParser &Parser) const {
if (!AsmParserCtorFn)
return 0;
- return AsmParserCtorFn(Triple, CPU, Features, Parser);
+ return AsmParserCtorFn(STI, Parser);
}
/// createAsmPrinter - Create a target specific assembly printer pass. This
@@ -506,6 +528,22 @@
T.MCRegInfoCtorFn = Fn;
}
+ /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
+ /// the given target.
+ ///
+ /// Clients are responsible for ensuring that registration doesn't occur
+ /// while another thread is attempting to access the registry. Typically
+ /// this is done by initializing all targets at program startup.
+ ///
+ /// @param T - The target being registered.
+ /// @param Fn - A function to construct a MCSubtargetInfo for the target.
+ static void RegisterMCSubtargetInfo(Target &T,
+ Target::MCSubtargetInfoCtorFnTy Fn) {
+ // Ignore duplicate registration.
+ if (!T.MCSubtargetInfoCtorFn)
+ T.MCSubtargetInfoCtorFn = Fn;
+ }
+
/// RegisterTargetMachine - Register a TargetMachine implementation for the
/// given target.
///
@@ -782,6 +820,40 @@
}
};
+ /// RegisterMCSubtargetInfo - Helper template for registering a target
+ /// subtarget info implementation. This invokes the static "Create" method
+ /// on the class to actually do the construction. Usage:
+ ///
+ /// extern "C" void LLVMInitializeFooTarget() {
+ /// extern Target TheFooTarget;
+ /// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
+ /// }
+ template<class MCSubtargetInfoImpl>
+ struct RegisterMCSubtargetInfo {
+ RegisterMCSubtargetInfo(Target &T) {
+ TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
+ }
+ private:
+ static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ return new MCSubtargetInfoImpl();
+ }
+ };
+
+ /// RegisterMCSubtargetInfoFn - Helper template for registering a target
+ /// subtarget info implementation. This invokes the specified function to
+ /// do the construction. Usage:
+ ///
+ /// extern "C" void LLVMInitializeFooTarget() {
+ /// extern Target TheFooTarget;
+ /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
+ /// }
+ struct RegisterMCSubtargetInfoFn {
+ RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
+ TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
+ }
+ };
+
/// RegisterTargetMachine - Helper template for registering a target machine
/// implementation, for use in the target machine initialization
/// function. Usage:
@@ -859,9 +931,8 @@
}
private:
- static TargetAsmParser *Allocator(StringRef TT, StringRef CPU,
- StringRef FS, MCAsmParser &P) {
- return new AsmParserImpl(TT, CPU, FS, P);
+ static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
+ return new AsmParserImpl(STI, P);
}
};
diff --git a/include/llvm/Target/TargetSelect.h b/include/llvm/Target/TargetSelect.h
index c5ab90b..7b969d0 100644
--- a/include/llvm/Target/TargetSelect.h
+++ b/include/llvm/Target/TargetSelect.h
@@ -26,6 +26,10 @@
#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target();
#include "llvm/Config/Targets.def"
+#define LLVM_TARGET(TargetName) \
+ void LLVMInitialize##TargetName##MCSubtargetInfo();
+#include "llvm/Config/Targets.def"
+
// Declare all of the available assembly printer initialization functions.
#define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter();
#include "llvm/Config/AsmPrinters.def"
@@ -35,7 +39,8 @@
#include "llvm/Config/AsmParsers.def"
// Declare all of the available disassembler initialization functions.
-#define LLVM_DISASSEMBLER(TargetName) void LLVMInitialize##TargetName##Disassembler();
+#define LLVM_DISASSEMBLER(TargetName) \
+ void LLVMInitialize##TargetName##Disassembler();
#include "llvm/Config/Disassemblers.def"
}
@@ -63,6 +68,16 @@
#include "llvm/Config/Targets.def"
}
+ /// InitializeAllMCSubtargetInfos - The main program should call this function
+ /// if it wants access to all available subtarget infos for targets that LLVM
+ /// is configured to support, to make them available via the TargetRegistry.
+ ///
+ /// It is legal for a client to make multiple calls to this function.
+ inline void InitializeAllMCSubtargetInfos() {
+#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCSubtargetInfo();
+#include "llvm/Config/Targets.def"
+ }
+
/// InitializeAllAsmPrinters - The main program should call this function if
/// it wants all asm printers that LLVM is configured to support, to make them
/// available via the TargetRegistry.
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
index dc84385..5ac455e 100644
--- a/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
+++ b/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Target/TargetMachine.h"
@@ -112,11 +113,15 @@
OutContext, OutStreamer,
*MAI));
- OwningPtr<TargetAsmParser>
- TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),
- TM.getTargetCPU(),
- TM.getTargetFeatureString(),
- *Parser));
+ // FIXME: It would be nice if we can avoid createing a new instance of
+ // MCSubtargetInfo here given TargetSubtargetInfo is available. However,
+ // we have to watch out for asm directives which can change subtarget
+ // state. e.g. .code 16, .code 32.
+ OwningPtr<MCSubtargetInfo>
+ STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
+ TM.getTargetCPU(),
+ TM.getTargetFeatureString()));
+ OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*STI, *Parser));
if (!TAP)
report_fatal_error("Inline asm not supported by this streamer because"
" we don't have an asm parser for this target\n");
diff --git a/lib/MC/MCDisassembler/EDDisassembler.cpp b/lib/MC/MCDisassembler/EDDisassembler.cpp
index a39f002..77c959f 100644
--- a/lib/MC/MCDisassembler/EDDisassembler.cpp
+++ b/lib/MC/MCDisassembler/EDDisassembler.cpp
@@ -23,6 +23,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
@@ -373,7 +374,8 @@
*AsmInfo));
StringRef triple = tripleFromArch(Key.Arch);
- OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "",
+ OwningPtr<MCSubtargetInfo> STI(Tgt->createMCSubtargetInfo(triple, "", ""));
+ OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*STI,
*genericParser));
AsmToken OpcodeToken = genericParser->Lex();
diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp
index 3bb20b0..b1b86fe 100644
--- a/lib/MC/MCSubtargetInfo.cpp
+++ b/lib/MC/MCSubtargetInfo.cpp
@@ -48,6 +48,23 @@
return FeatureBits;
}
+/// ToggleFeature - Toggle a feature and returns the re-computed feature
+/// bits. This version does not change the implied bits.
+uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
+ FeatureBits ^= FB;
+ return FeatureBits;
+}
+
+/// ToggleFeature - Toggle a feature and returns the re-computed feature
+/// bits. This version will also change all implied bits.
+uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
+ SubtargetFeatures Features;
+ FeatureBits = Features.ToggleFeature(FeatureBits, FS,
+ ProcFeatures, NumFeatures);
+ return FeatureBits;
+}
+
+
InstrItineraryData
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
assert(ProcItins && "Instruction itineraries information not available!");
diff --git a/lib/MC/SubtargetFeature.cpp b/lib/MC/SubtargetFeature.cpp
index 951e0aa..348cd4c 100644
--- a/lib/MC/SubtargetFeature.cpp
+++ b/lib/MC/SubtargetFeature.cpp
@@ -224,6 +224,38 @@
}
}
+/// ToggleFeature - Toggle a feature and returns the newly updated feature
+/// bits.
+uint64_t
+SubtargetFeatures::ToggleFeature(uint64_t Bits, const StringRef Feature,
+ const SubtargetFeatureKV *FeatureTable,
+ size_t FeatureTableSize) {
+ // Find feature in table.
+ const SubtargetFeatureKV *FeatureEntry =
+ Find(StripFlag(Feature), FeatureTable, FeatureTableSize);
+ // If there is a match
+ if (FeatureEntry) {
+ if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) {
+ Bits &= ~FeatureEntry->Value;
+
+ // For each feature that implies this, clear it.
+ ClearImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize);
+ } else {
+ Bits |= FeatureEntry->Value;
+
+ // For each feature that this implies, set it.
+ SetImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize);
+ }
+ } else {
+ errs() << "'" << Feature
+ << "' is not a recognized feature for this target"
+ << " (ignoring feature)\n";
+ }
+
+ return Bits;
+}
+
+
/// getFeatureBits - Get feature bits a CPU.
///
uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index f927abb..d8fd809 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -41,12 +41,8 @@
class ARMOperand;
class ARMAsmParser : public TargetAsmParser {
+ MCSubtargetInfo &STI;
MCAsmParser &Parser;
- /// STI, ARM_STI, Thumb_STI - Subtarget info for ARM and Thumb modes. STI
- /// points to either ARM_STI or Thumb_STI depending on the mode.
- const MCSubtargetInfo *STI;
- OwningPtr<const MCSubtargetInfo> ARM_STI;
- OwningPtr<const MCSubtargetInfo> Thumb_STI;
MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -91,14 +87,14 @@
bool isThumb() const {
// FIXME: Can tablegen auto-generate this?
- return (STI->getFeatureBits() & ARM::ModeThumb) != 0;
+ return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
}
bool isThumbOne() const {
- return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;
+ return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
}
void SwitchMode() {
- STI = isThumb() ? ARM_STI.get() : Thumb_STI.get();
- setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
+ unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
+ setAvailableFeatures(FB);
}
/// @name Auto-generated Match Functions
@@ -135,27 +131,12 @@
const SmallVectorImpl<MCParsedAsmOperand*> &);
public:
- ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser)
- : TargetAsmParser(), Parser(_Parser) {
+ ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
+ : TargetAsmParser(), STI(_STI), Parser(_Parser) {
MCAsmParserExtension::Initialize(_Parser);
- STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
- // FIXME: Design a better way to create two subtargets with only difference
- // being a feature change.
- if (isThumb()) {
- Thumb_STI.reset(STI);
- assert(TT.startswith("thumb") && "Unexpected Triple string for Thumb!");
- Twine ARM_TT = "arm" + TT.substr(5);
- ARM_STI.reset(ARM_MC::createARMMCSubtargetInfo(ARM_TT.str(), CPU, FS));
- } else {
- ARM_STI.reset(STI);
- assert(TT.startswith("arm") && "Unexpected Triple string for ARM!");
- Twine Thumb_TT = "thumb" + TT.substr(3);
- Thumb_STI.reset(ARM_MC::createARMMCSubtargetInfo(Thumb_TT.str(),CPU, FS));
- }
-
// Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
+ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
@@ -2237,10 +2218,12 @@
Parser.Lex();
if (Val == 16) {
- if (!isThumb()) SwitchMode();
+ if (!isThumb())
+ SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
} else {
- if (isThumb()) SwitchMode();
+ if (isThumb())
+ SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
}
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 0a8e3b1..1139cac 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -112,17 +112,18 @@
// Force static initialization.
extern "C" void LLVMInitializeARMMCInstrInfo() {
- RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget);
- RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget);
-
TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
}
extern "C" void LLVMInitializeARMMCRegInfo() {
- RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget);
- RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget);
-
TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
}
+
+extern "C" void LLVMInitializeARMMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
+ ARM_MC::createARMMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
+ ARM_MC::createARMMCSubtargetInfo);
+}
diff --git a/lib/Target/Alpha/AlphaSubtarget.cpp b/lib/Target/Alpha/AlphaSubtarget.cpp
index 75f5d8b..ccdc490 100644
--- a/lib/Target/Alpha/AlphaSubtarget.cpp
+++ b/lib/Target/Alpha/AlphaSubtarget.cpp
@@ -13,6 +13,7 @@
#include "AlphaSubtarget.h"
#include "Alpha.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -35,3 +36,15 @@
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
}
+
+MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitAlphaMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
+ createAlphaMCSubtargetInfo);
+}
diff --git a/lib/Target/Blackfin/BlackfinSubtarget.cpp b/lib/Target/Blackfin/BlackfinSubtarget.cpp
index 7b3e4d7..92914ae 100644
--- a/lib/Target/Blackfin/BlackfinSubtarget.cpp
+++ b/lib/Target/Blackfin/BlackfinSubtarget.cpp
@@ -12,6 +12,8 @@
//===----------------------------------------------------------------------===//
#include "BlackfinSubtarget.h"
+#include "Blackfin.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -42,3 +44,15 @@
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
+
+MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitBlackfinMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
+ createBlackfinMCSubtargetInfo);
+}
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index ec4020e..c59497e 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -37,6 +37,7 @@
#include "llvm/Transforms/Scalar.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetRegistry.h"
@@ -61,6 +62,10 @@
RegisterTargetMachine<CTargetMachine> X(TheCBackendTarget);
}
+extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {
+ RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCBackendTarget);
+}
+
namespace {
class CBEMCAsmInfo : public MCAsmInfo {
public:
diff --git a/lib/Target/CMakeLists.txt b/lib/Target/CMakeLists.txt
index f982316..9c684a2 100644
--- a/lib/Target/CMakeLists.txt
+++ b/lib/Target/CMakeLists.txt
@@ -54,3 +54,9 @@
${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in
${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def
)
+
+# Produce llvm/Config/MCSubtargetInfos.def
+configure_file(
+ ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in
+ ${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def
+ )
diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp
index d983507..3ce96b8 100644
--- a/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/lib/Target/CellSPU/SPUSubtarget.cpp
@@ -14,6 +14,7 @@
#include "SPUSubtarget.h"
#include "SPU.h"
#include "SPURegisterInfo.h"
+#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallVector.h"
#define GET_SUBTARGETINFO_ENUM
@@ -65,3 +66,15 @@
CriticalPathRCs.push_back(&SPU::VECREGRegClass);
return OptLevel >= CodeGenOpt::Default;
}
+
+MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitSPUMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
+ createSPUMCSubtargetInfo);
+}
diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp
index ae03725..351f1222 100644
--- a/lib/Target/CppBackend/CPPBackend.cpp
+++ b/lib/Target/CppBackend/CPPBackend.cpp
@@ -23,6 +23,7 @@
#include "llvm/Pass.h"
#include "llvm/PassManager.h"
#include "llvm/TypeSymbolTable.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
@@ -75,6 +76,10 @@
RegisterTargetMachine<CPPTargetMachine> X(TheCppBackendTarget);
}
+extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {
+ RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCppBackendTarget);
+}
+
namespace {
typedef std::vector<const Type*> TypeList;
typedef std::map<const Type*,std::string> TypeMap;
diff --git a/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp b/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
index a6fc147..8759e0c 100644
--- a/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
+++ b/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
@@ -63,8 +63,7 @@
public:
- MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS,
- MCAsmParser &_Parser)
+ MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
: TargetAsmParser(), Parser(_Parser) {}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
diff --git a/lib/Target/MBlaze/MBlazeSubtarget.cpp b/lib/Target/MBlaze/MBlazeSubtarget.cpp
index eb5e28f..54935b1 100644
--- a/lib/Target/MBlaze/MBlazeSubtarget.cpp
+++ b/lib/Target/MBlaze/MBlazeSubtarget.cpp
@@ -15,6 +15,7 @@
#include "MBlaze.h"
#include "MBlazeRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -62,3 +63,15 @@
CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
return HasItin && OptLevel >= CodeGenOpt::Default;
}
+
+MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitMBlazeMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
+ createMBlazeMCSubtargetInfo);
+}
diff --git a/lib/Target/MSP430/MSP430Subtarget.cpp b/lib/Target/MSP430/MSP430Subtarget.cpp
index dddfd2c..6c5156f 100644
--- a/lib/Target/MSP430/MSP430Subtarget.cpp
+++ b/lib/Target/MSP430/MSP430Subtarget.cpp
@@ -13,6 +13,7 @@
#include "MSP430Subtarget.h"
#include "MSP430.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -31,3 +32,15 @@
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
+
+MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitMSP430MCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
+ createMSP430MCSubtargetInfo);
+}
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index a0cb71e..b2b2652 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -13,6 +13,7 @@
#include "MipsSubtarget.h"
#include "Mips.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -61,3 +62,15 @@
HasCondMov = true;
}
}
+
+MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitMipsMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
+ createMipsMCSubtargetInfo);
+}
diff --git a/lib/Target/PTX/PTXSubtarget.cpp b/lib/Target/PTX/PTXSubtarget.cpp
index 584c1d0..a8a2ef7 100644
--- a/lib/Target/PTX/PTXSubtarget.cpp
+++ b/lib/Target/PTX/PTXSubtarget.cpp
@@ -12,7 +12,9 @@
//===----------------------------------------------------------------------===//
#include "PTXSubtarget.h"
+#include "PTX.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -64,3 +66,18 @@
case PTX_VERSION_2_3: return "2.3";
}
}
+
+
+MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitPTXMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializePTXMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
+ createPTXMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
+ createPTXMCSubtargetInfo);
+}
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index d486125..bd40063 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -15,6 +15,7 @@
#include "PPC.h"
#include "llvm/GlobalValue.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegistry.h"
#include <cstdlib>
#define GET_SUBTARGETINFO_ENUM
@@ -140,3 +141,17 @@
return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
GV->hasCommonLinkage() || isDecl;
}
+
+MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitPPCMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
+ createPPCMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
+ createPPCMCSubtargetInfo);
+}
diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp
index 05cea2a..3513479 100644
--- a/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/lib/Target/Sparc/SparcSubtarget.cpp
@@ -12,6 +12,8 @@
//===----------------------------------------------------------------------===//
#include "SparcSubtarget.h"
+#include "Sparc.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -42,3 +44,15 @@
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
+
+MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitSparcMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeSparcMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
+ createSparcMCSubtargetInfo);
+}
diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp
index f20010b..f6707f9 100644
--- a/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -15,6 +15,7 @@
#include "SystemZ.h"
#include "llvm/GlobalValue.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -53,3 +54,15 @@
return false;
}
+
+MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitSystemZMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeSystemZMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget,
+ createSystemZMCSubtargetInfo);
+}
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index db6ab33..cdbbcd3 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -37,8 +37,8 @@
struct X86Operand;
class X86ATTAsmParser : public TargetAsmParser {
+ MCSubtargetInfo &STI;
MCAsmParser &Parser;
- OwningPtr<const MCSubtargetInfo> STI;
private:
MCAsmParser &getParser() const { return Parser; }
@@ -66,7 +66,7 @@
bool is64Bit() {
// FIXME: Can tablegen auto-generate this?
- return (STI->getFeatureBits() & X86::Mode64Bit) != 0;
+ return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
}
/// @name Auto-generated Matcher Functions
@@ -78,13 +78,11 @@
/// }
public:
- X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS,
- MCAsmParser &parser)
- : TargetAsmParser(), Parser(parser),
- STI(X86_MC::createX86MCSubtargetInfo(TT, CPU, FS)) {
+ X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
+ : TargetAsmParser(), STI(sti), Parser(parser) {
// Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
+ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 728246f..c34d3c9 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -145,17 +145,19 @@
// Force static initialization.
extern "C" void LLVMInitializeX86MCInstrInfo() {
- RegisterMCInstrInfo<MCInstrInfo> X(TheX86_32Target);
- RegisterMCInstrInfo<MCInstrInfo> Y(TheX86_64Target);
-
TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
}
extern "C" void LLVMInitializeX86MCRegInfo() {
- RegisterMCRegInfo<MCRegisterInfo> X(TheX86_32Target);
- RegisterMCRegInfo<MCRegisterInfo> Y(TheX86_64Target);
-
TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
}
+
+
+extern "C" void LLVMInitializeX86MCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
+ X86_MC::createX86MCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
+ X86_MC::createX86MCSubtargetInfo);
+}
diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp
index 7d8fe8a..8ede936 100644
--- a/lib/Target/XCore/XCoreSubtarget.cpp
+++ b/lib/Target/XCore/XCoreSubtarget.cpp
@@ -13,6 +13,7 @@
#include "XCoreSubtarget.h"
#include "XCore.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -27,3 +28,16 @@
: XCoreGenSubtargetInfo(TT, CPU, FS)
{
}
+
+
+MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitXCoreMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeXCoreMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget,
+ createXCoreMCSubtargetInfo);
+}
diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp
index a2e508d..6d5b09c 100644
--- a/tools/llc/llc.cpp
+++ b/tools/llc/llc.cpp
@@ -201,6 +201,7 @@
// Initialize targets first, so that --version shows registered targets.
InitializeAllTargets();
+ InitializeAllMCSubtargetInfos();
InitializeAllAsmPrinters();
InitializeAllAsmParsers();
diff --git a/tools/llvm-mc/llvm-mc.cpp b/tools/llvm-mc/llvm-mc.cpp
index 15304fc..d73f7e5 100644
--- a/tools/llvm-mc/llvm-mc.cpp
+++ b/tools/llvm-mc/llvm-mc.cpp
@@ -19,6 +19,7 @@
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Target/TargetAsmBackend.h"
#include "llvm/Target/TargetAsmParser.h"
@@ -340,6 +341,9 @@
TM->getTargetLowering()->getObjFileLowering();
const_cast<TargetLoweringObjectFile&>(TLOF).Initialize(Ctx, *TM);
+ OwningPtr<MCSubtargetInfo>
+ STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
+
// FIXME: There is a bit of code duplication with addPassesToEmitFile.
if (FileType == OFT_AssemblyFile) {
MCInstPrinter *IP =
@@ -371,8 +375,7 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
*Str.get(), *MAI));
- OwningPtr<TargetAsmParser>
- TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));
+ OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*STI, *Parser));
if (!TAP) {
errs() << ProgName
<< ": error: this target does not support assembly parsing.\n";
@@ -448,6 +451,7 @@
llvm::InitializeAllTargetInfos();
// FIXME: We shouldn't need to initialize the Target(Machine)s.
llvm::InitializeAllTargets();
+ llvm::InitializeAllMCSubtargetInfos();
llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
diff --git a/tools/lto/LTOModule.cpp b/tools/lto/LTOModule.cpp
index 1794c97..83fdbbe 100644
--- a/tools/lto/LTOModule.cpp
+++ b/tools/lto/LTOModule.cpp
@@ -35,6 +35,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Target/TargetAsmParser.h"
@@ -618,11 +619,12 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(_target->getTarget(), SrcMgr,
Context, *Streamer,
*_target->getMCAsmInfo()));
+ OwningPtr<MCSubtargetInfo> STI(_target->getTarget().
+ createMCSubtargetInfo(_target->getTargetTriple(),
+ _target->getTargetCPU(),
+ _target->getTargetFeatureString()));
OwningPtr<TargetAsmParser>
- TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),
- _target->getTargetCPU(),
- _target->getTargetFeatureString(),
- *Parser.get()));
+ TAP(_target->getTarget().createAsmParser(*STI, *Parser.get()));
Parser->setTargetParser(*TAP);
int Res = Parser->Run(false);
if (Res)