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Chris Lattnerc16257f2006-01-18 19:37:44 +00001//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
Misha Brukmanb5f662f2005-04-21 23:30:14 +00002//
Misha Brukmanf2ccb772004-08-17 04:55:41 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanb5f662f2005-04-21 23:30:14 +00007//
Misha Brukmanf2ccb772004-08-17 04:55:41 +00008//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC32_INSTRUCTIONINFO_H
15#define POWERPC32_INSTRUCTIONINFO_H
16
Chris Lattner26689592005-10-14 23:51:18 +000017#include "PPC.h"
Chris Lattner617742b2005-10-14 22:44:13 +000018#include "llvm/Target/TargetInstrInfo.h"
Chris Lattner16e71f22005-10-14 23:59:06 +000019#include "PPCRegisterInfo.h"
Misha Brukmanf2ccb772004-08-17 04:55:41 +000020
21namespace llvm {
Chris Lattner88d211f2006-03-12 09:13:49 +000022
23/// PPCII - This namespace holds all of the PowerPC target-specific
24/// per-instruction flags. These must match the corresponding definitions in
25/// PPC.td and PPCInstrFormats.td.
26namespace PPCII {
27enum {
28 // PPC970 Instruction Flags. These flags describe the characteristics of the
29 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30 // raw machine instructions.
31
32 /// PPC970_First - This instruction starts a new dispatch group, so it will
33 /// always be the first one in the group.
34 PPC970_First = 0x1,
35
36 /// PPC970_Single - This instruction starts a new dispatch group and
37 /// terminates it, so it will be the sole instruction in the group.
38 PPC970_Single = 0x2,
39
Chris Lattnerfd977342006-03-13 05:15:10 +000040 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41 /// two dispatch pipes to be available to issue.
42 PPC970_Cracked = 0x4,
43
Chris Lattner88d211f2006-03-12 09:13:49 +000044 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45 /// an instruction is issued to.
Chris Lattnerfd977342006-03-13 05:15:10 +000046 PPC970_Shift = 3,
Chris Lattnerd74ea2b2006-05-24 17:04:05 +000047 PPC970_Mask = 0x07 << PPC970_Shift
Chris Lattner88d211f2006-03-12 09:13:49 +000048};
49enum PPC970_Unit {
50 /// These are the various PPC970 execution unit pipelines. Each instruction
51 /// is one of these.
52 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
53 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
54 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
55 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
56 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
57 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
58 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
Chris Lattnerd74ea2b2006-05-24 17:04:05 +000059 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
Chris Lattner88d211f2006-03-12 09:13:49 +000060};
61}
62
Chris Lattner617742b2005-10-14 22:44:13 +000063
Chris Lattner64105522008-01-01 01:03:04 +000064class PPCInstrInfo : public TargetInstrInfoImpl {
Chris Lattnerb1d26f62006-06-17 00:01:04 +000065 PPCTargetMachine &TM;
Nate Begeman21e463b2005-10-16 05:39:50 +000066 const PPCRegisterInfo RI;
Bill Wendling4a66e9a2008-03-10 22:49:16 +000067
Dan Gohman8e5f2c62008-07-07 23:14:23 +000068 bool StoreRegToStackSlot(MachineFunction &MF,
69 unsigned SrcReg, bool isKill, int FrameIdx,
Bill Wendling4a66e9a2008-03-10 22:49:16 +000070 const TargetRegisterClass *RC,
71 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Dan Gohman8e5f2c62008-07-07 23:14:23 +000072 void LoadRegFromStackSlot(MachineFunction &MF,
73 unsigned DestReg, int FrameIdx,
Bill Wendling4a66e9a2008-03-10 22:49:16 +000074 const TargetRegisterClass *RC,
75 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Misha Brukmanf2ccb772004-08-17 04:55:41 +000076public:
Dan Gohman950a4c42008-03-25 22:06:05 +000077 explicit PPCInstrInfo(PPCTargetMachine &TM);
Misha Brukmanf2ccb772004-08-17 04:55:41 +000078
79 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
80 /// such, whenever a client has an instance of instruction info, it should
81 /// always be able to get register info as well (through this method).
82 ///
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +000083 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
Misha Brukmanf2ccb772004-08-17 04:55:41 +000084
Chris Lattnerb1d26f62006-06-17 00:01:04 +000085 /// getPointerRegClass - Return the register class to use to hold pointers.
86 /// This is used for addressing modes.
87 virtual const TargetRegisterClass *getPointerRegClass() const;
88
Evan Cheng04ee5a12009-01-20 19:12:24 +000089 /// Return true if the instruction is a register to register move and return
90 /// the source and dest operands and their sub-register indices by reference.
91 virtual bool isMoveInstr(const MachineInstr &MI,
92 unsigned &SrcReg, unsigned &DstReg,
93 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
Misha Brukmanf2ccb772004-08-17 04:55:41 +000094
Dan Gohmancbad42c2008-11-18 19:49:32 +000095 unsigned isLoadFromStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const;
97 unsigned isStoreToStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const;
Chris Lattner40839602006-02-02 20:12:32 +000099
Chris Lattner043870d2005-09-09 18:17:41 +0000100 // commuteInstruction - We can commute rlwimi instructions, but only if the
101 // rotate amt is zero. We also have to munge the immediates a bit.
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000102 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
Chris Lattner043870d2005-09-09 18:17:41 +0000103
Chris Lattnerbbf1c722006-03-05 23:49:55 +0000104 virtual void insertNoop(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MI) const;
106
Chris Lattnerc50e2bc2006-10-13 21:21:17 +0000107
108 // Branch analysis.
109 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
110 MachineBasicBlock *&FBB,
Owen Anderson44eb65c2008-08-14 22:49:33 +0000111 SmallVectorImpl<MachineOperand> &Cond) const;
Evan Chengb5cdaa22007-05-18 00:05:48 +0000112 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
113 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
114 MachineBasicBlock *FBB,
Owen Anderson44eb65c2008-08-14 22:49:33 +0000115 const SmallVectorImpl<MachineOperand> &Cond) const;
Owen Anderson940f83e2008-08-26 18:03:31 +0000116 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Andersonf6372aa2008-01-01 21:11:32 +0000117 MachineBasicBlock::iterator MI,
118 unsigned DestReg, unsigned SrcReg,
119 const TargetRegisterClass *DestRC,
120 const TargetRegisterClass *SrcRC) const;
121
122 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MBBI,
124 unsigned SrcReg, bool isKill, int FrameIndex,
125 const TargetRegisterClass *RC) const;
126
127 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
128 SmallVectorImpl<MachineOperand> &Addr,
129 const TargetRegisterClass *RC,
130 SmallVectorImpl<MachineInstr*> &NewMIs) const;
131
132 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator MBBI,
134 unsigned DestReg, int FrameIndex,
135 const TargetRegisterClass *RC) const;
136
137 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
138 SmallVectorImpl<MachineOperand> &Addr,
139 const TargetRegisterClass *RC,
140 SmallVectorImpl<MachineInstr*> &NewMIs) const;
141
Owen Anderson43dbe052008-01-07 01:35:02 +0000142 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
143 /// copy instructions, turning them into load/store instructions.
Dan Gohmanc54baa22008-12-03 18:43:12 +0000144 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
145 MachineInstr* MI,
146 const SmallVectorImpl<unsigned> &Ops,
147 int FrameIndex) const;
Owen Anderson43dbe052008-01-07 01:35:02 +0000148
Dan Gohmanc54baa22008-12-03 18:43:12 +0000149 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
150 MachineInstr* MI,
151 const SmallVectorImpl<unsigned> &Ops,
152 MachineInstr* LoadMI) const {
Owen Anderson43dbe052008-01-07 01:35:02 +0000153 return 0;
154 }
155
Dan Gohman8e8b8a22008-10-16 01:49:15 +0000156 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
157 const SmallVectorImpl<unsigned> &Ops) const;
Owen Anderson43dbe052008-01-07 01:35:02 +0000158
Dan Gohman8e8b8a22008-10-16 01:49:15 +0000159 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
Owen Anderson44eb65c2008-08-14 22:49:33 +0000160 virtual
161 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Nicolas Geoffray52e724a2008-04-16 20:10:13 +0000162
163 /// GetInstSize - Return the number of bytes of code the specified
164 /// instruction may be. This returns the maximum number of bytes.
165 ///
166 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
Misha Brukmanf2ccb772004-08-17 04:55:41 +0000167};
168
169}
170
171#endif