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Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00001//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file implements a linear scan register allocator.
11//
12//===----------------------------------------------------------------------===//
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000013
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000014#define DEBUG_TYPE "regalloc"
Chris Lattnerb9805782005-08-23 22:27:31 +000015#include "VirtRegMap.h"
Lang Hames87e3bca2009-05-06 02:36:21 +000016#include "VirtRegRewriter.h"
Lang Hamese2b201b2009-05-18 19:03:16 +000017#include "Spiller.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000018#include "llvm/Function.h"
Evan Cheng3f32d652008-06-04 09:18:41 +000019#include "llvm/CodeGen/LiveIntervalAnalysis.h"
20#include "llvm/CodeGen/LiveStackAnalysis.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000021#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineInstr.h"
Evan Cheng22f07ff2007-12-11 02:09:15 +000023#include "llvm/CodeGen/MachineLoopInfo.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000025#include "llvm/CodeGen/Passes.h"
Jim Laskeyeb577ba2006-08-02 12:30:23 +000026#include "llvm/CodeGen/RegAllocRegistry.h"
David Greene2c17c4d2007-09-06 16:18:45 +000027#include "llvm/CodeGen/RegisterCoalescer.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000028#include "llvm/Target/TargetRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000029#include "llvm/Target/TargetMachine.h"
Owen Anderson95dad832008-10-07 20:22:28 +000030#include "llvm/Target/TargetOptions.h"
Evan Chengc92da382007-11-03 07:20:12 +000031#include "llvm/Target/TargetInstrInfo.h"
Chris Lattnerb9805782005-08-23 22:27:31 +000032#include "llvm/ADT/EquivalenceClasses.h"
Dan Gohmand68a0762009-01-05 17:59:02 +000033#include "llvm/ADT/SmallSet.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000034#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/STLExtras.h"
Chris Lattnerb9805782005-08-23 22:27:31 +000036#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000037#include "llvm/Support/Compiler.h"
Alkis Evlogimenos843b1602004-02-15 10:24:21 +000038#include <algorithm>
Alkis Evlogimenos26f5a692004-05-30 07:24:39 +000039#include <set>
Alkis Evlogimenos53eb3732004-07-22 08:14:44 +000040#include <queue>
Duraid Madina30059612005-12-28 04:55:42 +000041#include <memory>
Jeff Cohen97af7512006-12-02 02:22:01 +000042#include <cmath>
Lang Hamesf41538d2009-06-02 16:53:25 +000043
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000044using namespace llvm;
45
Chris Lattnercd3245a2006-12-19 22:41:21 +000046STATISTIC(NumIters , "Number of iterations performed");
47STATISTIC(NumBacktracks, "Number of times we had to backtrack");
Evan Chengc92da382007-11-03 07:20:12 +000048STATISTIC(NumCoalesce, "Number of copies coalesced");
Evan Cheng206d1852009-04-20 08:01:12 +000049STATISTIC(NumDowngrade, "Number of registers downgraded");
Chris Lattnercd3245a2006-12-19 22:41:21 +000050
Evan Cheng3e172252008-06-20 21:45:16 +000051static cl::opt<bool>
52NewHeuristic("new-spilling-heuristic",
53 cl::desc("Use new spilling heuristic"),
54 cl::init(false), cl::Hidden);
55
Evan Chengf5cd4f02008-10-23 20:43:13 +000056static cl::opt<bool>
57PreSplitIntervals("pre-alloc-split",
58 cl::desc("Pre-register allocation live interval splitting"),
59 cl::init(false), cl::Hidden);
60
Lang Hamese2b201b2009-05-18 19:03:16 +000061static cl::opt<bool>
62NewSpillFramework("new-spill-framework",
63 cl::desc("New spilling framework"),
64 cl::init(false), cl::Hidden);
65
Chris Lattnercd3245a2006-12-19 22:41:21 +000066static RegisterRegAlloc
Dan Gohmanb8cab922008-10-14 20:25:08 +000067linearscanRegAlloc("linearscan", "linear scan register allocator",
Chris Lattnercd3245a2006-12-19 22:41:21 +000068 createLinearScanRegisterAllocator);
69
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000070namespace {
Bill Wendlinge23e00d2007-05-08 19:02:46 +000071 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
Devang Patel19974732007-05-03 01:11:54 +000072 static char ID;
Dan Gohmanae73dc12008-09-04 17:05:41 +000073 RALinScan() : MachineFunctionPass(&ID) {}
Devang Patel794fd752007-05-01 21:15:47 +000074
Chris Lattnercbb56252004-11-18 02:42:27 +000075 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
Owen Andersoncd1dcbd2008-08-15 18:49:41 +000076 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
Chris Lattnercbb56252004-11-18 02:42:27 +000077 private:
Chris Lattnerb9805782005-08-23 22:27:31 +000078 /// RelatedRegClasses - This structure is built the first time a function is
79 /// compiled, and keeps track of which register classes have registers that
80 /// belong to multiple classes or have aliases that are in other classes.
81 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
Owen Anderson97382162008-08-13 23:36:23 +000082 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
Chris Lattnerb9805782005-08-23 22:27:31 +000083
Evan Cheng206d1852009-04-20 08:01:12 +000084 // NextReloadMap - For each register in the map, it maps to the another
85 // register which is defined by a reload from the same stack slot and
86 // both reloads are in the same basic block.
87 DenseMap<unsigned, unsigned> NextReloadMap;
88
89 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
90 // un-favored for allocation.
91 SmallSet<unsigned, 8> DowngradedRegs;
92
93 // DowngradeMap - A map from virtual registers to physical registers being
94 // downgraded for the virtual registers.
95 DenseMap<unsigned, unsigned> DowngradeMap;
96
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000097 MachineFunction* mf_;
Evan Cheng3e172252008-06-20 21:45:16 +000098 MachineRegisterInfo* mri_;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000099 const TargetMachine* tm_;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000100 const TargetRegisterInfo* tri_;
Evan Chengc92da382007-11-03 07:20:12 +0000101 const TargetInstrInfo* tii_;
Evan Chengc92da382007-11-03 07:20:12 +0000102 BitVector allocatableRegs_;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000103 LiveIntervals* li_;
Evan Cheng3f32d652008-06-04 09:18:41 +0000104 LiveStacks* ls_;
Evan Cheng22f07ff2007-12-11 02:09:15 +0000105 const MachineLoopInfo *loopInfo;
Chris Lattnercbb56252004-11-18 02:42:27 +0000106
107 /// handled_ - Intervals are added to the handled_ set in the order of their
108 /// start value. This is uses for backtracking.
109 std::vector<LiveInterval*> handled_;
110
111 /// fixed_ - Intervals that correspond to machine registers.
112 ///
113 IntervalPtrs fixed_;
114
115 /// active_ - Intervals that are currently being processed, and which have a
116 /// live range active for the current point.
117 IntervalPtrs active_;
118
119 /// inactive_ - Intervals that are currently being processed, but which have
120 /// a hold at the current point.
121 IntervalPtrs inactive_;
122
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000123 typedef std::priority_queue<LiveInterval*,
Owen Andersoncd1dcbd2008-08-15 18:49:41 +0000124 SmallVector<LiveInterval*, 64>,
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000125 greater_ptr<LiveInterval> > IntervalHeap;
126 IntervalHeap unhandled_;
Evan Cheng5b16cd22009-05-01 01:03:49 +0000127
128 /// regUse_ - Tracks register usage.
129 SmallVector<unsigned, 32> regUse_;
130 SmallVector<unsigned, 32> regUseBackUp_;
131
132 /// vrm_ - Tracks register assignments.
Owen Anderson49c8aa02009-03-13 05:55:11 +0000133 VirtRegMap* vrm_;
Evan Cheng5b16cd22009-05-01 01:03:49 +0000134
Lang Hames87e3bca2009-05-06 02:36:21 +0000135 std::auto_ptr<VirtRegRewriter> rewriter_;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000136
Lang Hamese2b201b2009-05-18 19:03:16 +0000137 std::auto_ptr<Spiller> spiller_;
138
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000139 public:
140 virtual const char* getPassName() const {
141 return "Linear Scan Register Allocator";
142 }
143
144 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000145 AU.addRequired<LiveIntervals>();
Owen Anderson95dad832008-10-07 20:22:28 +0000146 if (StrongPHIElim)
147 AU.addRequiredID(StrongPHIEliminationID);
David Greene2c17c4d2007-09-06 16:18:45 +0000148 // Make sure PassManager knows which analyses to make available
149 // to coalescing and which analyses coalescing invalidates.
150 AU.addRequiredTransitive<RegisterCoalescer>();
Evan Chengf5cd4f02008-10-23 20:43:13 +0000151 if (PreSplitIntervals)
152 AU.addRequiredID(PreAllocSplittingID);
Evan Cheng3f32d652008-06-04 09:18:41 +0000153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
Evan Cheng22f07ff2007-12-11 02:09:15 +0000155 AU.addRequired<MachineLoopInfo>();
Bill Wendling67d65bb2008-01-04 20:54:55 +0000156 AU.addPreserved<MachineLoopInfo>();
Owen Anderson49c8aa02009-03-13 05:55:11 +0000157 AU.addRequired<VirtRegMap>();
158 AU.addPreserved<VirtRegMap>();
Bill Wendling67d65bb2008-01-04 20:54:55 +0000159 AU.addPreservedID(MachineDominatorsID);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000160 MachineFunctionPass::getAnalysisUsage(AU);
161 }
162
163 /// runOnMachineFunction - register allocate the whole function
164 bool runOnMachineFunction(MachineFunction&);
165
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000166 private:
167 /// linearScan - the linear scan algorithm
168 void linearScan();
169
Chris Lattnercbb56252004-11-18 02:42:27 +0000170 /// initIntervalSets - initialize the interval sets.
171 ///
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000172 void initIntervalSets();
173
Chris Lattnercbb56252004-11-18 02:42:27 +0000174 /// processActiveIntervals - expire old intervals and move non-overlapping
175 /// ones to the inactive list.
176 void processActiveIntervals(unsigned CurPoint);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000177
Chris Lattnercbb56252004-11-18 02:42:27 +0000178 /// processInactiveIntervals - expire old intervals and move overlapping
179 /// ones to the active list.
180 void processInactiveIntervals(unsigned CurPoint);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000181
Evan Cheng206d1852009-04-20 08:01:12 +0000182 /// hasNextReloadInterval - Return the next liveinterval that's being
183 /// defined by a reload from the same SS as the specified one.
184 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
185
186 /// DowngradeRegister - Downgrade a register for allocation.
187 void DowngradeRegister(LiveInterval *li, unsigned Reg);
188
189 /// UpgradeRegister - Upgrade a register for allocation.
190 void UpgradeRegister(unsigned Reg);
191
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000192 /// assignRegOrStackSlotAtInterval - assign a register if one
193 /// is available, or spill.
194 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
195
Evan Cheng5d088fe2009-03-23 22:57:19 +0000196 void updateSpillWeights(std::vector<float> &Weights,
197 unsigned reg, float weight,
198 const TargetRegisterClass *RC);
199
Evan Cheng3e172252008-06-20 21:45:16 +0000200 /// findIntervalsToSpill - Determine the intervals to spill for the
201 /// specified interval. It's passed the physical registers whose spill
202 /// weight is the lowest among all the registers whose live intervals
203 /// conflict with the interval.
204 void findIntervalsToSpill(LiveInterval *cur,
205 std::vector<std::pair<unsigned,float> > &Candidates,
206 unsigned NumCands,
207 SmallVector<LiveInterval*, 8> &SpillIntervals);
208
Evan Chengc92da382007-11-03 07:20:12 +0000209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
215 /// conservative.
216 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
217
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000218 ///
Evan Cheng5b16cd22009-05-01 01:03:49 +0000219 /// Register usage / availability tracking helpers.
220 ///
221
222 void initRegUses() {
223 regUse_.resize(tri_->getNumRegs(), 0);
224 regUseBackUp_.resize(tri_->getNumRegs(), 0);
225 }
226
227 void finalizeRegUses() {
Evan Chengc781a242009-05-03 18:32:42 +0000228#ifndef NDEBUG
229 // Verify all the registers are "freed".
230 bool Error = false;
231 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
232 if (regUse_[i] != 0) {
233 cerr << tri_->getName(i) << " is still in use!\n";
234 Error = true;
235 }
236 }
237 if (Error)
238 abort();
239#endif
Evan Cheng5b16cd22009-05-01 01:03:49 +0000240 regUse_.clear();
241 regUseBackUp_.clear();
242 }
243
244 void addRegUse(unsigned physReg) {
245 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
246 "should be physical register!");
247 ++regUse_[physReg];
248 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
249 ++regUse_[*as];
250 }
251
252 void delRegUse(unsigned physReg) {
253 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
254 "should be physical register!");
255 assert(regUse_[physReg] != 0);
256 --regUse_[physReg];
257 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
258 assert(regUse_[*as] != 0);
259 --regUse_[*as];
260 }
261 }
262
263 bool isRegAvail(unsigned physReg) const {
264 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
265 "should be physical register!");
266 return regUse_[physReg] == 0;
267 }
268
269 void backUpRegUses() {
270 regUseBackUp_ = regUse_;
271 }
272
273 void restoreRegUses() {
274 regUse_ = regUseBackUp_;
275 }
276
277 ///
278 /// Register handling helpers.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000279 ///
280
Chris Lattnercbb56252004-11-18 02:42:27 +0000281 /// getFreePhysReg - return a free physical register for this virtual
282 /// register interval if we have one, otherwise return 0.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000283 unsigned getFreePhysReg(LiveInterval* cur);
Evan Cheng206d1852009-04-20 08:01:12 +0000284 unsigned getFreePhysReg(const TargetRegisterClass *RC,
285 unsigned MaxInactiveCount,
286 SmallVector<unsigned, 256> &inactiveCounts,
287 bool SkipDGRegs);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000288
289 /// assignVirt2StackSlot - assigns this virtual register to a
290 /// stack slot. returns the stack slot
291 int assignVirt2StackSlot(unsigned virtReg);
292
Chris Lattnerb9805782005-08-23 22:27:31 +0000293 void ComputeRelatedRegClasses();
294
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000295 template <typename ItTy>
296 void printIntervals(const char* const str, ItTy i, ItTy e) const {
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000297 if (str) DOUT << str << " intervals:\n";
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000298 for (; i != e; ++i) {
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000299 DOUT << "\t" << *i->first << " -> ";
Chris Lattnercbb56252004-11-18 02:42:27 +0000300 unsigned reg = i->first->reg;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000301 if (TargetRegisterInfo::isVirtualRegister(reg)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000302 reg = vrm_->getPhys(reg);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000303 }
Bill Wendlinge6d088a2008-02-26 21:47:57 +0000304 DOUT << tri_->getName(reg) << '\n';
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000305 }
306 }
307 };
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000308 char RALinScan::ID = 0;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000309}
310
Evan Cheng3f32d652008-06-04 09:18:41 +0000311static RegisterPass<RALinScan>
312X("linearscan-regalloc", "Linear Scan Register Allocator");
313
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000314void RALinScan::ComputeRelatedRegClasses() {
Chris Lattnerb9805782005-08-23 22:27:31 +0000315 // First pass, add all reg classes to the union, and determine at least one
316 // reg class that each register is in.
317 bool HasAliases = false;
Evan Cheng206d1852009-04-20 08:01:12 +0000318 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
319 E = tri_->regclass_end(); RCI != E; ++RCI) {
Chris Lattnerb9805782005-08-23 22:27:31 +0000320 RelatedRegClasses.insert(*RCI);
321 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
322 I != E; ++I) {
Evan Cheng206d1852009-04-20 08:01:12 +0000323 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
Chris Lattnerb9805782005-08-23 22:27:31 +0000324
325 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
326 if (PRC) {
327 // Already processed this register. Just make sure we know that
328 // multiple register classes share a register.
329 RelatedRegClasses.unionSets(PRC, *RCI);
330 } else {
331 PRC = *RCI;
332 }
333 }
334 }
335
336 // Second pass, now that we know conservatively what register classes each reg
337 // belongs to, add info about aliases. We don't need to do this for targets
338 // without register aliases.
339 if (HasAliases)
Owen Anderson97382162008-08-13 23:36:23 +0000340 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
Chris Lattnerb9805782005-08-23 22:27:31 +0000341 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
342 I != E; ++I)
Evan Cheng206d1852009-04-20 08:01:12 +0000343 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
Chris Lattnerb9805782005-08-23 22:27:31 +0000344 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
345}
346
Evan Chengc92da382007-11-03 07:20:12 +0000347/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
348/// try allocate the definition the same register as the source register
349/// if the register is not defined during live time of the interval. This
350/// eliminate a copy. This is used to coalesce copies which were not
351/// coalesced away before allocation either due to dest and src being in
352/// different register classes or because the coalescer was overly
353/// conservative.
354unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
Evan Cheng9aeaf752007-11-04 08:32:21 +0000355 if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
Evan Chengc92da382007-11-03 07:20:12 +0000356 return Reg;
357
Evan Chengd0deec22009-01-20 00:16:18 +0000358 VNInfo *vni = cur.begin()->valno;
Evan Chengc92da382007-11-03 07:20:12 +0000359 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
360 return Reg;
361 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
Evan Chengeca24fb2009-05-12 23:07:00 +0000362 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
Evan Cheng04ee5a12009-01-20 19:12:24 +0000363 if (!CopyMI ||
364 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
Evan Chengc92da382007-11-03 07:20:12 +0000365 return Reg;
Evan Chengeca24fb2009-05-12 23:07:00 +0000366 PhysReg = SrcReg;
Anton Korobeynikov4aefd6b2008-02-20 12:07:57 +0000367 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
Evan Chengc92da382007-11-03 07:20:12 +0000368 if (!vrm_->isAssignedReg(SrcReg))
369 return Reg;
Evan Chengeca24fb2009-05-12 23:07:00 +0000370 PhysReg = vrm_->getPhys(SrcReg);
Anton Korobeynikov4aefd6b2008-02-20 12:07:57 +0000371 }
Evan Chengeca24fb2009-05-12 23:07:00 +0000372 if (Reg == PhysReg)
Evan Chengc92da382007-11-03 07:20:12 +0000373 return Reg;
374
Evan Cheng841ee1a2008-09-18 22:38:47 +0000375 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
Evan Chengeca24fb2009-05-12 23:07:00 +0000376 if (!RC->contains(PhysReg))
Evan Chengc92da382007-11-03 07:20:12 +0000377 return Reg;
378
379 // Try to coalesce.
Evan Chengeca24fb2009-05-12 23:07:00 +0000380 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
381 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
Bill Wendling74ab84c2008-02-26 21:11:01 +0000382 << '\n';
Evan Chengc92da382007-11-03 07:20:12 +0000383 vrm_->clearVirt(cur.reg);
Evan Chengeca24fb2009-05-12 23:07:00 +0000384 vrm_->assignVirt2Phys(cur.reg, PhysReg);
385
386 // Remove unnecessary kills since a copy does not clobber the register.
387 if (li_->hasInterval(SrcReg)) {
388 LiveInterval &SrcLI = li_->getInterval(SrcReg);
389 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
390 E = mri_->reg_end(); I != E; ++I) {
391 MachineOperand &O = I.getOperand();
392 if (!O.isUse() || !O.isKill())
393 continue;
394 MachineInstr *MI = &*I;
395 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
396 O.setIsKill(false);
397 }
398 }
399
Evan Chengc92da382007-11-03 07:20:12 +0000400 ++NumCoalesce;
401 return SrcReg;
402 }
403
404 return Reg;
405}
406
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000407bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000408 mf_ = &fn;
Evan Cheng3e172252008-06-20 21:45:16 +0000409 mri_ = &fn.getRegInfo();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000410 tm_ = &fn.getTarget();
Dan Gohman6f0d0242008-02-10 18:45:23 +0000411 tri_ = tm_->getRegisterInfo();
Evan Chengc92da382007-11-03 07:20:12 +0000412 tii_ = tm_->getInstrInfo();
Dan Gohman6f0d0242008-02-10 18:45:23 +0000413 allocatableRegs_ = tri_->getAllocatableSet(fn);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000414 li_ = &getAnalysis<LiveIntervals>();
Evan Cheng3f32d652008-06-04 09:18:41 +0000415 ls_ = &getAnalysis<LiveStacks>();
Evan Cheng22f07ff2007-12-11 02:09:15 +0000416 loopInfo = &getAnalysis<MachineLoopInfo>();
Chris Lattnerf348e3a2004-11-18 04:33:31 +0000417
David Greene2c17c4d2007-09-06 16:18:45 +0000418 // We don't run the coalescer here because we have no reason to
419 // interact with it. If the coalescer requires interaction, it
420 // won't do anything. If it doesn't require interaction, we assume
421 // it was run as a separate pass.
422
Chris Lattnerb9805782005-08-23 22:27:31 +0000423 // If this is the first function compiled, compute the related reg classes.
424 if (RelatedRegClasses.empty())
425 ComputeRelatedRegClasses();
Evan Cheng5b16cd22009-05-01 01:03:49 +0000426
427 // Also resize register usage trackers.
428 initRegUses();
429
Owen Anderson49c8aa02009-03-13 05:55:11 +0000430 vrm_ = &getAnalysis<VirtRegMap>();
Lang Hames87e3bca2009-05-06 02:36:21 +0000431 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
Lang Hamese2b201b2009-05-18 19:03:16 +0000432
433 if (NewSpillFramework) {
Lang Hamesf41538d2009-06-02 16:53:25 +0000434 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
Lang Hamese2b201b2009-05-18 19:03:16 +0000435 }
Lang Hamesf41538d2009-06-02 16:53:25 +0000436
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000437 initIntervalSets();
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000438
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000439 linearScan();
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000440
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000441 // Rewrite spill code and update the PhysRegsUsed set.
Lang Hames87e3bca2009-05-06 02:36:21 +0000442 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
Chris Lattnercbb56252004-11-18 02:42:27 +0000443
Dan Gohman51cd9d62008-06-23 23:51:16 +0000444 assert(unhandled_.empty() && "Unhandled live intervals remain!");
Evan Cheng5b16cd22009-05-01 01:03:49 +0000445
446 finalizeRegUses();
447
Chris Lattnercbb56252004-11-18 02:42:27 +0000448 fixed_.clear();
449 active_.clear();
450 inactive_.clear();
451 handled_.clear();
Evan Cheng206d1852009-04-20 08:01:12 +0000452 NextReloadMap.clear();
453 DowngradedRegs.clear();
454 DowngradeMap.clear();
Lang Hamesf41538d2009-06-02 16:53:25 +0000455 spiller_.reset(0);
Chris Lattnercbb56252004-11-18 02:42:27 +0000456
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000457 return true;
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000458}
459
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000460/// initIntervalSets - initialize the interval sets.
461///
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000462void RALinScan::initIntervalSets()
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000463{
464 assert(unhandled_.empty() && fixed_.empty() &&
465 active_.empty() && inactive_.empty() &&
466 "interval sets should be empty on initialization");
467
Owen Andersoncd1dcbd2008-08-15 18:49:41 +0000468 handled_.reserve(li_->getNumIntervals());
469
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000470 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
Owen Anderson03857b22008-08-13 21:49:13 +0000471 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
Evan Cheng841ee1a2008-09-18 22:38:47 +0000472 mri_->setPhysRegUsed(i->second->reg);
Owen Anderson03857b22008-08-13 21:49:13 +0000473 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000474 } else
Owen Anderson03857b22008-08-13 21:49:13 +0000475 unhandled_.push(i->second);
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000476 }
477}
478
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000479void RALinScan::linearScan()
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000480{
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000481 // linear scan algorithm
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000482 DOUT << "********** LINEAR SCAN **********\n";
483 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000484
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000485 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000486
487 while (!unhandled_.empty()) {
488 // pick the interval with the earliest start point
489 LiveInterval* cur = unhandled_.top();
490 unhandled_.pop();
Evan Cheng11923cc2007-10-16 21:09:14 +0000491 ++NumIters;
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000492 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000493
Evan Chengf30a49d2008-04-03 16:40:27 +0000494 if (!cur->empty()) {
495 processActiveIntervals(cur->beginNumber());
496 processInactiveIntervals(cur->beginNumber());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000497
Evan Chengf30a49d2008-04-03 16:40:27 +0000498 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
499 "Can only allocate virtual registers!");
500 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000501
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000502 // Allocating a virtual register. try to find a free
503 // physical register or spill an interval (possibly this one) in order to
504 // assign it one.
505 assignRegOrStackSlotAtInterval(cur);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000506
Alkis Evlogimenos39a0d5c2004-02-20 06:15:40 +0000507 DEBUG(printIntervals("active", active_.begin(), active_.end()));
508 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000509 }
Alkis Evlogimenos7d629b52004-01-07 09:20:58 +0000510
Evan Cheng5b16cd22009-05-01 01:03:49 +0000511 // Expire any remaining active intervals
Evan Cheng11923cc2007-10-16 21:09:14 +0000512 while (!active_.empty()) {
513 IntervalPtr &IP = active_.back();
514 unsigned reg = IP.first->reg;
515 DOUT << "\tinterval " << *IP.first << " expired\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +0000516 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000517 "Can only allocate virtual registers!");
518 reg = vrm_->getPhys(reg);
Evan Cheng5b16cd22009-05-01 01:03:49 +0000519 delRegUse(reg);
Evan Cheng11923cc2007-10-16 21:09:14 +0000520 active_.pop_back();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000521 }
Alkis Evlogimenos7d629b52004-01-07 09:20:58 +0000522
Evan Cheng5b16cd22009-05-01 01:03:49 +0000523 // Expire any remaining inactive intervals
Evan Cheng11923cc2007-10-16 21:09:14 +0000524 DEBUG(for (IntervalPtrs::reverse_iterator
Bill Wendling87075ca2007-11-15 00:40:48 +0000525 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
Evan Cheng11923cc2007-10-16 21:09:14 +0000526 DOUT << "\tinterval " << *i->first << " expired\n");
527 inactive_.clear();
Alkis Evlogimenosb7be1152004-01-13 20:42:08 +0000528
Evan Cheng81a03822007-11-17 00:40:40 +0000529 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000530 MachineFunction::iterator EntryMBB = mf_->begin();
Evan Chenga5bfc972007-10-17 06:53:44 +0000531 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000532 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
Owen Anderson03857b22008-08-13 21:49:13 +0000533 LiveInterval &cur = *i->second;
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000534 unsigned Reg = 0;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000535 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
Evan Cheng81a03822007-11-17 00:40:40 +0000536 if (isPhys)
Owen Anderson03857b22008-08-13 21:49:13 +0000537 Reg = cur.reg;
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000538 else if (vrm_->isAssignedReg(cur.reg))
Evan Chengc92da382007-11-03 07:20:12 +0000539 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000540 if (!Reg)
541 continue;
Evan Cheng81a03822007-11-17 00:40:40 +0000542 // Ignore splited live intervals.
543 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
544 continue;
Evan Cheng550aacb2009-06-04 20:28:22 +0000545
546 // A register defined by an implicit_def can be liveout the def BB and livein
547 // to a use BB. Add it to the livein set of the use BB's.
548 if (!isPhys && cur.empty()) {
549 if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) {
550 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
551 MachineBasicBlock *DefMBB = DefMI->getParent();
552 SmallPtrSet<MachineBasicBlock*, 4> Seen;
553 Seen.insert(DefMBB);
554 for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg),
555 re = mri_->reg_end(); ri != re; ++ri) {
556 MachineInstr *UseMI = &*ri;
557 MachineBasicBlock *UseMBB = UseMI->getParent();
558 if (Seen.insert(UseMBB))
559 UseMBB->addLiveIn(Reg);
560 }
561 }
562 }
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000563 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
564 I != E; ++I) {
565 const LiveRange &LR = *I;
Evan Chengd0e32c52008-10-29 05:06:14 +0000566 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
Evan Cheng3f4b80e2007-10-17 02:12:22 +0000567 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
568 if (LiveInMBBs[i] != EntryMBB)
569 LiveInMBBs[i]->addLiveIn(Reg);
Evan Chenga5bfc972007-10-17 06:53:44 +0000570 LiveInMBBs.clear();
Evan Cheng9fc508f2007-02-16 09:05:02 +0000571 }
572 }
573 }
574
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000575 DOUT << *vrm_;
Evan Chengc781a242009-05-03 18:32:42 +0000576
577 // Look for physical registers that end up not being allocated even though
578 // register allocator had to spill other registers in its register class.
579 if (ls_->getNumIntervals() == 0)
580 return;
581 if (!vrm_->FindUnusedRegisters(tri_, li_))
582 return;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000583}
584
Chris Lattnercbb56252004-11-18 02:42:27 +0000585/// processActiveIntervals - expire old intervals and move non-overlapping ones
586/// to the inactive list.
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000587void RALinScan::processActiveIntervals(unsigned CurPoint)
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000588{
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000589 DOUT << "\tprocessing active intervals:\n";
Chris Lattner23b71c12004-11-18 01:29:39 +0000590
Chris Lattnercbb56252004-11-18 02:42:27 +0000591 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
592 LiveInterval *Interval = active_[i].first;
593 LiveInterval::iterator IntervalPos = active_[i].second;
594 unsigned reg = Interval->reg;
Alkis Evlogimenosed543732004-09-01 22:52:29 +0000595
Chris Lattnercbb56252004-11-18 02:42:27 +0000596 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
597
598 if (IntervalPos == Interval->end()) { // Remove expired intervals.
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000599 DOUT << "\t\tinterval " << *Interval << " expired\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +0000600 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000601 "Can only allocate virtual registers!");
602 reg = vrm_->getPhys(reg);
Evan Cheng5b16cd22009-05-01 01:03:49 +0000603 delRegUse(reg);
Chris Lattnercbb56252004-11-18 02:42:27 +0000604
605 // Pop off the end of the list.
606 active_[i] = active_.back();
607 active_.pop_back();
608 --i; --e;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000609
Chris Lattnercbb56252004-11-18 02:42:27 +0000610 } else if (IntervalPos->start > CurPoint) {
611 // Move inactive intervals to inactive list.
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000612 DOUT << "\t\tinterval " << *Interval << " inactive\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +0000613 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000614 "Can only allocate virtual registers!");
615 reg = vrm_->getPhys(reg);
Evan Cheng5b16cd22009-05-01 01:03:49 +0000616 delRegUse(reg);
Chris Lattnercbb56252004-11-18 02:42:27 +0000617 // add to inactive.
618 inactive_.push_back(std::make_pair(Interval, IntervalPos));
619
620 // Pop off the end of the list.
621 active_[i] = active_.back();
622 active_.pop_back();
623 --i; --e;
624 } else {
625 // Otherwise, just update the iterator position.
626 active_[i].second = IntervalPos;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000627 }
628 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000629}
630
Chris Lattnercbb56252004-11-18 02:42:27 +0000631/// processInactiveIntervals - expire old intervals and move overlapping
632/// ones to the active list.
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000633void RALinScan::processInactiveIntervals(unsigned CurPoint)
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000634{
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000635 DOUT << "\tprocessing inactive intervals:\n";
Chris Lattner365b95f2004-11-18 04:13:02 +0000636
Chris Lattnercbb56252004-11-18 02:42:27 +0000637 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
638 LiveInterval *Interval = inactive_[i].first;
639 LiveInterval::iterator IntervalPos = inactive_[i].second;
640 unsigned reg = Interval->reg;
Chris Lattner23b71c12004-11-18 01:29:39 +0000641
Chris Lattnercbb56252004-11-18 02:42:27 +0000642 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000643
Chris Lattnercbb56252004-11-18 02:42:27 +0000644 if (IntervalPos == Interval->end()) { // remove expired intervals.
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000645 DOUT << "\t\tinterval " << *Interval << " expired\n";
Alkis Evlogimenos169cfd02003-12-21 05:43:40 +0000646
Chris Lattnercbb56252004-11-18 02:42:27 +0000647 // Pop off the end of the list.
648 inactive_[i] = inactive_.back();
649 inactive_.pop_back();
650 --i; --e;
651 } else if (IntervalPos->start <= CurPoint) {
652 // move re-activated intervals in active list
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000653 DOUT << "\t\tinterval " << *Interval << " active\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +0000654 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000655 "Can only allocate virtual registers!");
656 reg = vrm_->getPhys(reg);
Evan Cheng5b16cd22009-05-01 01:03:49 +0000657 addRegUse(reg);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000658 // add to active
Chris Lattnercbb56252004-11-18 02:42:27 +0000659 active_.push_back(std::make_pair(Interval, IntervalPos));
660
661 // Pop off the end of the list.
662 inactive_[i] = inactive_.back();
663 inactive_.pop_back();
664 --i; --e;
665 } else {
666 // Otherwise, just update the iterator position.
667 inactive_[i].second = IntervalPos;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000668 }
669 }
Alkis Evlogimenos169cfd02003-12-21 05:43:40 +0000670}
671
Chris Lattnercbb56252004-11-18 02:42:27 +0000672/// updateSpillWeights - updates the spill weights of the specifed physical
673/// register and its weight.
Evan Cheng5d088fe2009-03-23 22:57:19 +0000674void RALinScan::updateSpillWeights(std::vector<float> &Weights,
675 unsigned reg, float weight,
676 const TargetRegisterClass *RC) {
677 SmallSet<unsigned, 4> Processed;
678 SmallSet<unsigned, 4> SuperAdded;
679 SmallVector<unsigned, 4> Supers;
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000680 Weights[reg] += weight;
Evan Cheng5d088fe2009-03-23 22:57:19 +0000681 Processed.insert(reg);
682 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
Chris Lattnerc8b9f332004-11-18 06:01:45 +0000683 Weights[*as] += weight;
Evan Cheng5d088fe2009-03-23 22:57:19 +0000684 Processed.insert(*as);
685 if (tri_->isSubRegister(*as, reg) &&
686 SuperAdded.insert(*as) &&
687 RC->contains(*as)) {
688 Supers.push_back(*as);
689 }
690 }
691
692 // If the alias is a super-register, and the super-register is in the
693 // register class we are trying to allocate. Then add the weight to all
694 // sub-registers of the super-register even if they are not aliases.
695 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
696 // bl should get the same spill weight otherwise it will be choosen
697 // as a spill candidate since spilling bh doesn't make ebx available.
698 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
Evan Chengc781a242009-05-03 18:32:42 +0000699 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
700 if (!Processed.count(*sr))
701 Weights[*sr] += weight;
Evan Cheng5d088fe2009-03-23 22:57:19 +0000702 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000703}
704
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000705static
706RALinScan::IntervalPtrs::iterator
707FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
708 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
709 I != E; ++I)
Chris Lattnercbb56252004-11-18 02:42:27 +0000710 if (I->first == LI) return I;
711 return IP.end();
712}
713
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000714static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
Chris Lattner19828d42004-11-18 03:49:30 +0000715 for (unsigned i = 0, e = V.size(); i != e; ++i) {
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000716 RALinScan::IntervalPtr &IP = V[i];
Chris Lattner19828d42004-11-18 03:49:30 +0000717 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
718 IP.second, Point);
719 if (I != IP.first->begin()) --I;
720 IP.second = I;
721 }
722}
Chris Lattnercbb56252004-11-18 02:42:27 +0000723
Evan Cheng3f32d652008-06-04 09:18:41 +0000724/// addStackInterval - Create a LiveInterval for stack if the specified live
725/// interval has been spilled.
726static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
Evan Chengc781a242009-05-03 18:32:42 +0000727 LiveIntervals *li_,
728 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
Evan Cheng3f32d652008-06-04 09:18:41 +0000729 int SS = vrm_.getStackSlot(cur->reg);
730 if (SS == VirtRegMap::NO_STACK_SLOT)
731 return;
Evan Chengc781a242009-05-03 18:32:42 +0000732
733 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
734 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
Evan Cheng9c3c2212008-06-06 07:54:39 +0000735
Evan Cheng3f32d652008-06-04 09:18:41 +0000736 VNInfo *VNI;
Evan Cheng54898932008-10-29 08:39:34 +0000737 if (SI.hasAtLeastOneValue())
Evan Cheng3f32d652008-06-04 09:18:41 +0000738 VNI = SI.getValNumInfo(0);
739 else
740 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
741
742 LiveInterval &RI = li_->getInterval(cur->reg);
743 // FIXME: This may be overly conservative.
744 SI.MergeRangesInAsValue(RI, VNI);
Evan Cheng3f32d652008-06-04 09:18:41 +0000745}
746
Evan Cheng3e172252008-06-20 21:45:16 +0000747/// getConflictWeight - Return the number of conflicts between cur
748/// live interval and defs and uses of Reg weighted by loop depthes.
Evan Chengc781a242009-05-03 18:32:42 +0000749static
750float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
751 MachineRegisterInfo *mri_,
752 const MachineLoopInfo *loopInfo) {
Evan Cheng3e172252008-06-20 21:45:16 +0000753 float Conflicts = 0;
754 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
755 E = mri_->reg_end(); I != E; ++I) {
756 MachineInstr *MI = &*I;
757 if (cur->liveAt(li_->getInstructionIndex(MI))) {
758 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
759 Conflicts += powf(10.0f, (float)loopDepth);
760 }
761 }
762 return Conflicts;
763}
764
765/// findIntervalsToSpill - Determine the intervals to spill for the
766/// specified interval. It's passed the physical registers whose spill
767/// weight is the lowest among all the registers whose live intervals
768/// conflict with the interval.
769void RALinScan::findIntervalsToSpill(LiveInterval *cur,
770 std::vector<std::pair<unsigned,float> > &Candidates,
771 unsigned NumCands,
772 SmallVector<LiveInterval*, 8> &SpillIntervals) {
773 // We have figured out the *best* register to spill. But there are other
774 // registers that are pretty good as well (spill weight within 3%). Spill
775 // the one that has fewest defs and uses that conflict with cur.
776 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
777 SmallVector<LiveInterval*, 8> SLIs[3];
778
779 DOUT << "\tConsidering " << NumCands << " candidates: ";
780 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
781 DOUT << tri_->getName(Candidates[i].first) << " ";
782 DOUT << "\n";);
783
784 // Calculate the number of conflicts of each candidate.
785 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
786 unsigned Reg = i->first->reg;
787 unsigned PhysReg = vrm_->getPhys(Reg);
788 if (!cur->overlapsFrom(*i->first, i->second))
789 continue;
790 for (unsigned j = 0; j < NumCands; ++j) {
791 unsigned Candidate = Candidates[j].first;
792 if (tri_->regsOverlap(PhysReg, Candidate)) {
793 if (NumCands > 1)
794 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
795 SLIs[j].push_back(i->first);
796 }
797 }
798 }
799
800 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
801 unsigned Reg = i->first->reg;
802 unsigned PhysReg = vrm_->getPhys(Reg);
803 if (!cur->overlapsFrom(*i->first, i->second-1))
804 continue;
805 for (unsigned j = 0; j < NumCands; ++j) {
806 unsigned Candidate = Candidates[j].first;
807 if (tri_->regsOverlap(PhysReg, Candidate)) {
808 if (NumCands > 1)
809 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
810 SLIs[j].push_back(i->first);
811 }
812 }
813 }
814
815 // Which is the best candidate?
816 unsigned BestCandidate = 0;
817 float MinConflicts = Conflicts[0];
818 for (unsigned i = 1; i != NumCands; ++i) {
819 if (Conflicts[i] < MinConflicts) {
820 BestCandidate = i;
821 MinConflicts = Conflicts[i];
822 }
823 }
824
825 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
826 std::back_inserter(SpillIntervals));
827}
828
829namespace {
830 struct WeightCompare {
831 typedef std::pair<unsigned, float> RegWeightPair;
832 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
833 return LHS.second < RHS.second;
834 }
835 };
836}
837
838static bool weightsAreClose(float w1, float w2) {
839 if (!NewHeuristic)
840 return false;
841
842 float diff = w1 - w2;
843 if (diff <= 0.02f) // Within 0.02f
844 return true;
845 return (diff / w2) <= 0.05f; // Within 5%.
846}
847
Evan Cheng206d1852009-04-20 08:01:12 +0000848LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
849 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
850 if (I == NextReloadMap.end())
851 return 0;
852 return &li_->getInterval(I->second);
853}
854
855void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
856 bool isNew = DowngradedRegs.insert(Reg);
857 isNew = isNew; // Silence compiler warning.
858 assert(isNew && "Multiple reloads holding the same register?");
859 DowngradeMap.insert(std::make_pair(li->reg, Reg));
860 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
861 isNew = DowngradedRegs.insert(*AS);
862 isNew = isNew; // Silence compiler warning.
863 assert(isNew && "Multiple reloads holding the same register?");
864 DowngradeMap.insert(std::make_pair(li->reg, *AS));
865 }
866 ++NumDowngrade;
867}
868
869void RALinScan::UpgradeRegister(unsigned Reg) {
870 if (Reg) {
871 DowngradedRegs.erase(Reg);
872 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
873 DowngradedRegs.erase(*AS);
874 }
875}
876
877namespace {
878 struct LISorter {
879 bool operator()(LiveInterval* A, LiveInterval* B) {
880 return A->beginNumber() < B->beginNumber();
881 }
882 };
883}
884
Chris Lattnercbb56252004-11-18 02:42:27 +0000885/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
886/// spill.
Bill Wendlinge23e00d2007-05-08 19:02:46 +0000887void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000888{
Bill Wendling54fcc7f2006-11-17 00:50:36 +0000889 DOUT << "\tallocating current interval: ";
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000890
Evan Chengf30a49d2008-04-03 16:40:27 +0000891 // This is an implicitly defined live interval, just assign any register.
Evan Cheng841ee1a2008-09-18 22:38:47 +0000892 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
Evan Chengf30a49d2008-04-03 16:40:27 +0000893 if (cur->empty()) {
894 unsigned physReg = cur->preference;
895 if (!physReg)
896 physReg = *RC->allocation_order_begin(*mf_);
897 DOUT << tri_->getName(physReg) << '\n';
898 // Note the register is not really in use.
899 vrm_->assignVirt2Phys(cur->reg, physReg);
Evan Chengf30a49d2008-04-03 16:40:27 +0000900 return;
901 }
902
Evan Cheng5b16cd22009-05-01 01:03:49 +0000903 backUpRegUses();
Alkis Evlogimenos169cfd02003-12-21 05:43:40 +0000904
Chris Lattnera6c17502005-08-22 20:20:42 +0000905 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
Chris Lattner365b95f2004-11-18 04:13:02 +0000906 unsigned StartPosition = cur->beginNumber();
Chris Lattnerb9805782005-08-23 22:27:31 +0000907 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
Evan Chengc92da382007-11-03 07:20:12 +0000908
Evan Chengd0deec22009-01-20 00:16:18 +0000909 // If start of this live interval is defined by a move instruction and its
910 // source is assigned a physical register that is compatible with the target
911 // register class, then we should try to assign it the same register.
Evan Chengc92da382007-11-03 07:20:12 +0000912 // This can happen when the move is from a larger register class to a smaller
913 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
Evan Chengd0deec22009-01-20 00:16:18 +0000914 if (!cur->preference && cur->hasAtLeastOneValue()) {
915 VNInfo *vni = cur->begin()->valno;
Evan Chengc92da382007-11-03 07:20:12 +0000916 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
917 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
Evan Cheng04ee5a12009-01-20 19:12:24 +0000918 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
919 if (CopyMI &&
920 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
Evan Chengc92da382007-11-03 07:20:12 +0000921 unsigned Reg = 0;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000922 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Evan Chengc92da382007-11-03 07:20:12 +0000923 Reg = SrcReg;
924 else if (vrm_->isAssignedReg(SrcReg))
925 Reg = vrm_->getPhys(SrcReg);
Evan Cheng1c2f6da2009-04-29 00:42:27 +0000926 if (Reg) {
927 if (SrcSubReg)
928 Reg = tri_->getSubReg(Reg, SrcSubReg);
929 if (DstSubReg)
930 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
931 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
932 cur->preference = Reg;
933 }
Evan Chengc92da382007-11-03 07:20:12 +0000934 }
935 }
936 }
937
Evan Cheng5b16cd22009-05-01 01:03:49 +0000938 // For every interval in inactive we overlap with, mark the
Chris Lattnera6c17502005-08-22 20:20:42 +0000939 // register as not free and update spill weights.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000940 for (IntervalPtrs::const_iterator i = inactive_.begin(),
941 e = inactive_.end(); i != e; ++i) {
Chris Lattnerb9805782005-08-23 22:27:31 +0000942 unsigned Reg = i->first->reg;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000943 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
Chris Lattnerb9805782005-08-23 22:27:31 +0000944 "Can only allocate virtual registers!");
Evan Cheng841ee1a2008-09-18 22:38:47 +0000945 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
Chris Lattnerb9805782005-08-23 22:27:31 +0000946 // If this is not in a related reg class to the register we're allocating,
947 // don't check it.
948 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
949 cur->overlapsFrom(*i->first, i->second-1)) {
950 Reg = vrm_->getPhys(Reg);
Evan Cheng5b16cd22009-05-01 01:03:49 +0000951 addRegUse(Reg);
Chris Lattnerb9805782005-08-23 22:27:31 +0000952 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000953 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000954 }
Chris Lattnera411cbc2005-08-22 20:59:30 +0000955
956 // Speculatively check to see if we can get a register right now. If not,
957 // we know we won't be able to by adding more constraints. If so, we can
958 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
959 // is very bad (it contains all callee clobbered registers for any functions
960 // with a call), so we want to avoid doing that if possible.
961 unsigned physReg = getFreePhysReg(cur);
Evan Cheng676dd7c2008-03-11 07:19:34 +0000962 unsigned BestPhysReg = physReg;
Chris Lattnera411cbc2005-08-22 20:59:30 +0000963 if (physReg) {
964 // We got a register. However, if it's in the fixed_ list, we might
Chris Lattnere836ad62005-08-30 21:03:36 +0000965 // conflict with it. Check to see if we conflict with it or any of its
966 // aliases.
Evan Chengc92da382007-11-03 07:20:12 +0000967 SmallSet<unsigned, 8> RegAliases;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000968 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
Chris Lattnere836ad62005-08-30 21:03:36 +0000969 RegAliases.insert(*AS);
970
Chris Lattnera411cbc2005-08-22 20:59:30 +0000971 bool ConflictsWithFixed = false;
972 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
Jim Laskeye719d9f2006-10-24 14:35:25 +0000973 IntervalPtr &IP = fixed_[i];
974 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
Chris Lattnera411cbc2005-08-22 20:59:30 +0000975 // Okay, this reg is on the fixed list. Check to see if we actually
976 // conflict.
Chris Lattnera411cbc2005-08-22 20:59:30 +0000977 LiveInterval *I = IP.first;
978 if (I->endNumber() > StartPosition) {
979 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
980 IP.second = II;
981 if (II != I->begin() && II->start > StartPosition)
982 --II;
Chris Lattnere836ad62005-08-30 21:03:36 +0000983 if (cur->overlapsFrom(*I, II)) {
Chris Lattnera411cbc2005-08-22 20:59:30 +0000984 ConflictsWithFixed = true;
Chris Lattnere836ad62005-08-30 21:03:36 +0000985 break;
986 }
Chris Lattnera411cbc2005-08-22 20:59:30 +0000987 }
Chris Lattnerf348e3a2004-11-18 04:33:31 +0000988 }
Alkis Evlogimenos169cfd02003-12-21 05:43:40 +0000989 }
Chris Lattnera411cbc2005-08-22 20:59:30 +0000990
991 // Okay, the register picked by our speculative getFreePhysReg call turned
992 // out to be in use. Actually add all of the conflicting fixed registers to
Evan Cheng5b16cd22009-05-01 01:03:49 +0000993 // regUse_ so we can do an accurate query.
Chris Lattnera411cbc2005-08-22 20:59:30 +0000994 if (ConflictsWithFixed) {
Chris Lattnerb9805782005-08-23 22:27:31 +0000995 // For every interval in fixed we overlap with, mark the register as not
996 // free and update spill weights.
Chris Lattnera411cbc2005-08-22 20:59:30 +0000997 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
998 IntervalPtr &IP = fixed_[i];
999 LiveInterval *I = IP.first;
Chris Lattnerb9805782005-08-23 22:27:31 +00001000
1001 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1002 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1003 I->endNumber() > StartPosition) {
Chris Lattnera411cbc2005-08-22 20:59:30 +00001004 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1005 IP.second = II;
1006 if (II != I->begin() && II->start > StartPosition)
1007 --II;
1008 if (cur->overlapsFrom(*I, II)) {
1009 unsigned reg = I->reg;
Evan Cheng5b16cd22009-05-01 01:03:49 +00001010 addRegUse(reg);
Chris Lattnera411cbc2005-08-22 20:59:30 +00001011 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1012 }
1013 }
1014 }
Alkis Evlogimenos169cfd02003-12-21 05:43:40 +00001015
Evan Cheng5b16cd22009-05-01 01:03:49 +00001016 // Using the newly updated regUse_ object, which includes conflicts in the
Chris Lattnera411cbc2005-08-22 20:59:30 +00001017 // future, see if there are any registers available.
1018 physReg = getFreePhysReg(cur);
1019 }
1020 }
1021
Chris Lattnera6c17502005-08-22 20:20:42 +00001022 // Restore the physical register tracker, removing information about the
1023 // future.
Evan Cheng5b16cd22009-05-01 01:03:49 +00001024 restoreRegUses();
Chris Lattnera6c17502005-08-22 20:20:42 +00001025
Evan Cheng5b16cd22009-05-01 01:03:49 +00001026 // If we find a free register, we are done: assign this virtual to
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001027 // the free physical register and add this interval to the active
1028 // list.
1029 if (physReg) {
Bill Wendlinge6d088a2008-02-26 21:47:57 +00001030 DOUT << tri_->getName(physReg) << '\n';
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001031 vrm_->assignVirt2Phys(cur->reg, physReg);
Evan Cheng5b16cd22009-05-01 01:03:49 +00001032 addRegUse(physReg);
Chris Lattnercbb56252004-11-18 02:42:27 +00001033 active_.push_back(std::make_pair(cur, cur->begin()));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001034 handled_.push_back(cur);
Evan Cheng206d1852009-04-20 08:01:12 +00001035
1036 // "Upgrade" the physical register since it has been allocated.
1037 UpgradeRegister(physReg);
1038 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1039 // "Downgrade" physReg to try to keep physReg from being allocated until
1040 // the next reload from the same SS is allocated.
1041 NextReloadLI->preference = physReg;
1042 DowngradeRegister(cur, physReg);
1043 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001044 return;
1045 }
Bill Wendling54fcc7f2006-11-17 00:50:36 +00001046 DOUT << "no free registers\n";
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001047
Chris Lattnera6c17502005-08-22 20:20:42 +00001048 // Compile the spill weights into an array that is better for scanning.
Evan Cheng3e172252008-06-20 21:45:16 +00001049 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
Chris Lattnera6c17502005-08-22 20:20:42 +00001050 for (std::vector<std::pair<unsigned, float> >::iterator
1051 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
Evan Cheng5d088fe2009-03-23 22:57:19 +00001052 updateSpillWeights(SpillWeights, I->first, I->second, RC);
Chris Lattnera6c17502005-08-22 20:20:42 +00001053
1054 // for each interval in active, update spill weights.
1055 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1056 i != e; ++i) {
1057 unsigned reg = i->first->reg;
Dan Gohman6f0d0242008-02-10 18:45:23 +00001058 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
Chris Lattnera6c17502005-08-22 20:20:42 +00001059 "Can only allocate virtual registers!");
1060 reg = vrm_->getPhys(reg);
Evan Cheng5d088fe2009-03-23 22:57:19 +00001061 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
Chris Lattnera6c17502005-08-22 20:20:42 +00001062 }
1063
Bill Wendling54fcc7f2006-11-17 00:50:36 +00001064 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001065
Chris Lattnerc8e2c552006-03-25 23:00:56 +00001066 // Find a register to spill.
Jim Laskey7902c752006-11-07 12:25:45 +00001067 float minWeight = HUGE_VALF;
Evan Cheng5d088fe2009-03-23 22:57:19 +00001068 unsigned minReg = 0; /*cur->preference*/; // Try the pref register first.
Evan Cheng3e172252008-06-20 21:45:16 +00001069
1070 bool Found = false;
1071 std::vector<std::pair<unsigned,float> > RegsWeights;
Evan Cheng20b0abc2007-04-17 20:32:26 +00001072 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1073 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1074 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1075 unsigned reg = *i;
Evan Cheng3e172252008-06-20 21:45:16 +00001076 float regWeight = SpillWeights[reg];
1077 if (minWeight > regWeight)
1078 Found = true;
1079 RegsWeights.push_back(std::make_pair(reg, regWeight));
Alkis Evlogimenos3bf564a2003-12-23 18:00:33 +00001080 }
Chris Lattnerc8e2c552006-03-25 23:00:56 +00001081
1082 // If we didn't find a register that is spillable, try aliases?
Evan Cheng3e172252008-06-20 21:45:16 +00001083 if (!Found) {
Evan Cheng3b6d56c2006-05-12 19:07:46 +00001084 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1085 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1086 unsigned reg = *i;
1087 // No need to worry about if the alias register size < regsize of RC.
1088 // We are going to spill all registers that alias it anyway.
Evan Cheng3e172252008-06-20 21:45:16 +00001089 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1090 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
Evan Cheng676dd7c2008-03-11 07:19:34 +00001091 }
Evan Cheng3b6d56c2006-05-12 19:07:46 +00001092 }
Evan Cheng3e172252008-06-20 21:45:16 +00001093
1094 // Sort all potential spill candidates by weight.
1095 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1096 minReg = RegsWeights[0].first;
1097 minWeight = RegsWeights[0].second;
1098 if (minWeight == HUGE_VALF) {
1099 // All registers must have inf weight. Just grab one!
1100 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
Owen Andersona1566f22008-07-22 22:46:49 +00001101 if (cur->weight == HUGE_VALF ||
Evan Cheng5e8d9de2008-09-20 01:28:05 +00001102 li_->getApproximateInstructionCount(*cur) == 0) {
Evan Cheng3e172252008-06-20 21:45:16 +00001103 // Spill a physical register around defs and uses.
Evan Cheng206d1852009-04-20 08:01:12 +00001104 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
Evan Cheng96f3fd92009-04-29 07:16:34 +00001105 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1106 // in fixed_. Reset them.
1107 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1108 IntervalPtr &IP = fixed_[i];
1109 LiveInterval *I = IP.first;
1110 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1111 IP.second = I->advanceTo(I->begin(), StartPosition);
1112 }
1113
Evan Cheng206d1852009-04-20 08:01:12 +00001114 DowngradedRegs.clear();
Evan Cheng2824a652009-03-23 18:24:37 +00001115 assignRegOrStackSlotAtInterval(cur);
Evan Cheng206d1852009-04-20 08:01:12 +00001116 } else {
Evan Cheng2824a652009-03-23 18:24:37 +00001117 cerr << "Ran out of registers during register allocation!\n";
1118 exit(1);
1119 }
Evan Cheng5e8d9de2008-09-20 01:28:05 +00001120 return;
1121 }
Evan Cheng3e172252008-06-20 21:45:16 +00001122 }
1123
1124 // Find up to 3 registers to consider as spill candidates.
1125 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1126 while (LastCandidate > 1) {
1127 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1128 break;
1129 --LastCandidate;
1130 }
1131
1132 DOUT << "\t\tregister(s) with min weight(s): ";
1133 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1134 DOUT << tri_->getName(RegsWeights[i].first)
1135 << " (" << RegsWeights[i].second << ")\n");
Alkis Evlogimenos3bf564a2003-12-23 18:00:33 +00001136
Evan Cheng206d1852009-04-20 08:01:12 +00001137 // If the current has the minimum weight, we need to spill it and
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001138 // add any added intervals back to unhandled, and restart
1139 // linearscan.
Jim Laskey7902c752006-11-07 12:25:45 +00001140 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
Bill Wendling54fcc7f2006-11-17 00:50:36 +00001141 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
Evan Chengdc377862008-09-30 15:44:16 +00001142 SmallVector<LiveInterval*, 8> spillIs;
Lang Hamese2b201b2009-05-18 19:03:16 +00001143 std::vector<LiveInterval*> added;
1144
1145 if (!NewSpillFramework) {
1146 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
Lang Hamesf41538d2009-06-02 16:53:25 +00001147 } else {
Lang Hamese2b201b2009-05-18 19:03:16 +00001148 added = spiller_->spill(cur);
1149 }
1150
Evan Cheng206d1852009-04-20 08:01:12 +00001151 std::sort(added.begin(), added.end(), LISorter());
Evan Chengc781a242009-05-03 18:32:42 +00001152 addStackInterval(cur, ls_, li_, mri_, *vrm_);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001153 if (added.empty())
1154 return; // Early exit if all spills were folded.
Alkis Evlogimenosf5eaf162004-02-06 18:08:18 +00001155
Evan Cheng206d1852009-04-20 08:01:12 +00001156 // Merge added with unhandled. Note that we have already sorted
1157 // intervals returned by addIntervalsForSpills by their starting
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001158 // point.
Evan Chengc4f718a2009-04-20 17:23:48 +00001159 // This also update the NextReloadMap. That is, it adds mapping from a
1160 // register defined by a reload from SS to the next reload from SS in the
1161 // same basic block.
1162 MachineBasicBlock *LastReloadMBB = 0;
1163 LiveInterval *LastReload = 0;
1164 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1165 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1166 LiveInterval *ReloadLi = added[i];
1167 if (ReloadLi->weight == HUGE_VALF &&
1168 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1169 unsigned ReloadIdx = ReloadLi->beginNumber();
1170 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1171 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1172 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1173 // Last reload of same SS is in the same MBB. We want to try to
1174 // allocate both reloads the same register and make sure the reg
1175 // isn't clobbered in between if at all possible.
1176 assert(LastReload->beginNumber() < ReloadIdx);
1177 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1178 }
1179 LastReloadMBB = ReloadMBB;
1180 LastReload = ReloadLi;
1181 LastReloadSS = ReloadSS;
1182 }
1183 unhandled_.push(ReloadLi);
1184 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001185 return;
1186 }
1187
Chris Lattner19828d42004-11-18 03:49:30 +00001188 ++NumBacktracks;
1189
Evan Cheng206d1852009-04-20 08:01:12 +00001190 // Push the current interval back to unhandled since we are going
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001191 // to re-run at least this iteration. Since we didn't modify it it
1192 // should go back right in the front of the list
1193 unhandled_.push(cur);
1194
Dan Gohman6f0d0242008-02-10 18:45:23 +00001195 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001196 "did not choose a register to spill?");
Chris Lattner19828d42004-11-18 03:49:30 +00001197
Evan Cheng3e172252008-06-20 21:45:16 +00001198 // We spill all intervals aliasing the register with
1199 // minimum weight, rollback to the interval with the earliest
1200 // start point and let the linear scan algorithm run again
1201 SmallVector<LiveInterval*, 8> spillIs;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001202
Evan Cheng3e172252008-06-20 21:45:16 +00001203 // Determine which intervals have to be spilled.
1204 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1205
1206 // Set of spilled vregs (used later to rollback properly)
1207 SmallSet<unsigned, 8> spilled;
1208
1209 // The earliest start of a Spilled interval indicates up to where
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001210 // in handled we need to roll back
Lang Hamesf41538d2009-06-02 16:53:25 +00001211
Lang Hamesf41538d2009-06-02 16:53:25 +00001212 LiveInterval *earliestStartInterval = cur;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001213
Evan Cheng3e172252008-06-20 21:45:16 +00001214 // Spill live intervals of virtual regs mapped to the physical register we
Chris Lattner19828d42004-11-18 03:49:30 +00001215 // want to clear (and its aliases). We only spill those that overlap with the
1216 // current interval as the rest do not affect its allocation. we also keep
1217 // track of the earliest start of all spilled live intervals since this will
1218 // mark our rollback point.
Evan Cheng3e172252008-06-20 21:45:16 +00001219 std::vector<LiveInterval*> added;
1220 while (!spillIs.empty()) {
Lang Hamesf41538d2009-06-02 16:53:25 +00001221 bool epicFail = false;
Evan Cheng3e172252008-06-20 21:45:16 +00001222 LiveInterval *sli = spillIs.back();
1223 spillIs.pop_back();
1224 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
Lang Hamesf41538d2009-06-02 16:53:25 +00001225 earliestStartInterval =
1226 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1227 earliestStartInterval : sli;
Lang Hamesfcad1722009-06-04 01:04:22 +00001228
Lang Hamesf41538d2009-06-02 16:53:25 +00001229 std::vector<LiveInterval*> newIs;
1230 if (!NewSpillFramework) {
1231 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1232 } else {
1233 newIs = spiller_->spill(sli);
1234 }
Evan Chengc781a242009-05-03 18:32:42 +00001235 addStackInterval(sli, ls_, li_, mri_, *vrm_);
Evan Cheng3e172252008-06-20 21:45:16 +00001236 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1237 spilled.insert(sli->reg);
Lang Hamesf41538d2009-06-02 16:53:25 +00001238
Lang Hamesf41538d2009-06-02 16:53:25 +00001239 if (epicFail) {
1240 //abort();
1241 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001242 }
1243
Lang Hamesfcad1722009-06-04 01:04:22 +00001244 unsigned earliestStart = earliestStartInterval->beginNumber();
Lang Hamesf41538d2009-06-02 16:53:25 +00001245
Bill Wendling54fcc7f2006-11-17 00:50:36 +00001246 DOUT << "\t\trolling back to: " << earliestStart << '\n';
Chris Lattnercbb56252004-11-18 02:42:27 +00001247
1248 // Scan handled in reverse order up to the earliest start of a
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001249 // spilled live interval and undo each one, restoring the state of
Chris Lattnercbb56252004-11-18 02:42:27 +00001250 // unhandled.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001251 while (!handled_.empty()) {
1252 LiveInterval* i = handled_.back();
Chris Lattnercbb56252004-11-18 02:42:27 +00001253 // If this interval starts before t we are done.
Chris Lattner23b71c12004-11-18 01:29:39 +00001254 if (i->beginNumber() < earliestStart)
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001255 break;
Bill Wendling54fcc7f2006-11-17 00:50:36 +00001256 DOUT << "\t\t\tundo changes for: " << *i << '\n';
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001257 handled_.pop_back();
Chris Lattnercbb56252004-11-18 02:42:27 +00001258
1259 // When undoing a live interval allocation we must know if it is active or
Evan Cheng5b16cd22009-05-01 01:03:49 +00001260 // inactive to properly update regUse_ and the VirtRegMap.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001261 IntervalPtrs::iterator it;
Chris Lattnercbb56252004-11-18 02:42:27 +00001262 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001263 active_.erase(it);
Dan Gohman6f0d0242008-02-10 18:45:23 +00001264 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
Chris Lattnerffab4222006-02-23 06:44:17 +00001265 if (!spilled.count(i->reg))
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001266 unhandled_.push(i);
Evan Cheng5b16cd22009-05-01 01:03:49 +00001267 delRegUse(vrm_->getPhys(i->reg));
Chris Lattnerffab4222006-02-23 06:44:17 +00001268 vrm_->clearVirt(i->reg);
Chris Lattnercbb56252004-11-18 02:42:27 +00001269 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001270 inactive_.erase(it);
Dan Gohman6f0d0242008-02-10 18:45:23 +00001271 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
Chris Lattnerffab4222006-02-23 06:44:17 +00001272 if (!spilled.count(i->reg))
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001273 unhandled_.push(i);
Chris Lattnerffab4222006-02-23 06:44:17 +00001274 vrm_->clearVirt(i->reg);
Chris Lattnerc8b9f332004-11-18 06:01:45 +00001275 } else {
Dan Gohman6f0d0242008-02-10 18:45:23 +00001276 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
Chris Lattnerc8b9f332004-11-18 06:01:45 +00001277 "Can only allocate virtual registers!");
1278 vrm_->clearVirt(i->reg);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001279 unhandled_.push(i);
1280 }
Evan Cheng9aeaf752007-11-04 08:32:21 +00001281
Evan Cheng206d1852009-04-20 08:01:12 +00001282 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1283 if (ii == DowngradeMap.end())
1284 // It interval has a preference, it must be defined by a copy. Clear the
1285 // preference now since the source interval allocation may have been
1286 // undone as well.
1287 i->preference = 0;
1288 else {
1289 UpgradeRegister(ii->second);
1290 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001291 }
1292
Chris Lattner19828d42004-11-18 03:49:30 +00001293 // Rewind the iterators in the active, inactive, and fixed lists back to the
1294 // point we reverted to.
1295 RevertVectorIteratorsTo(active_, earliestStart);
1296 RevertVectorIteratorsTo(inactive_, earliestStart);
1297 RevertVectorIteratorsTo(fixed_, earliestStart);
1298
Evan Cheng206d1852009-04-20 08:01:12 +00001299 // Scan the rest and undo each interval that expired after t and
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001300 // insert it in active (the next iteration of the algorithm will
1301 // put it in inactive if required)
Chris Lattnercbb56252004-11-18 02:42:27 +00001302 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1303 LiveInterval *HI = handled_[i];
1304 if (!HI->expiredAt(earliestStart) &&
1305 HI->expiredAt(cur->beginNumber())) {
Bill Wendling54fcc7f2006-11-17 00:50:36 +00001306 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
Chris Lattnercbb56252004-11-18 02:42:27 +00001307 active_.push_back(std::make_pair(HI, HI->begin()));
Dan Gohman6f0d0242008-02-10 18:45:23 +00001308 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
Evan Cheng5b16cd22009-05-01 01:03:49 +00001309 addRegUse(vrm_->getPhys(HI->reg));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001310 }
1311 }
1312
Evan Cheng206d1852009-04-20 08:01:12 +00001313 // Merge added with unhandled.
1314 // This also update the NextReloadMap. That is, it adds mapping from a
1315 // register defined by a reload from SS to the next reload from SS in the
1316 // same basic block.
1317 MachineBasicBlock *LastReloadMBB = 0;
1318 LiveInterval *LastReload = 0;
1319 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1320 std::sort(added.begin(), added.end(), LISorter());
1321 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1322 LiveInterval *ReloadLi = added[i];
1323 if (ReloadLi->weight == HUGE_VALF &&
1324 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1325 unsigned ReloadIdx = ReloadLi->beginNumber();
1326 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1327 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1328 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1329 // Last reload of same SS is in the same MBB. We want to try to
1330 // allocate both reloads the same register and make sure the reg
1331 // isn't clobbered in between if at all possible.
1332 assert(LastReload->beginNumber() < ReloadIdx);
1333 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1334 }
1335 LastReloadMBB = ReloadMBB;
1336 LastReload = ReloadLi;
1337 LastReloadSS = ReloadSS;
1338 }
1339 unhandled_.push(ReloadLi);
1340 }
1341}
1342
1343unsigned RALinScan::getFreePhysReg(const TargetRegisterClass *RC,
1344 unsigned MaxInactiveCount,
1345 SmallVector<unsigned, 256> &inactiveCounts,
1346 bool SkipDGRegs) {
1347 unsigned FreeReg = 0;
1348 unsigned FreeRegInactiveCount = 0;
1349
1350 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
1351 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
1352 assert(I != E && "No allocatable register in this register class!");
1353
1354 // Scan for the first available register.
1355 for (; I != E; ++I) {
1356 unsigned Reg = *I;
1357 // Ignore "downgraded" registers.
1358 if (SkipDGRegs && DowngradedRegs.count(Reg))
1359 continue;
Evan Cheng5b16cd22009-05-01 01:03:49 +00001360 if (isRegAvail(Reg)) {
Evan Cheng206d1852009-04-20 08:01:12 +00001361 FreeReg = Reg;
1362 if (FreeReg < inactiveCounts.size())
1363 FreeRegInactiveCount = inactiveCounts[FreeReg];
1364 else
1365 FreeRegInactiveCount = 0;
1366 break;
1367 }
1368 }
1369
1370 // If there are no free regs, or if this reg has the max inactive count,
1371 // return this register.
1372 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1373 return FreeReg;
1374
1375 // Continue scanning the registers, looking for the one with the highest
1376 // inactive count. Alkis found that this reduced register pressure very
1377 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1378 // reevaluated now.
1379 for (; I != E; ++I) {
1380 unsigned Reg = *I;
1381 // Ignore "downgraded" registers.
1382 if (SkipDGRegs && DowngradedRegs.count(Reg))
1383 continue;
Evan Cheng5b16cd22009-05-01 01:03:49 +00001384 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
Evan Cheng206d1852009-04-20 08:01:12 +00001385 FreeRegInactiveCount < inactiveCounts[Reg]) {
1386 FreeReg = Reg;
1387 FreeRegInactiveCount = inactiveCounts[Reg];
1388 if (FreeRegInactiveCount == MaxInactiveCount)
1389 break; // We found the one with the max inactive count.
1390 }
1391 }
1392
1393 return FreeReg;
Alkis Evlogimenos843b1602004-02-15 10:24:21 +00001394}
Alkis Evlogimenosf5eaf162004-02-06 18:08:18 +00001395
Chris Lattnercbb56252004-11-18 02:42:27 +00001396/// getFreePhysReg - return a free physical register for this virtual register
1397/// interval if we have one, otherwise return 0.
Bill Wendlinge23e00d2007-05-08 19:02:46 +00001398unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
Chris Lattnerfe424622008-02-26 22:08:41 +00001399 SmallVector<unsigned, 256> inactiveCounts;
Chris Lattnerf8355d92005-08-22 16:55:22 +00001400 unsigned MaxInactiveCount = 0;
1401
Evan Cheng841ee1a2008-09-18 22:38:47 +00001402 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
Chris Lattnerb9805782005-08-23 22:27:31 +00001403 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1404
Alkis Evlogimenos84f5bcb2004-09-02 21:23:32 +00001405 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1406 i != e; ++i) {
Chris Lattnercbb56252004-11-18 02:42:27 +00001407 unsigned reg = i->first->reg;
Dan Gohman6f0d0242008-02-10 18:45:23 +00001408 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
Chris Lattnerc8b9f332004-11-18 06:01:45 +00001409 "Can only allocate virtual registers!");
Chris Lattnerb9805782005-08-23 22:27:31 +00001410
1411 // If this is not in a related reg class to the register we're allocating,
1412 // don't check it.
Evan Cheng841ee1a2008-09-18 22:38:47 +00001413 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
Chris Lattnerb9805782005-08-23 22:27:31 +00001414 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1415 reg = vrm_->getPhys(reg);
Chris Lattnerfe424622008-02-26 22:08:41 +00001416 if (inactiveCounts.size() <= reg)
1417 inactiveCounts.resize(reg+1);
Chris Lattnerb9805782005-08-23 22:27:31 +00001418 ++inactiveCounts[reg];
1419 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1420 }
Alkis Evlogimenos84f5bcb2004-09-02 21:23:32 +00001421 }
1422
Evan Cheng20b0abc2007-04-17 20:32:26 +00001423 // If copy coalescer has assigned a "preferred" register, check if it's
Dale Johannesen86b49f82008-09-24 01:07:17 +00001424 // available first.
Anton Korobeynikov4aefd6b2008-02-20 12:07:57 +00001425 if (cur->preference) {
Evan Cheng1c2f6da2009-04-29 00:42:27 +00001426 DOUT << "(preferred: " << tri_->getName(cur->preference) << ") ";
Evan Cheng5b16cd22009-05-01 01:03:49 +00001427 if (isRegAvail(cur->preference) &&
Evan Cheng1c2f6da2009-04-29 00:42:27 +00001428 RC->contains(cur->preference))
Evan Cheng20b0abc2007-04-17 20:32:26 +00001429 return cur->preference;
Anton Korobeynikov4aefd6b2008-02-20 12:07:57 +00001430 }
Evan Cheng20b0abc2007-04-17 20:32:26 +00001431
Evan Cheng206d1852009-04-20 08:01:12 +00001432 if (!DowngradedRegs.empty()) {
1433 unsigned FreeReg = getFreePhysReg(RC, MaxInactiveCount, inactiveCounts,
1434 true);
1435 if (FreeReg)
1436 return FreeReg;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +00001437 }
Evan Cheng206d1852009-04-20 08:01:12 +00001438 return getFreePhysReg(RC, MaxInactiveCount, inactiveCounts, false);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00001439}
1440
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00001441FunctionPass* llvm::createLinearScanRegisterAllocator() {
Bill Wendlinge23e00d2007-05-08 19:02:46 +00001442 return new RALinScan();
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00001443}