| Jim Laskey | 076866c | 2005-10-18 16:23:40 +0000 | [diff] [blame^] | 1 | //===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by James M. Laskey and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the itinerary class data for the G4+ (7450) processor. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | def G4PlusItineraries : ProcessorItineraries<G4Plus, [ |
| 15 | InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, |
| 16 | InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, |
| 17 | InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>, |
| 18 | InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>, |
| 19 | InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>, |
| 20 | InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>, |
| 21 | InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>, |
| 22 | InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>, |
| 23 | InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>, |
| 24 | InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>, |
| 25 | InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>, |
| 26 | InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>, |
| 27 | InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>, |
| 28 | InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>, |
| 29 | InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, |
| 30 | InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, |
| 31 | InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>, |
| 32 | InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, |
| 33 | InstrItinData<BrB , [InstrStage<1, [BPU]>]>, |
| 34 | InstrItinData<BrCR , [InstrStage<2, [IU2]>]>, |
| 35 | InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>, |
| 36 | InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, |
| 37 | InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>, |
| 38 | InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, |
| 39 | InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, |
| 40 | InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>, |
| 41 | InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, |
| 42 | InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, |
| 43 | InstrItinData<LdStLBZUX , [InstrStage<3, [SLU]>]>, |
| 44 | InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>, |
| 45 | InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>, |
| 46 | InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>, |
| 47 | InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>, |
| 48 | InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>, |
| 49 | InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>, |
| 50 | InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>, |
| 51 | InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>, |
| 52 | InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, |
| 53 | InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>, |
| 54 | InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>, |
| 55 | InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, |
| 56 | InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>, |
| 57 | InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>, |
| 58 | InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>, |
| 59 | InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, |
| 60 | InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, |
| 61 | InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>, |
| 62 | InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>, |
| 63 | InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>, |
| 64 | InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, |
| 65 | InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, |
| 66 | InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, |
| 67 | InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>, |
| 68 | InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>, |
| 69 | InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>, |
| 70 | InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>, |
| 71 | InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, |
| 72 | InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, |
| 73 | InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>, |
| 74 | InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>, |
| 75 | InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>, |
| 76 | InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>, |
| 77 | InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>, |
| 78 | InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>, |
| 79 | InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>, |
| 80 | InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, |
| 81 | InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, |
| 82 | InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, |
| 83 | InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>, |
| 84 | InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>, |
| 85 | InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>, |
| 86 | InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>, |
| 87 | InstrItinData<VecVSR , [InstrStage<2, [VPU]>]> |
| 88 | ]>; |