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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 07c375d6f604610f97447467044e424d8d74ec1f / . / lib / Target / PowerPC / PPCScheduleG5.td
blob: 4738b8929925d7c7609b16c7355e0953847215ca [file] [log] [blame]
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]1//===- PPCScheduleG5.td - PPC G5 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by James M. Laskey and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G5 (970) processor.
11//
12//===----------------------------------------------------------------------===//
13
14def G5Itineraries : ProcessorItineraries<G5, [
15 InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
16 InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>,
17 InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>,
18 InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>,
19 InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>,
20 InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>,
21 InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]22 InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
23 InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
24 InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>,
25 InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>,
26 InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>,
27 InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>,
28 InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>,
29 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>,
30 InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>,
31 InstrItinData<IntTrapW , [InstrStage<1, [IU1, IU2]>]>,
32 InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
33 InstrItinData<BrCR , [InstrStage<4, [BPU]>]>,
34 InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>,
35 InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]36 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]37 InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
38 InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>,
Jim Laskey21f587c2005-10-18 16:59:23 +0000[diff] [blame]39 InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]40 InstrItinData<LdStLBZUX , [InstrStage<4, [SLU]>]>,
41 InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>,
42 InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>,
43 InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>,
44 InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>,
45 InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>,
46 InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>,
47 InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
48 InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>,
49 InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>,
Jim Laskey21f587c2005-10-18 16:59:23 +0000[diff] [blame]50 InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]51 InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>,
52 InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
53 InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>,
54 InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>,
55 InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>,
56 InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
Jim Laskey21f587c2005-10-18 16:59:23 +0000[diff] [blame]57 InstrItinData<SprISYNC , [InstrStage<40, [SLU]>]>, // needs work
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]58 InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>,
59 InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>,
60 InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>,
61 InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
62 InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
63 InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
64 InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>,
65 InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>,
66 InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>,
Jim Laskey076866c2005-10-18 16:23:40 +0000[diff] [blame]67 InstrItinData<SprSC , [InstrStage<1, [IU2]>]>,
68 InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
69 InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
70 InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>,
71 InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>,
72 InstrItinData<FPFused , [InstrStage<6, [FPU1, FPU2]>]>,
73 InstrItinData<FPRes , [InstrStage<6, [FPU1, FPU2]>]>,
74 InstrItinData<FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>,
75 InstrItinData<VecGeneral , [InstrStage<2, [VIU1]>]>,
76 InstrItinData<VecFP , [InstrStage<8, [VFPU]>]>,
77 InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
78 InstrItinData<VecComplex , [InstrStage<5, [VIU2]>]>,
79 InstrItinData<VecPerm , [InstrStage<3, [VPU]>]>,
80 InstrItinData<VecFPRound , [InstrStage<8, [VFPU]>]>,
81 InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>,
82 InstrItinData<VecVSR , [InstrStage<3, [VPU]>]>
83]>;