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Andrew Trick96f678f2012-01-13 06:30:30 +00001//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// MachineScheduler schedules machine instructions after phi elimination. It
11// preserves LiveIntervals so it can be invoked before register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "misched"
16
17#include "ScheduleDAGInstrs.h"
Andrew Trick96f678f2012-01-13 06:30:30 +000018#include "llvm/CodeGen/LiveIntervalAnalysis.h"
19#include "llvm/CodeGen/MachinePassRegistry.h"
20#include "llvm/CodeGen/Passes.h"
21#include "llvm/Analysis/AliasAnalysis.h"
Andrew Tricke9ef4ed2012-01-14 02:17:09 +000022#include "llvm/Target/TargetInstrInfo.h"
Andrew Trick96f678f2012-01-13 06:30:30 +000023#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/ADT/OwningPtr.h"
28
Andrew Trickc6cf11b2012-01-17 06:55:07 +000029#include <queue>
30
Andrew Trick96f678f2012-01-13 06:30:30 +000031using namespace llvm;
32
Andrew Trick5edf2f02012-01-14 02:17:06 +000033//===----------------------------------------------------------------------===//
34// Machine Instruction Scheduling Pass and Registry
35//===----------------------------------------------------------------------===//
36
Andrew Trick96f678f2012-01-13 06:30:30 +000037namespace {
Andrew Trick42b7a712012-01-17 06:55:03 +000038/// MachineScheduler runs after coalescing and before register allocation.
39class MachineScheduler : public MachineFunctionPass {
Andrew Trick96f678f2012-01-13 06:30:30 +000040public:
41 MachineFunction *MF;
Andrew Trick5edf2f02012-01-14 02:17:06 +000042 const TargetInstrInfo *TII;
Andrew Trick96f678f2012-01-13 06:30:30 +000043 const MachineLoopInfo *MLI;
44 const MachineDominatorTree *MDT;
Lang Hames907cc8f2012-01-27 22:36:19 +000045 LiveIntervals *LIS;
Andrew Trick96f678f2012-01-13 06:30:30 +000046
Andrew Trick42b7a712012-01-17 06:55:03 +000047 MachineScheduler();
Andrew Trick96f678f2012-01-13 06:30:30 +000048
49 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
50
51 virtual void releaseMemory() {}
52
53 virtual bool runOnMachineFunction(MachineFunction&);
54
55 virtual void print(raw_ostream &O, const Module* = 0) const;
56
57 static char ID; // Class identification, replacement for typeinfo
58};
59} // namespace
60
Andrew Trick42b7a712012-01-17 06:55:03 +000061char MachineScheduler::ID = 0;
Andrew Trick96f678f2012-01-13 06:30:30 +000062
Andrew Trick42b7a712012-01-17 06:55:03 +000063char &llvm::MachineSchedulerID = MachineScheduler::ID;
Andrew Trick96f678f2012-01-13 06:30:30 +000064
Andrew Trick42b7a712012-01-17 06:55:03 +000065INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
Andrew Trick96f678f2012-01-13 06:30:30 +000066 "Machine Instruction Scheduler", false, false)
67INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
68INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
69INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
Andrew Trick42b7a712012-01-17 06:55:03 +000070INITIALIZE_PASS_END(MachineScheduler, "misched",
Andrew Trick96f678f2012-01-13 06:30:30 +000071 "Machine Instruction Scheduler", false, false)
72
Andrew Trick42b7a712012-01-17 06:55:03 +000073MachineScheduler::MachineScheduler()
Andrew Trick96f678f2012-01-13 06:30:30 +000074: MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
Andrew Trick42b7a712012-01-17 06:55:03 +000075 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
Andrew Trick96f678f2012-01-13 06:30:30 +000076}
77
Andrew Trick42b7a712012-01-17 06:55:03 +000078void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
Andrew Trick96f678f2012-01-13 06:30:30 +000079 AU.setPreservesCFG();
80 AU.addRequiredID(MachineDominatorsID);
81 AU.addRequired<MachineLoopInfo>();
82 AU.addRequired<AliasAnalysis>();
83 AU.addPreserved<AliasAnalysis>();
84 AU.addRequired<SlotIndexes>();
85 AU.addPreserved<SlotIndexes>();
86 AU.addRequired<LiveIntervals>();
87 AU.addPreserved<LiveIntervals>();
Andrew Trick96f678f2012-01-13 06:30:30 +000088 MachineFunctionPass::getAnalysisUsage(AU);
89}
90
91namespace {
Andrew Trick96f678f2012-01-13 06:30:30 +000092/// MachineSchedRegistry provides a selection of available machine instruction
93/// schedulers.
94class MachineSchedRegistry : public MachinePassRegistryNode {
95public:
Andrew Trick42b7a712012-01-17 06:55:03 +000096 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
Andrew Trick96f678f2012-01-13 06:30:30 +000097
98 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
99 typedef ScheduleDAGCtor FunctionPassCtor;
100
101 static MachinePassRegistry Registry;
102
103 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
104 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
105 Registry.Add(this);
106 }
107 ~MachineSchedRegistry() { Registry.Remove(this); }
108
109 // Accessors.
110 //
111 MachineSchedRegistry *getNext() const {
112 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
113 }
114 static MachineSchedRegistry *getList() {
115 return (MachineSchedRegistry *)Registry.getList();
116 }
117 static ScheduleDAGCtor getDefault() {
118 return (ScheduleDAGCtor)Registry.getDefault();
119 }
120 static void setDefault(ScheduleDAGCtor C) {
121 Registry.setDefault((MachinePassCtor)C);
122 }
123 static void setListener(MachinePassRegistryListener *L) {
124 Registry.setListener(L);
125 }
126};
127} // namespace
128
129MachinePassRegistry MachineSchedRegistry::Registry;
130
Andrew Trick42b7a712012-01-17 06:55:03 +0000131static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
Andrew Trick96f678f2012-01-13 06:30:30 +0000132
133/// MachineSchedOpt allows command line selection of the scheduler.
134static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
135 RegisterPassParser<MachineSchedRegistry> >
136MachineSchedOpt("misched",
137 cl::init(&createDefaultMachineSched), cl::Hidden,
138 cl::desc("Machine instruction scheduler to use"));
139
Andrew Trick5edf2f02012-01-14 02:17:06 +0000140//===----------------------------------------------------------------------===//
Andrew Trick42b7a712012-01-17 06:55:03 +0000141// Machine Instruction Scheduling Common Implementation
Andrew Trick5edf2f02012-01-14 02:17:06 +0000142//===----------------------------------------------------------------------===//
143
144namespace {
Andrew Trick78b29612012-02-09 00:40:52 +0000145/// ScheduleTopDownLive is an implementation of ScheduleDAGInstrs that schedules
Andrew Trick5edf2f02012-01-14 02:17:06 +0000146/// machine instructions while updating LiveIntervals.
Andrew Trick42b7a712012-01-17 06:55:03 +0000147class ScheduleTopDownLive : public ScheduleDAGInstrs {
148protected:
149 MachineScheduler *Pass;
Andrew Trick5edf2f02012-01-14 02:17:06 +0000150public:
Andrew Trick42b7a712012-01-17 06:55:03 +0000151 ScheduleTopDownLive(MachineScheduler *P):
Andrew Trickb4566a92012-02-22 06:08:11 +0000152 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false, P->LIS),
153 Pass(P) {}
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000154
155 /// ScheduleDAGInstrs callback.
156 void Schedule();
157
158 /// Interface implemented by the selected top-down liveinterval scheduler.
159 ///
160 /// Pick the next node to schedule, or return NULL.
161 virtual SUnit *pickNode() = 0;
162
163 /// When all preceeding dependencies have been resolved, free this node for
164 /// scheduling.
165 virtual void releaseNode(SUnit *SU) = 0;
166
167protected:
168 void releaseSucc(SUnit *SU, SDep *SuccEdge);
169 void releaseSuccessors(SUnit *SU);
Andrew Trick5edf2f02012-01-14 02:17:06 +0000170};
171} // namespace
172
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000173/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
174/// NumPredsLeft reaches zero, release the successor node.
175void ScheduleTopDownLive::releaseSucc(SUnit *SU, SDep *SuccEdge) {
176 SUnit *SuccSU = SuccEdge->getSUnit();
177
178#ifndef NDEBUG
179 if (SuccSU->NumPredsLeft == 0) {
180 dbgs() << "*** Scheduling failed! ***\n";
181 SuccSU->dump(this);
182 dbgs() << " has been released too many times!\n";
183 llvm_unreachable(0);
184 }
185#endif
186 --SuccSU->NumPredsLeft;
187 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
188 releaseNode(SuccSU);
189}
190
191/// releaseSuccessors - Call releaseSucc on each of SU's successors.
192void ScheduleTopDownLive::releaseSuccessors(SUnit *SU) {
193 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
194 I != E; ++I) {
195 releaseSucc(SU, &*I);
196 }
197}
198
199/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
200/// time to do some work.
201void ScheduleTopDownLive::Schedule() {
202 BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
203
204 DEBUG(dbgs() << "********** MI Scheduling **********\n");
205 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
206 SUnits[su].dumpAll(this));
207
208 // Release any successors of the special Entry node. It is currently unused,
209 // but we keep up appearances.
210 releaseSuccessors(&EntrySU);
211
212 // Release all DAG roots for scheduling.
213 for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
214 I != E; ++I) {
215 // A SUnit is ready to schedule if it has no predecessors.
216 if (I->Preds.empty())
217 releaseNode(&(*I));
218 }
219
220 InsertPos = Begin;
221 while (SUnit *SU = pickNode()) {
222 DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
223
224 // Move the instruction to its new location in the instruction stream.
225 MachineInstr *MI = SU->getInstr();
226 if (&*InsertPos == MI)
227 ++InsertPos;
228 else {
Lang Hamesda7984f2012-02-15 01:23:52 +0000229 BB->splice(InsertPos, BB, MI);
230 Pass->LIS->handleMove(MI);
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000231 if (Begin == InsertPos)
232 Begin = MI;
233 }
234
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000235 // Release dependent instructions for scheduling.
236 releaseSuccessors(SU);
237 }
238}
239
Andrew Trick42b7a712012-01-17 06:55:03 +0000240bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
Andrew Trick96f678f2012-01-13 06:30:30 +0000241 // Initialize the context of the pass.
242 MF = &mf;
243 MLI = &getAnalysis<MachineLoopInfo>();
244 MDT = &getAnalysis<MachineDominatorTree>();
Lang Hames907cc8f2012-01-27 22:36:19 +0000245 LIS = &getAnalysis<LiveIntervals>();
Andrew Trick5edf2f02012-01-14 02:17:06 +0000246 TII = MF->getTarget().getInstrInfo();
Andrew Trick96f678f2012-01-13 06:30:30 +0000247
248 // Select the scheduler, or set the default.
249 MachineSchedRegistry::ScheduleDAGCtor Ctor =
250 MachineSchedRegistry::getDefault();
251 if (!Ctor) {
252 Ctor = MachineSchedOpt;
253 MachineSchedRegistry::setDefault(Ctor);
254 }
255 // Instantiate the selected scheduler.
256 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
257
258 // Visit all machine basic blocks.
259 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
260 MBB != MBBEnd; ++MBB) {
261
Andrew Tricke9ef4ed2012-01-14 02:17:09 +0000262 // Break the block into scheduling regions [I, RegionEnd), and schedule each
263 // region as soon as it is discovered.
264 unsigned RemainingCount = MBB->size();
265 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
266 RegionEnd != MBB->begin();) {
Andrew Trick6cfb14f2012-03-07 00:18:05 +0000267 Scheduler->StartBlock(MBB);
Andrew Tricke9ef4ed2012-01-14 02:17:09 +0000268 // The next region starts above the previous region. Look backward in the
269 // instruction stream until we find the nearest boundary.
270 MachineBasicBlock::iterator I = RegionEnd;
Andrew Trick3c58ba82012-01-14 02:17:18 +0000271 for(;I != MBB->begin(); --I, --RemainingCount) {
Andrew Tricke9ef4ed2012-01-14 02:17:09 +0000272 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
273 break;
274 }
Andrew Trick3c58ba82012-01-14 02:17:18 +0000275 if (I == RegionEnd) {
276 // Skip empty scheduling regions.
Andrew Tricke9ef4ed2012-01-14 02:17:09 +0000277 RegionEnd = llvm::prior(RegionEnd);
Andrew Trick3c58ba82012-01-14 02:17:18 +0000278 --RemainingCount;
Andrew Tricke9ef4ed2012-01-14 02:17:09 +0000279 continue;
280 }
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000281 // Skip regions with one instruction.
282 if (I == llvm::prior(RegionEnd)) {
283 RegionEnd = llvm::prior(RegionEnd);
284 continue;
Andrew Trick3c58ba82012-01-14 02:17:18 +0000285 }
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000286 DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
Andrew Trick291411c2012-02-08 02:17:21 +0000287 << ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
288 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
289 else dbgs() << "End";
290 dbgs() << " Remaining: " << RemainingCount << "\n");
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000291
292 // Inform ScheduleDAGInstrs of the region being scheduled. It calls back
293 // to our Schedule() method.
294 Scheduler->Run(MBB, I, RegionEnd, MBB->size());
295 RegionEnd = Scheduler->Begin;
Andrew Tricke9ef4ed2012-01-14 02:17:09 +0000296 }
297 assert(RemainingCount == 0 && "Instruction count mismatch!");
Andrew Trick6cfb14f2012-03-07 00:18:05 +0000298 Scheduler->FinishBlock();
Andrew Trick96f678f2012-01-13 06:30:30 +0000299 }
300 return true;
301}
302
Andrew Trick42b7a712012-01-17 06:55:03 +0000303void MachineScheduler::print(raw_ostream &O, const Module* m) const {
Andrew Trick96f678f2012-01-13 06:30:30 +0000304 // unimplemented
305}
306
Andrew Trick5edf2f02012-01-14 02:17:06 +0000307//===----------------------------------------------------------------------===//
Andrew Trick42b7a712012-01-17 06:55:03 +0000308// Placeholder for extending the machine instruction scheduler.
309//===----------------------------------------------------------------------===//
310
311namespace {
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000312class DefaultMachineScheduler : public ScheduleDAGInstrs {
313 MachineScheduler *Pass;
Andrew Trick42b7a712012-01-17 06:55:03 +0000314public:
315 DefaultMachineScheduler(MachineScheduler *P):
Andrew Trickb4566a92012-02-22 06:08:11 +0000316 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false, P->LIS),
317 Pass(P) {}
Andrew Trick42b7a712012-01-17 06:55:03 +0000318
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000319 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
320 /// time to do some work.
Andrew Trick42b7a712012-01-17 06:55:03 +0000321 void Schedule();
322};
323} // namespace
324
325static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
326 return new DefaultMachineScheduler(P);
327}
328static MachineSchedRegistry
329SchedDefaultRegistry("default", "Activate the scheduler pass, "
330 "but don't reorder instructions",
331 createDefaultMachineSched);
332
333
334/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
335/// time to do some work.
336void DefaultMachineScheduler::Schedule() {
337 BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
338
339 DEBUG(dbgs() << "********** MI Scheduling **********\n");
340 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
341 SUnits[su].dumpAll(this));
342
343 // TODO: Put interesting things here.
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000344 //
345 // When this is fully implemented, it will become a subclass of
346 // ScheduleTopDownLive. So this driver will disappear.
Andrew Trick42b7a712012-01-17 06:55:03 +0000347}
348
349//===----------------------------------------------------------------------===//
Andrew Trick5edf2f02012-01-14 02:17:06 +0000350// Machine Instruction Shuffler for Correctness Testing
351//===----------------------------------------------------------------------===//
352
Andrew Trick96f678f2012-01-13 06:30:30 +0000353#ifndef NDEBUG
354namespace {
Andrew Trickb4566a92012-02-22 06:08:11 +0000355// Nodes with a higher number have higher priority. This way we attempt to
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000356// schedule the latest instructions earliest.
357//
358// TODO: Relies on the property of the BuildSchedGraph that results in SUnits
Andrew Trickb4566a92012-02-22 06:08:11 +0000359// being ordered in sequence top-down.
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000360struct ShuffleSUnitOrder {
361 bool operator()(SUnit *A, SUnit *B) const {
Andrew Trickb4566a92012-02-22 06:08:11 +0000362 return A->NodeNum < B->NodeNum;
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000363 }
364};
365
Andrew Trick96f678f2012-01-13 06:30:30 +0000366/// Reorder instructions as much as possible.
Andrew Trick42b7a712012-01-17 06:55:03 +0000367class InstructionShuffler : public ScheduleTopDownLive {
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000368 std::priority_queue<SUnit*, std::vector<SUnit*>, ShuffleSUnitOrder> Queue;
Andrew Trick96f678f2012-01-13 06:30:30 +0000369public:
Andrew Trick42b7a712012-01-17 06:55:03 +0000370 InstructionShuffler(MachineScheduler *P):
371 ScheduleTopDownLive(P) {}
Andrew Trick96f678f2012-01-13 06:30:30 +0000372
Andrew Trickc6cf11b2012-01-17 06:55:07 +0000373 /// ScheduleTopDownLive Interface
374
375 virtual SUnit *pickNode() {
376 if (Queue.empty()) return NULL;
377 SUnit *SU = Queue.top();
378 Queue.pop();
379 return SU;
380 }
381
382 virtual void releaseNode(SUnit *SU) {
383 Queue.push(SU);
Andrew Trick96f678f2012-01-13 06:30:30 +0000384 }
385};
386} // namespace
387
Andrew Trick42b7a712012-01-17 06:55:03 +0000388static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
Andrew Trick96f678f2012-01-13 06:30:30 +0000389 return new InstructionShuffler(P);
390}
391static MachineSchedRegistry ShufflerRegistry("shuffle",
392 "Shuffle machine instructions",
393 createInstructionShuffler);
394#endif // !NDEBUG