blob: 00346bf404c96eb7c86c2b64e352710f6d3fa2b0 [file] [log] [blame]
Chad Rosier42536af2011-11-05 20:16:15 +00001; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
2; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
3
4define i32 @t0(i1 zeroext %a) nounwind {
5 %1 = zext i1 %a to i32
6 ret i32 %1
7}
8
9define i32 @t1(i8 signext %a) nounwind {
10 %1 = sext i8 %a to i32
11 ret i32 %1
12}
13
14define i32 @t2(i8 zeroext %a) nounwind {
15 %1 = zext i8 %a to i32
16 ret i32 %1
17}
18
19define i32 @t3(i16 signext %a) nounwind {
20 %1 = sext i16 %a to i32
21 ret i32 %1
22}
23
24define i32 @t4(i16 zeroext %a) nounwind {
25 %1 = zext i16 %a to i32
26 ret i32 %1
27}
28
29define void @foo(i8 %a, i16 %b) nounwind {
30; ARM: foo
31; THUMB: foo
32;; Materialize i1 1
33; ARM: movw r2, #1
34;; zero-ext
35; ARM: and r2, r2, #1
36; THUMB: and r2, r2, #1
37 %1 = call i32 @t0(i1 zeroext 1)
38; ARM: sxtb r2, r1
39; ARM: mov r0, r2
40; THUMB: sxtb r2, r1
41; THUMB: mov r0, r2
42 %2 = call i32 @t1(i8 signext %a)
43; ARM: uxtb r2, r1
44; ARM: mov r0, r2
45; THUMB: uxtb r2, r1
46; THUMB: mov r0, r2
47 %3 = call i32 @t2(i8 zeroext %a)
48; ARM: sxth r2, r1
49; ARM: mov r0, r2
50; THUMB: sxth r2, r1
51; THUMB: mov r0, r2
52 %4 = call i32 @t3(i16 signext %b)
53; ARM: uxth r2, r1
54; ARM: mov r0, r2
55; THUMB: uxth r2, r1
56; THUMB: mov r0, r2
57 %5 = call i32 @t4(i16 zeroext %b)
58
59;; A few test to check materialization
60;; Note: i1 1 was materialized with t1 call
61; ARM: movw r1, #255
62%6 = call i32 @t2(i8 zeroext 255)
63; ARM: movw r1, #65535
64; THUMB: movw r1, #65535
65%7 = call i32 @t4(i16 zeroext 65535)
66 ret void
67}
Chad Rosier0eff39f2011-11-08 00:03:32 +000068
69define void @foo2() nounwind {
70 %1 = call signext i16 @t5()
71 %2 = call zeroext i16 @t6()
72 %3 = call signext i8 @t7()
73 %4 = call zeroext i8 @t8()
74 %5 = call zeroext i1 @t9()
75 ret void
76}
77
78declare signext i16 @t5();
79declare zeroext i16 @t6();
80declare signext i8 @t7();
81declare zeroext i8 @t8();
82declare zeroext i1 @t9();