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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 0faf46c640c6747f1add89ba06631cebc4fa3afd / . / lib / Target / ARM / ARMISelLowering.h
blob: 2f062ea0becb7e34d33ba15286645ed274553e71 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Craig Topperc1f6f422012-03-17 07:33:42 +0000[diff] [blame]18#include "ARM.h"
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]19#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]20#include "llvm/Target/TargetLowering.h"
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]21#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]22#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]23#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]24#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]25#include <vector>
26
27namespace llvm {
28 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]29
30 namespace ARMISD {
31 // ARM Specific DAG Nodes
32 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]33 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]35
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng53519f02011-01-21 18:55:51 +0000[diff] [blame]38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 // DYN mode.
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000[diff] [blame]40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 // PIC mode.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]43
Manman Ren763a75d2012-06-01 02:44:42 +0000[diff] [blame]44 // Add pseudo op to model memcpy for struct byval.
45 COPY_STRUCT_BYVAL,
46
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]47 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]48 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]54 RET_FLAG, // Return with a flag operand.
55
56 PIC_ADD, // Add with a PC operand and a PIC label.
57
58 CMP, // ARM compare instructions.
Bill Wendlingad5c8802012-06-11 08:07:26 +0000[diff] [blame]59 CMN, // ARM CMN instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]60 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]61 CMPFP, // ARM VFP compare instruction, sets FPSCR.
62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
63 FMSTAT, // ARM fmstat instruction.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]64
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]65 CMOV, // ARM conditional move instructions.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]66 CAND, // ARM conditional and instructions.
67 COR, // ARM conditional or instructions.
68 CXOR, // ARM conditional xor instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]69
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]70 BCC_i64,
71
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]72 RBIT, // ARM bitreverse instruction
73
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]74 FTOSI, // FP to sint within a FP register.
75 FTOUI, // FP to uint within a FP register.
76 SITOF, // sint to FP within a FP register.
77 UITOF, // uint to FP within a FP register.
78
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]82
Evan Cheng342e3162011-08-30 01:34:54 +0000[diff] [blame]83 ADDC, // Add with carry
84 ADDE, // Add using carry
85 SUBC, // Sub with carry
86 SUBE, // Sub using carry
87
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]88 VMOVRRD, // double to two gprs.
89 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]90
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]93
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]94 TC_RETURN, // Tail call return pseudo.
95
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]96 THREAD_POINTER,
97
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]98 DYN_ALLOC, // Dynamic allocation on the stack.
99
Bob Wilsonf74a4292010-10-30 00:54:37 +0000[diff] [blame]100 MEMBARRIER, // Memory barrier (DMB)
101 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Chengdfed19f2010-11-03 06:34:55 +0000[diff] [blame]102
103 PRELOAD, // Preload
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]104
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]105 VCEQ, // Vector compare equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]106 VCEQZ, // Vector compare equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]107 VCGE, // Vector compare greater than or equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]108 VCGEZ, // Vector compare greater than or equal to zero.
109 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]110 VCGEU, // Vector compare unsigned greater than or equal.
111 VCGT, // Vector compare greater than.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]112 VCGTZ, // Vector compare greater than zero.
113 VCLTZ, // Vector compare less than zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]114 VCGTU, // Vector compare unsigned greater than.
115 VTST, // Vector test bits.
116
117 // Vector shift by immediate:
118 VSHL, // ...left
119 VSHRs, // ...right (signed)
120 VSHRu, // ...right (unsigned)
121 VSHLLs, // ...left long (signed)
122 VSHLLu, // ...left long (unsigned)
123 VSHLLi, // ...left long (with maximum shift count)
124 VSHRN, // ...right narrow
125
126 // Vector rounding shift by immediate:
127 VRSHRs, // ...right (signed)
128 VRSHRu, // ...right (unsigned)
129 VRSHRN, // ...right narrow
130
131 // Vector saturating shift by immediate:
132 VQSHLs, // ...left (signed)
133 VQSHLu, // ...left (unsigned)
134 VQSHLsu, // ...left (signed to unsigned)
135 VQSHRNs, // ...right narrow (signed)
136 VQSHRNu, // ...right narrow (unsigned)
137 VQSHRNsu, // ...right narrow (signed to unsigned)
138
139 // Vector saturating rounding shift by immediate:
140 VQRSHRNs, // ...right narrow (signed)
141 VQRSHRNu, // ...right narrow (unsigned)
142 VQRSHRNsu, // ...right narrow (signed to unsigned)
143
144 // Vector shift and insert:
145 VSLI, // ...left
146 VSRI, // ...right
147
148 // Vector get lane (VMOV scalar to ARM core register)
149 // (These are used for 8- and 16-bit element types only.)
150 VGETLANEu, // zero-extend vector extract element
151 VGETLANEs, // sign-extend vector extract element
152
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]153 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]154 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]155 VMVNIMM,
156
Evan Chengeaa192a2011-11-15 02:12:34 +0000[diff] [blame]157 // Vector move f32 immediate:
158 VMOVFPIMM,
159
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]160 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]161 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]162 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]163
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]164 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]165 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]166 VREV64, // reverse elements within 64-bit doublewords
167 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]168 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]169 VZIP, // zip (interleave)
170 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]171 VTRN, // transpose
Bill Wendling69a05a72011-03-14 23:02:38 +0000[diff] [blame]172 VTBL1, // 1-register shuffle with mask
173 VTBL2, // 2-register shuffle with mask
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]174
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000[diff] [blame]175 // Vector multiply long:
176 VMULLs, // ...signed
177 VMULLu, // ...unsigned
178
Arnold Schwaighoferbcc4c1d2012-08-09 15:25:52 +0000[diff] [blame]179 UMLAL, // 64bit Unsigned Accumulate Multiply
180 SMLAL, // 64bit Signed Accumulate Multiply
181
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]182 // Operands of the standard BUILD_VECTOR node are not legalized, which
183 // is fine if BUILD_VECTORs are always lowered to shuffles or other
184 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
185 // operands need to be legalized. Define an ARM-specific version of
186 // BUILD_VECTOR for this purpose.
187 BUILD_VECTOR,
188
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]189 // Floating-point max and min:
190 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]191 FMIN,
192
193 // Bit-field insert
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]194 BFI,
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]195
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]196 // Vector OR with immediate
Owen Anderson080c0922010-11-05 19:27:46 +0000[diff] [blame]197 VORRIMM,
198 // Vector AND with NOT of immediate
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]199 VBICIMM,
200
Cameron Zwarichc0e6d782011-03-30 23:01:21 +0000[diff] [blame]201 // Vector bitwise select
202 VBSL,
203
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]204 // Vector load N-element structure to all lanes:
205 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
206 VLD3DUP,
Bob Wilson1c3ef902011-02-07 17:43:21 +0000[diff] [blame]207 VLD4DUP,
208
209 // NEON loads with post-increment base updates:
210 VLD1_UPD,
211 VLD2_UPD,
212 VLD3_UPD,
213 VLD4_UPD,
214 VLD2LN_UPD,
215 VLD3LN_UPD,
216 VLD4LN_UPD,
217 VLD2DUP_UPD,
218 VLD3DUP_UPD,
219 VLD4DUP_UPD,
220
221 // NEON stores with post-increment base updates:
222 VST1_UPD,
223 VST2_UPD,
224 VST3_UPD,
225 VST4_UPD,
226 VST2LN_UPD,
227 VST3LN_UPD,
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]228 VST4LN_UPD,
229
230 // 64-bit atomic ops (value split into two registers)
231 ATOMADD64_DAG,
232 ATOMSUB64_DAG,
233 ATOMOR64_DAG,
234 ATOMXOR64_DAG,
235 ATOMAND64_DAG,
236 ATOMNAND64_DAG,
237 ATOMSWAP64_DAG,
238 ATOMCMPXCHG64_DAG
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]239 };
240 }
241
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]242 /// Define some predicates that are used for node matching.
243 namespace ARM {
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]244 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]245 }
246
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]247 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]248 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]249
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]250 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]251 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]252 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]253
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]254 virtual unsigned getJumpTableEncoding(void) const;
255
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]256 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]257
258 /// ReplaceNodeResults - Replace the results of node with an illegal result
259 /// type with new values built out of custom code.
260 ///
261 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]262 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]263
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]264 virtual const char *getTargetNodeName(unsigned Opcode) const;
265
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]266 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
267 virtual EVT getSetCCResultType(EVT VT) const;
268
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]269 virtual MachineBasicBlock *
270 EmitInstrWithCustomInserter(MachineInstr *MI,
271 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]272
Evan Cheng37fefc22011-08-30 19:09:48 +0000[diff] [blame]273 virtual void
274 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
275
Evan Chenge721f5c2011-07-13 00:42:17 +0000[diff] [blame]276 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Cheng31959b12011-02-02 01:06:55 +0000[diff] [blame]277 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
278
279 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
280
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]281 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
282 /// unaligned memory accesses. of the specified type.
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]283 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
284
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]285 virtual EVT getOptimalMemOpType(uint64_t Size,
286 unsigned DstAlign, unsigned SrcAlign,
Lang Hamesa1e78882011-11-02 23:37:04 +0000[diff] [blame]287 bool IsZeroVal,
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]288 bool MemcpyStrSrc,
289 MachineFunction &MF) const;
290
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]291 /// isLegalAddressingMode - Return true if the addressing mode represented
292 /// by AM is legal for this target, for a load/store of the specified type.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]293 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]294 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]295
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]296 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]297 /// icmp immediate, that is the target has icmp instructions which can
298 /// compare a register against the immediate without having to materialize
299 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]300 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]301
Dan Gohmancca82142011-05-03 00:46:49 +0000[diff] [blame]302 /// isLegalAddImmediate - Return true if the specified immediate is legal
303 /// add immediate, that is the target has add instructions which can
304 /// add a register and the immediate without having to materialize
305 /// the immediate into a register.
306 virtual bool isLegalAddImmediate(int64_t Imm) const;
307
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]308 /// getPreIndexedAddressParts - returns true by value, base pointer and
309 /// offset pointer and addressing mode by reference if the node's address
310 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]311 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
312 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]313 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]314 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]315
316 /// getPostIndexedAddressParts - returns true by value, base pointer and
317 /// offset pointer and addressing mode by reference if this node can be
318 /// combined with a load / store to form a post-indexed load / store.
319 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]320 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]321 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]322 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]323
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]324 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]325 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]326 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]327 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]328 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]329
330
Evan Cheng55d42002011-01-08 01:24:27 +0000[diff] [blame]331 virtual bool ExpandInlineAsm(CallInst *CI) const;
332
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]333 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]334
335 /// Examine constraint string and operand type and determine a weight value.
336 /// The operand object must already have been set up with the operand type.
337 ConstraintWeight getSingleConstraintMatchWeight(
338 AsmOperandInfo &info, const char *constraint) const;
339
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]340 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]341 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]342 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]343
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]344 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
345 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
346 /// true it means one of the asm constraint of the inline asm instruction
347 /// being processed is 'm'.
348 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]349 std::string &Constraint,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]350 std::vector<SDValue> &Ops,
351 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]352
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]353 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]354 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]355 }
356
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]357 /// getRegClassFor - Return the register class that should be used for the
358 /// specified value type.
Craig Topper44d23822012-02-22 05:59:10 +0000[diff] [blame]359 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]360
Anton Korobeynikovcec36f42010-07-24 21:52:08 +0000[diff] [blame]361 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
362 /// be used for loads / stores from the global.
363 virtual unsigned getMaximalGlobalOffset() const;
364
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]365 /// createFastISel - This method returns a target specific FastISel object,
366 /// or null if the target does not support "fast" ISel.
Bob Wilsond49edb72012-08-03 04:06:28 +0000[diff] [blame]367 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
368 const TargetLibraryInfo *libInfo) const;
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]369
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]370 Sched::Preference getSchedulingPreference(SDNode *N) const;
371
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]372 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]373 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]374
375 /// isFPImmLegal - Returns true if the target can instruction select the
376 /// specified FP immediate natively. If false, the legalizer will
377 /// materialize the FP immediate as a load from a constant pool.
378 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
379
Bob Wilson65ffec42010-09-21 17:56:22 +0000[diff] [blame]380 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
381 const CallInst &I,
382 unsigned Intrinsic) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]383 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]384 std::pair<const TargetRegisterClass*, uint8_t>
385 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]386
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]387 private:
388 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
389 /// make the right decision when generating code for different targets.
390 const ARMSubtarget *Subtarget;
391
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]392 const TargetRegisterInfo *RegInfo;
393
Evan Cheng3ef1c872010-09-10 01:29:16 +0000[diff] [blame]394 const InstrItineraryData *Itins;
395
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]396 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]397 ///
398 unsigned ARMPCLabelIndex;
399
Craig Topper0faf46c2012-08-12 03:16:37 +0000[diff] [blame^]400 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
401 void addDRTypeForNEON(MVT VT);
402 void addQRTypeForNEON(MVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]403
404 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]405 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]406 SDValue Chain, SDValue &Arg,
407 RegsToPassVector &RegsToPass,
408 CCValAssign &VA, CCValAssign &NextVA,
409 SDValue &StackPtr,
410 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]411 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]412 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]413 SDValue &Root, SelectionDAG &DAG,
414 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]415
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]416 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
417 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]418 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
419 DebugLoc dl, SelectionDAG &DAG,
420 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]421 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]422 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]423 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]424 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]425 const ARMSubtarget *Subtarget) const;
426 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
429 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]430 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]431 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]432 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgfd5abd52012-05-04 09:40:39 +0000[diff] [blame]433 SelectionDAG &DAG,
434 TLSModel::Model model) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]435 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendlingde2b1512010-08-11 08:43:16 +0000[diff] [blame]437 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]438 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]440 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]441 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]442 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]443 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]445 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hames45b5f882012-03-15 18:49:02 +0000[diff] [blame]446 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
447 const ARMSubtarget *ST) const;
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]448 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson11a1dff2011-01-07 21:37:30 +0000[diff] [blame]449 const ARMSubtarget *ST) const;
450
451 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]452
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]453 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]454 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]455 const SmallVectorImpl<ISD::InputArg> &Ins,
456 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]457 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]458
459 virtual SDValue
460 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]461 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]462 const SmallVectorImpl<ISD::InputArg> &Ins,
463 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]464 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]465
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]466 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
467 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
468 const;
469
470 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
471 unsigned &VARegSize, unsigned &VARegSaveSize) const;
472
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]473 virtual SDValue
Justin Holewinskid2ea0e12012-05-25 16:35:28 +0000[diff] [blame]474 LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]475 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]476
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]477 /// HandleByVal - Target-specific cleanup for ByVal support.
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]478 virtual void HandleByVal(CCState *, unsigned &) const;
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]479
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]480 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
481 /// for tail call optimization. Targets which want to do tail call
482 /// optimization should implement this function.
483 bool IsEligibleForTailCallOptimization(SDValue Callee,
484 CallingConv::ID CalleeCC,
485 bool isVarArg,
486 bool isCalleeStructRet,
487 bool isCallerStructRet,
488 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]489 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]490 const SmallVectorImpl<ISD::InputArg> &Ins,
491 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]492 virtual SDValue
493 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]494 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]495 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]496 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]497 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]498
Evan Chengbf010eb2012-04-10 01:51:00 +0000[diff] [blame]499 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
Evan Cheng3d2125c2010-11-30 23:55:39 +0000[diff] [blame]500
Evan Cheng485fafc2011-03-21 01:19:09 +0000[diff] [blame]501 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
502
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]503 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]504 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
505 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
506 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson79f56c92011-03-08 01:17:20 +0000[diff] [blame]507 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]508
509 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]510
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]511 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
512 MachineBasicBlock *BB,
513 unsigned Size) const;
514 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
515 MachineBasicBlock *BB,
516 unsigned Size,
517 unsigned BinOpcode) const;
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]518 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
519 MachineBasicBlock *BB,
520 unsigned Op1,
521 unsigned Op2,
Eli Friedman4d3f3292011-08-31 17:52:22 +0000[diff] [blame]522 bool NeedsCarry = false,
523 bool IsCmpxchg = false) const;
Jim Grosbachf7da8822011-04-26 19:44:18 +0000[diff] [blame]524 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
525 MachineBasicBlock *BB,
526 unsigned Size,
527 bool signExtend,
528 ARMCC::CondCodes Cond) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]529
Bill Wendlinge29fa1d2011-10-06 22:18:16 +0000[diff] [blame]530 void SetupEntryBlockForSjLj(MachineInstr *MI,
531 MachineBasicBlock *MBB,
532 MachineBasicBlock *DispatchBB, int FI) const;
533
Bill Wendlingf7e4aef2011-10-03 21:25:38 +0000[diff] [blame]534 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
535 MachineBasicBlock *MBB) const;
536
Andrew Trick1c3af772011-04-23 03:55:32 +0000[diff] [blame]537 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Manman Ren68f25572012-06-01 19:33:18 +0000[diff] [blame]538
539 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
540 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]541 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]542
Owen Anderson36fa3ea2010-11-05 21:57:54 +0000[diff] [blame]543 enum NEONModImmType {
544 VMOVModImm,
545 VMVNModImm,
546 OtherModImm
547 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]548
549
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]550 namespace ARM {
Bob Wilsond49edb72012-08-03 04:06:28 +0000[diff] [blame]551 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
552 const TargetLibraryInfo *libInfo);
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]553 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]554}
555
556#endif // ARMISELLOWERING_H