blob: a6e1ca3128ee6b61fb03f32e02a31eee2e61a98b [file] [log] [blame]
Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
John Criswell856ba762003-10-21 15:17:13 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
John Criswell856ba762003-10-21 15:17:13 +00007//
8//===----------------------------------------------------------------------===//
Chris Lattner762fb5f2003-08-03 15:47:49 +00009//
10// This is a target description file for the Intel i386 architecture, refered to
11// here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattnerc8f45872003-08-04 04:59:56 +000015// Get the target-independent interfaces which we are implementing...
Chris Lattner762fb5f2003-08-03 15:47:49 +000016//
Evan Cheng027fdbe2008-11-24 07:34:46 +000017include "llvm/Target/Target.td"
Chris Lattner762fb5f2003-08-03 15:47:49 +000018
19//===----------------------------------------------------------------------===//
Evan Chenga26eb5e2006-10-06 09:17:41 +000020// X86 Subtarget features.
Bill Wendling4222d802007-05-04 20:38:40 +000021//===----------------------------------------------------------------------===//
Chris Lattner70084162009-09-02 05:53:04 +000022
23def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
24 "Enable conditional move instructions">;
25
Bill Wendling4222d802007-05-04 20:38:40 +000026def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
27 "Enable MMX instructions">;
28def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
29 "Enable SSE instructions",
Chris Lattner70084162009-09-02 05:53:04 +000030 // SSE codegen depends on cmovs, and all
31 // SSE1+ processors support them.
32 [FeatureMMX, FeatureCMOV]>;
Bill Wendling4222d802007-05-04 20:38:40 +000033def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
34 "Enable SSE2 instructions",
35 [FeatureSSE1]>;
36def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
37 "Enable SSE3 instructions",
38 [FeatureSSE2]>;
39def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
40 "Enable SSSE3 instructions",
41 [FeatureSSE3]>;
Nate Begeman63ec90a2008-02-03 07:18:54 +000042def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
43 "Enable SSE 4.1 instructions",
44 [FeatureSSSE3]>;
45def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
46 "Enable SSE 4.2 instructions",
47 [FeatureSSE41]>;
Bill Wendling4222d802007-05-04 20:38:40 +000048def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
49 "Enable 3DNow! instructions">;
50def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
Bill Wendling11d8fda2007-05-06 07:56:19 +000051 "Enable 3DNow! Athlon instructions",
52 [Feature3DNow]>;
Dan Gohmanf75e5b42009-02-03 00:04:43 +000053// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
54// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
55// without disabling 64-bit mode.
Bill Wendling11d8fda2007-05-06 07:56:19 +000056def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
Dan Gohmanf75e5b42009-02-03 00:04:43 +000057 "Support 64-bit instructions">;
Evan Chengccb69762009-01-02 05:35:45 +000058def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
59 "Bit testing of memory is slow">;
Stefanus Du Toit8cf5ab12009-05-26 21:04:35 +000060def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
61 "Support SSE 4a instructions">;
Evan Chenga26eb5e2006-10-06 09:17:41 +000062
David Greene343dadb2009-06-26 22:46:54 +000063def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
64 "Enable AVX instructions">;
65def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
Sean Callanan108934c2009-12-18 00:01:26 +000066 "Enable three-operand fused multiple-add">;
David Greene343dadb2009-06-26 22:46:54 +000067def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
68 "Enable four-operand fused multiple-add">;
69
Evan Chenga26eb5e2006-10-06 09:17:41 +000070//===----------------------------------------------------------------------===//
71// X86 processors supported.
72//===----------------------------------------------------------------------===//
73
74class Proc<string Name, list<SubtargetFeature> Features>
75 : Processor<Name, NoItineraries, Features>;
76
77def : Proc<"generic", []>;
78def : Proc<"i386", []>;
79def : Proc<"i486", []>;
Dale Johannesen2194d462008-10-14 22:06:33 +000080def : Proc<"i586", []>;
Evan Chenga26eb5e2006-10-06 09:17:41 +000081def : Proc<"pentium", []>;
82def : Proc<"pentium-mmx", [FeatureMMX]>;
83def : Proc<"i686", []>;
Chris Lattner70084162009-09-02 05:53:04 +000084def : Proc<"pentiumpro", [FeatureCMOV]>;
85def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
Bill Wendlingcd6cea02007-05-22 05:15:37 +000086def : Proc<"pentium3", [FeatureSSE1]>;
Evan Chengccb69762009-01-02 05:35:45 +000087def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
Bill Wendlingcd6cea02007-05-22 05:15:37 +000088def : Proc<"pentium4", [FeatureSSE2]>;
Dan Gohmanf75e5b42009-02-03 00:04:43 +000089def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
Evan Chengccb69762009-01-02 05:35:45 +000090def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
91def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
92def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
93def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
94def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
Evan Cheng0be6d3f2009-01-03 04:24:44 +000095def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
96def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
David Greene343dadb2009-06-26 22:46:54 +000097def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
98// Sandy Bridge does not have FMA
99def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>;
Evan Chenga26eb5e2006-10-06 09:17:41 +0000100
101def : Proc<"k6", [FeatureMMX]>;
Bill Wendlingcd6cea02007-05-22 05:15:37 +0000102def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
103def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
Evan Chengccb69762009-01-02 05:35:45 +0000104def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
105def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
106def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
107def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
108def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
Dan Gohmanf75e5b42009-02-03 00:04:43 +0000109def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
110 FeatureSlowBTMem]>;
111def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
112 FeatureSlowBTMem]>;
113def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
114 FeatureSlowBTMem]>;
115def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
116 FeatureSlowBTMem]>;
Stefanus Du Toit8cf5ab12009-05-26 21:04:35 +0000117def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
118 FeatureSlowBTMem]>;
119def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
120 FeatureSlowBTMem]>;
121def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
122 FeatureSlowBTMem]>;
123def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
124 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
125def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
126 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
David Greene3016af52009-06-29 16:54:06 +0000127def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
128 Feature3DNowA]>;
129def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
130 Feature3DNowA]>;
Evan Chenga26eb5e2006-10-06 09:17:41 +0000131
132def : Proc<"winchip-c6", [FeatureMMX]>;
133def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
134def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
Bill Wendlingcd6cea02007-05-22 05:15:37 +0000135def : Proc<"c3-2", [FeatureSSE1]>;
Evan Chenga26eb5e2006-10-06 09:17:41 +0000136
137//===----------------------------------------------------------------------===//
Chris Lattner762fb5f2003-08-03 15:47:49 +0000138// Register File Description
139//===----------------------------------------------------------------------===//
140
141include "X86RegisterInfo.td"
142
Chris Lattnerb77eb782003-08-03 18:19:37 +0000143//===----------------------------------------------------------------------===//
144// Instruction Descriptions
145//===----------------------------------------------------------------------===//
146
Chris Lattner1cca5e32003-08-03 21:54:21 +0000147include "X86InstrInfo.td"
148
Chris Lattnerb77eb782003-08-03 18:19:37 +0000149def X86InstrInfo : InstrInfo {
Chris Lattner1cca5e32003-08-03 21:54:21 +0000150
151 // Define how we want to layout our TargetSpecific information field... This
152 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
John Criswell4ffff9e2004-04-08 20:31:47 +0000153 let TSFlagsFields = ["FormBits",
154 "hasOpSizePrefix",
Evan Cheng25ab6902006-09-08 06:48:29 +0000155 "hasAdSizePrefix",
John Criswell4ffff9e2004-04-08 20:31:47 +0000156 "Prefix",
Evan Cheng25ab6902006-09-08 06:48:29 +0000157 "hasREX_WPrefix",
John Criswell4ffff9e2004-04-08 20:31:47 +0000158 "ImmTypeBits",
159 "FPFormBits",
Andrew Lenharthea7da502008-03-01 13:37:02 +0000160 "hasLockPrefix",
Anton Korobeynikovef93cec2008-10-11 19:09:15 +0000161 "SegOvrBits",
John Criswell4ffff9e2004-04-08 20:31:47 +0000162 "Opcode"];
163 let TSFlagsShifts = [0,
John Criswell4ffff9e2004-04-08 20:31:47 +0000164 6,
Evan Cheng3c55c542006-02-01 06:13:50 +0000165 7,
Evan Cheng25ab6902006-09-08 06:48:29 +0000166 8,
167 12,
Evan Cheng3c55c542006-02-01 06:13:50 +0000168 13,
Evan Cheng25ab6902006-09-08 06:48:29 +0000169 16,
Andrew Lenharthea7da502008-03-01 13:37:02 +0000170 19,
Anton Korobeynikovef93cec2008-10-11 19:09:15 +0000171 20,
Evan Cheng25ab6902006-09-08 06:48:29 +0000172 24];
Chris Lattnerb77eb782003-08-03 18:19:37 +0000173}
174
Chris Lattner31c8a6d2007-02-26 18:17:14 +0000175//===----------------------------------------------------------------------===//
176// Calling Conventions
177//===----------------------------------------------------------------------===//
178
179include "X86CallingConv.td"
180
181
182//===----------------------------------------------------------------------===//
183// Assembly Printers
184//===----------------------------------------------------------------------===//
185
Daniel Dunbar0e2771f2009-07-29 00:02:19 +0000186// Currently the X86 assembly parser only supports ATT syntax.
187def ATTAsmParser : AsmParser {
188 string AsmParserClassName = "ATTAsmParser";
189 int Variant = 0;
Daniel Dunbar59fc42d2009-08-11 20:59:47 +0000190
191 // Discard comments in assembly strings.
192 string CommentDelimiter = "#";
193
194 // Recognize hard coded registers.
195 string RegisterPrefix = "%";
Daniel Dunbar0e2771f2009-07-29 00:02:19 +0000196}
197
Chris Lattner9a3e49a2004-10-03 20:36:57 +0000198// The X86 target supports two different syntaxes for emitting machine code.
199// This is controlled by the -x86-asm-syntax={att|intel}
200def ATTAsmWriter : AsmWriter {
Chris Lattnercae05cb2009-09-13 19:30:11 +0000201 string AsmWriterClassName = "ATTInstPrinter";
Chris Lattner9a3e49a2004-10-03 20:36:57 +0000202 int Variant = 0;
203}
204def IntelAsmWriter : AsmWriter {
Chris Lattner70576412009-09-20 07:47:59 +0000205 string AsmWriterClassName = "IntelInstPrinter";
Chris Lattner9a3e49a2004-10-03 20:36:57 +0000206 int Variant = 1;
207}
208
Chris Lattnerb77eb782003-08-03 18:19:37 +0000209def X86 : Target {
Chris Lattnerb77eb782003-08-03 18:19:37 +0000210 // Information about the instructions...
Chris Lattnerc8f45872003-08-04 04:59:56 +0000211 let InstructionSet = X86InstrInfo;
Chris Lattner9a3e49a2004-10-03 20:36:57 +0000212
Daniel Dunbar0e2771f2009-07-29 00:02:19 +0000213 let AssemblyParsers = [ATTAsmParser];
214
Chris Lattner9a3e49a2004-10-03 20:36:57 +0000215 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
Chris Lattnerb77eb782003-08-03 18:19:37 +0000216}