Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 26 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 29 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 30 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 31 | [SDTCisVT<0, OtherVT>, |
| 32 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 33 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 34 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 35 | [SDTCisVT<0, i8>, |
| 36 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 37 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 38 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
| 39 | SDTCisVT<2, i8>]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 40 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 41 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 42 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 43 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 44 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 45 | |
Bill Wendling | c69107c | 2007-11-13 09:19:02 +0000 | [diff] [blame] | 46 | def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; |
| 47 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, |
| 48 | SDTCisVT<1, i32> ]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 49 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 50 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 51 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 52 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 53 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 54 | def SDTX86RdTsc : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 55 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 56 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 57 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 58 | def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>; |
| 59 | |
| 60 | def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; |
| 61 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 62 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 63 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 64 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 65 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 66 | def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>; |
| 67 | def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 68 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 69 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 70 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 71 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 72 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 73 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 74 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 75 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 76 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 77 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 78 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
| 79 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 80 | SDNPMayLoad]>; |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 81 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, |
| 82 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 83 | SDNPMayLoad]>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 84 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
| 85 | [SDNPHasChain, SDNPMayStore, |
| 86 | SDNPMayLoad, SDNPMemOperand]>; |
| 87 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
| 88 | [SDNPHasChain, SDNPMayStore, |
| 89 | SDNPMayLoad, SDNPMemOperand]>; |
| 90 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
| 91 | [SDNPHasChain, SDNPMayStore, |
| 92 | SDNPMayLoad, SDNPMemOperand]>; |
| 93 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
| 94 | [SDNPHasChain, SDNPMayStore, |
| 95 | SDNPMayLoad, SDNPMemOperand]>; |
| 96 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
| 97 | [SDNPHasChain, SDNPMayStore, |
| 98 | SDNPMayLoad, SDNPMemOperand]>; |
| 99 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
| 100 | [SDNPHasChain, SDNPMayStore, |
| 101 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 102 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
| 103 | [SDNPHasChain, SDNPMayStore, |
| 104 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 105 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
| 106 | [SDNPHasChain, SDNPOptInFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 107 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 108 | def X86callseq_start : |
| 109 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Evan Cheng | bb7b844 | 2006-08-11 09:03:33 +0000 | [diff] [blame] | 110 | [SDNPHasChain, SDNPOutFlag]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 111 | def X86callseq_end : |
| 112 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 113 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 114 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 115 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
| 116 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 117 | |
Evan Cheng | fb914c4 | 2006-05-20 01:40:16 +0000 | [diff] [blame] | 118 | def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call, |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 119 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; |
| 120 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 121 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 122 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 123 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 124 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, |
| 125 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 126 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 127 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc, |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 128 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 129 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 130 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 131 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 132 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 133 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 134 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 135 | def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>; |
| 136 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 137 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 138 | [SDNPHasChain]>; |
| 139 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 140 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
| 141 | [SDNPHasChain, SDNPOptInFlag]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 142 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 143 | //===----------------------------------------------------------------------===// |
| 144 | // X86 Operand Definitions. |
| 145 | // |
| 146 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 147 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 148 | // |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 149 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 150 | let PrintMethod = printMethod; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 151 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 152 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 153 | |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 154 | def i8mem : X86MemOperand<"printi8mem">; |
| 155 | def i16mem : X86MemOperand<"printi16mem">; |
| 156 | def i32mem : X86MemOperand<"printi32mem">; |
| 157 | def i64mem : X86MemOperand<"printi64mem">; |
Evan Cheng | 470a6ad | 2006-02-22 02:26:30 +0000 | [diff] [blame] | 158 | def i128mem : X86MemOperand<"printi128mem">; |
Chris Lattner | 4543251 | 2005-12-17 19:47:05 +0000 | [diff] [blame] | 159 | def f32mem : X86MemOperand<"printf32mem">; |
| 160 | def f64mem : X86MemOperand<"printf64mem">; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 161 | def f80mem : X86MemOperand<"printf80mem">; |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 162 | def f128mem : X86MemOperand<"printf128mem">; |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 163 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 164 | def lea32mem : Operand<i32> { |
| 165 | let PrintMethod = "printi32mem"; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 166 | let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm); |
| 167 | } |
| 168 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 169 | def SSECC : Operand<i8> { |
| 170 | let PrintMethod = "printSSECC"; |
| 171 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 172 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 173 | def piclabel: Operand<i32> { |
| 174 | let PrintMethod = "printPICLabel"; |
| 175 | } |
| 176 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 177 | // A couple of more descriptive operand definitions. |
| 178 | // 16-bits but only 8 bits are significant. |
| 179 | def i16i8imm : Operand<i16>; |
| 180 | // 32-bits but only 8 bits are significant. |
| 181 | def i32i8imm : Operand<i32>; |
| 182 | |
Evan Cheng | d35b8c1 | 2005-12-04 08:19:43 +0000 | [diff] [blame] | 183 | // Branch targets have OtherVT type. |
| 184 | def brtarget : Operand<OtherVT>; |
| 185 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 186 | //===----------------------------------------------------------------------===// |
| 187 | // X86 Complex Pattern Definitions. |
| 188 | // |
| 189 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 190 | // Define X86 specific addressing mode. |
Evan Cheng | af9db75 | 2006-10-11 21:03:53 +0000 | [diff] [blame] | 191 | def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 192 | def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr", |
Evan Cheng | af9db75 | 2006-10-11 21:03:53 +0000 | [diff] [blame] | 193 | [add, mul, shl, or, frameindex], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 194 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 195 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 196 | // X86 Instruction Predicate Definitions. |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 197 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
| 198 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
| 199 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 200 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 201 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 202 | def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; |
| 203 | def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 204 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 205 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 206 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">; |
| 207 | def In64BitMode : Predicate<"Subtarget->is64Bit()">; |
| 208 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 209 | def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">; |
| 210 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 211 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 212 | |
| 213 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 214 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 215 | // |
| 216 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 217 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 218 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 219 | //===----------------------------------------------------------------------===// |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 220 | // Pattern fragments... |
| 221 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 222 | |
| 223 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 224 | // X86InstrInfo.h. They must be kept in synch. |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 225 | def X86_COND_A : PatLeaf<(i8 0)>; |
| 226 | def X86_COND_AE : PatLeaf<(i8 1)>; |
| 227 | def X86_COND_B : PatLeaf<(i8 2)>; |
| 228 | def X86_COND_BE : PatLeaf<(i8 3)>; |
| 229 | def X86_COND_E : PatLeaf<(i8 4)>; |
| 230 | def X86_COND_G : PatLeaf<(i8 5)>; |
| 231 | def X86_COND_GE : PatLeaf<(i8 6)>; |
| 232 | def X86_COND_L : PatLeaf<(i8 7)>; |
| 233 | def X86_COND_LE : PatLeaf<(i8 8)>; |
| 234 | def X86_COND_NE : PatLeaf<(i8 9)>; |
| 235 | def X86_COND_NO : PatLeaf<(i8 10)>; |
| 236 | def X86_COND_NP : PatLeaf<(i8 11)>; |
| 237 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Bill Wendling | 3fafd93 | 2008-11-26 22:37:40 +0000 | [diff] [blame] | 238 | def X86_COND_NC : PatLeaf<(i8 13)>; |
| 239 | def X86_COND_O : PatLeaf<(i8 14)>; |
| 240 | def X86_COND_P : PatLeaf<(i8 15)>; |
| 241 | def X86_COND_S : PatLeaf<(i8 16)>; |
| 242 | def X86_COND_C : PatLeaf<(i8 17)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 243 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 244 | def i16immSExt8 : PatLeaf<(i16 imm), [{ |
| 245 | // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 246 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 247 | return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 248 | }]>; |
| 249 | |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 250 | def i32immSExt8 : PatLeaf<(i32 imm), [{ |
| 251 | // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 252 | // sign extended field. |
Dan Gohman | f5aeb1a | 2008-09-12 16:56:44 +0000 | [diff] [blame] | 253 | return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); |
Evan Cheng | b355854 | 2005-12-13 00:01:09 +0000 | [diff] [blame] | 254 | }]>; |
| 255 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 256 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 257 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 258 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 259 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 260 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 261 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 262 | if (ExtType == ISD::NON_EXTLOAD) |
| 263 | return true; |
| 264 | if (ExtType == ISD::EXTLOAD) |
| 265 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 266 | return false; |
| 267 | }]>; |
| 268 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 269 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 270 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 271 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 272 | if (ExtType == ISD::EXTLOAD) |
| 273 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 274 | return false; |
| 275 | }]>; |
| 276 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 277 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 278 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 279 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 280 | if (ExtType == ISD::NON_EXTLOAD) |
| 281 | return true; |
| 282 | if (ExtType == ISD::EXTLOAD) |
| 283 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 284 | return false; |
| 285 | }]>; |
| 286 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 287 | def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 288 | LoadSDNode *LD = cast<LoadSDNode>(N); |
| 289 | if (LD->isVolatile()) |
| 290 | return false; |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 291 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 292 | if (ExtType == ISD::NON_EXTLOAD) |
| 293 | return true; |
| 294 | if (ExtType == ISD::EXTLOAD) |
| 295 | return LD->getAlignment() >= 4; |
| 296 | return false; |
| 297 | }]>; |
| 298 | |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 299 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 300 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; |
Evan Cheng | 06a8aa1 | 2006-03-17 19:55:52 +0000 | [diff] [blame] | 301 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 302 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 303 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 304 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 305 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 306 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 307 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 308 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 309 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 310 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 311 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 312 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 313 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 314 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 315 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 316 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 317 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 318 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 319 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 320 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 321 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 322 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 323 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 324 | |
| 325 | // An 'and' node with a single use. |
| 326 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 327 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 328 | }]>; |
| 329 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 330 | // 'shld' and 'shrd' instruction patterns. Note that even though these have |
| 331 | // the srl and shl in their patterns, the C++ code must still check for them, |
| 332 | // because predicates are tested before children nodes are explored. |
| 333 | |
| 334 | def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 335 | (or (srl node:$src1, node:$amt1), |
| 336 | (shl node:$src2, node:$amt2)), [{ |
| 337 | assert(N->getOpcode() == ISD::OR); |
| 338 | return N->getOperand(0).getOpcode() == ISD::SRL && |
| 339 | N->getOperand(1).getOpcode() == ISD::SHL && |
| 340 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 341 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 342 | N->getOperand(0).getConstantOperandVal(1) == |
| 343 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 344 | }]>; |
| 345 | |
| 346 | def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2), |
| 347 | (or (shl node:$src1, node:$amt1), |
| 348 | (srl node:$src2, node:$amt2)), [{ |
| 349 | assert(N->getOpcode() == ISD::OR); |
| 350 | return N->getOperand(0).getOpcode() == ISD::SHL && |
| 351 | N->getOperand(1).getOpcode() == ISD::SRL && |
| 352 | isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) && |
| 353 | isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) && |
| 354 | N->getOperand(0).getConstantOperandVal(1) == |
| 355 | N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1); |
| 356 | }]>; |
| 357 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 358 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 359 | // Instruction list... |
| 360 | // |
| 361 | |
Chris Lattner | f18c074 | 2006-10-12 17:42:56 +0000 | [diff] [blame] | 362 | // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into |
| 363 | // a stack adjustment and the codegen must know that they may modify the stack |
| 364 | // pointer before prolog-epilog rewriting occurs. |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 365 | // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become |
| 366 | // sub / add which can clobber EFLAGS. |
Evan Cheng | 8decf6b | 2007-09-28 01:19:48 +0000 | [diff] [blame] | 367 | let Defs = [ESP, EFLAGS], Uses = [ESP] in { |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 368 | def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt), |
| 369 | "#ADJCALLSTACKDOWN", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 370 | [(X86callseq_start timm:$amt)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 371 | Requires<[In32BitMode]>; |
| 372 | def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), |
| 373 | "#ADJCALLSTACKUP", |
Chris Lattner | e563bbc | 2008-10-11 22:08:30 +0000 | [diff] [blame] | 374 | [(X86callseq_end timm:$amt1, timm:$amt2)]>, |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 375 | Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 376 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 377 | |
| 378 | // Nop |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 379 | let neverHasSideEffects = 1 in |
| 380 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 381 | |
Evan Cheng | 0475ab5 | 2008-01-05 00:41:47 +0000 | [diff] [blame] | 382 | // PIC base |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 383 | let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 384 | def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label), |
| 385 | "call\t$label\n\tpop{l}\t$reg", []>; |
Evan Cheng | 8f7f712 | 2006-05-05 05:40:20 +0000 | [diff] [blame] | 386 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 387 | //===----------------------------------------------------------------------===// |
| 388 | // Control Flow Instructions... |
| 389 | // |
| 390 | |
Chris Lattner | 1be4811 | 2005-05-13 17:56:48 +0000 | [diff] [blame] | 391 | // Return instructions. |
Evan Cheng | 2b4ea79 | 2005-12-26 09:11:45 +0000 | [diff] [blame] | 392 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 393 | hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in { |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 394 | def RET : I <0xC3, RawFrm, (outs), (ins variable_ops), |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 395 | "ret", |
Dan Gohman | e4c67cd | 2008-05-31 02:11:25 +0000 | [diff] [blame] | 396 | [(X86retflag 0)]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 397 | def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), |
| 398 | "ret\t$amt", |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 399 | [(X86retflag imm:$amt)]>; |
Evan Cheng | 171049d | 2005-12-23 22:14:32 +0000 | [diff] [blame] | 400 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 401 | |
| 402 | // All branches are RawFrm, Void, Branch, and Terminators |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 403 | let isBranch = 1, isTerminator = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 404 | class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> : |
| 405 | I<opcode, RawFrm, (outs), ins, asm, pattern>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 406 | |
Evan Cheng | ec3bc39 | 2006-09-07 19:03:48 +0000 | [diff] [blame] | 407 | let isBranch = 1, isBarrier = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 408 | def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 409 | |
Owen Anderson | 20ab290 | 2007-11-12 07:39:39 +0000 | [diff] [blame] | 410 | // Indirect branches |
| 411 | let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 412 | def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 413 | [(brind GR32:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 414 | def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 415 | [(brind (loadi32 addr:$dst))]>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | // Conditional branches |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 419 | let Uses = [EFLAGS] in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 420 | def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 421 | [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 422 | def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 423 | [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 424 | def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 425 | [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 426 | def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 427 | [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 428 | def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 429 | [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 430 | def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 431 | [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 432 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 433 | def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 434 | [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 435 | def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 436 | [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 437 | def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 438 | [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 439 | def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 440 | [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 441 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 442 | def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 443 | [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 444 | def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 445 | [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 446 | def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 447 | [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 448 | def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 449 | [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 450 | def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 451 | [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 452 | def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 453 | [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB; |
Bill Wendling | 3fafd93 | 2008-11-26 22:37:40 +0000 | [diff] [blame] | 454 | def JC : IBr<0x82, (ins brtarget:$dst), "jc\t$dst", |
| 455 | [(X86brcond bb:$dst, X86_COND_C, EFLAGS)]>, TB; |
| 456 | def JNC : IBr<0x83, (ins brtarget:$dst), "jnc\t$dst", |
| 457 | [(X86brcond bb:$dst, X86_COND_NC, EFLAGS)]>, TB; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 458 | } // Uses = [EFLAGS] |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 459 | |
| 460 | //===----------------------------------------------------------------------===// |
| 461 | // Call Instructions... |
| 462 | // |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 463 | let isCall = 1 in |
Dan Gohman | 6d4b052 | 2008-10-01 18:28:06 +0000 | [diff] [blame] | 464 | // All calls clobber the non-callee saved registers. ESP is marked as |
| 465 | // a use to prevent stack-pointer assignments that appear immediately |
| 466 | // before calls from potentially appearing dead. Uses for argument |
| 467 | // registers are added manually. |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 468 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Bill Wendling | 3f3a17d | 2007-04-25 21:31:48 +0000 | [diff] [blame] | 469 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
Evan Cheng | 109a562 | 2008-10-17 21:02:22 +0000 | [diff] [blame] | 470 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 471 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], |
Dan Gohman | 2662d55 | 2008-10-01 04:14:30 +0000 | [diff] [blame] | 472 | Uses = [ESP] in { |
Evan Cheng | f02ca69 | 2007-12-22 02:26:46 +0000 | [diff] [blame] | 473 | def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops), |
| 474 | "call\t${dst:call}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 475 | def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 476 | "call\t{*}$dst", [(X86call GR32:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 477 | def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), |
Dan Gohman | b410617 | 2008-05-29 21:50:34 +0000 | [diff] [blame] | 478 | "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 479 | } |
| 480 | |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 481 | // Tail call stuff. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 482 | |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 483 | def TAILCALL : I<0, Pseudo, (outs), (ins), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 484 | "#TAILCALL", |
| 485 | []>; |
| 486 | |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 487 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 4fe3073 | 2008-03-19 16:39:45 +0000 | [diff] [blame] | 488 | def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 489 | "#TC_RETURN $dst $offset", |
| 490 | []>; |
| 491 | |
| 492 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 4fe3073 | 2008-03-19 16:39:45 +0000 | [diff] [blame] | 493 | def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 494 | "#TC_RETURN $dst $offset", |
| 495 | []>; |
| 496 | |
| 497 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | 30e62c0 | 2008-04-30 09:16:33 +0000 | [diff] [blame] | 498 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 499 | def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL", |
Evan Cheng | f10c17f | 2006-09-22 21:43:59 +0000 | [diff] [blame] | 500 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 501 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 502 | def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL", |
| 503 | []>; |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 504 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 505 | def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 506 | "jmp\t{*}$dst # TAILCALL", []>; |
Chris Lattner | 1e9448b | 2005-05-15 03:10:37 +0000 | [diff] [blame] | 507 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 508 | //===----------------------------------------------------------------------===// |
| 509 | // Miscellaneous Instructions... |
| 510 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 511 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 512 | def LEAVE : I<0xC9, RawFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 513 | (outs), (ins), "leave", []>; |
| 514 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 515 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
| 516 | let mayLoad = 1 in |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 517 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 518 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 519 | let mayStore = 1 in |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 520 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 521 | } |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 522 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 523 | let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 524 | def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 525 | let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 526 | def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 527 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 528 | let isTwoAddress = 1 in // GR32 = bswap GR32 |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 529 | def BSWAP32r : I<0xC8, AddRegFrm, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 530 | (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 531 | "bswap{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 532 | [(set GR32:$dst, (bswap GR32:$src))]>, TB; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 533 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 534 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 535 | // Bit scan instructions. |
| 536 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 537 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 538 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 539 | [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 540 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 541 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 542 | [(set GR16:$dst, (X86bsf (loadi16 addr:$src))), |
| 543 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 544 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 545 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 546 | [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 547 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 548 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 549 | [(set GR32:$dst, (X86bsf (loadi32 addr:$src))), |
| 550 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 551 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 552 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 553 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 554 | [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 555 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 556 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 557 | [(set GR16:$dst, (X86bsr (loadi16 addr:$src))), |
| 558 | (implicit EFLAGS)]>, TB; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 559 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 560 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 561 | [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 562 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 563 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 152804e | 2007-12-14 08:30:15 +0000 | [diff] [blame] | 564 | [(set GR32:$dst, (X86bsr (loadi32 addr:$src))), |
| 565 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 566 | } // Defs = [EFLAGS] |
| 567 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 568 | let neverHasSideEffects = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 569 | def LEA16r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 570 | (outs GR16:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 571 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize; |
Evan Cheng | e771ebd | 2008-03-27 01:41:09 +0000 | [diff] [blame] | 572 | let isReMaterializable = 1 in |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 573 | def LEA32r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 574 | (outs GR32:$dst), (ins lea32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 575 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 576 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 577 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 578 | let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 579 | def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 580 | [(X86rep_movs i8)]>, REP; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 581 | def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 582 | [(X86rep_movs i16)]>, REP, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 583 | def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 584 | [(X86rep_movs i32)]>, REP; |
| 585 | } |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 586 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 587 | let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 588 | def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 589 | [(X86rep_stos i8)]>, REP; |
| 590 | let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 591 | def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 592 | [(X86rep_stos i16)]>, REP, OpSize; |
| 593 | let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 594 | def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 595 | [(X86rep_stos i32)]>, REP; |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 596 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 597 | let Defs = [RAX, RDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 598 | def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 599 | TB; |
Chris Lattner | b89abef | 2004-02-14 04:45:37 +0000 | [diff] [blame] | 600 | |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 601 | let isBarrier = 1, hasCtrlDep = 1 in { |
Chris Lattner | da68d30 | 2008-01-15 21:58:22 +0000 | [diff] [blame] | 602 | def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; |
Anton Korobeynikov | 66fac79 | 2008-01-15 07:02:33 +0000 | [diff] [blame] | 603 | } |
| 604 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 605 | //===----------------------------------------------------------------------===// |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 606 | // Input/Output Instructions... |
| 607 | // |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 608 | let Defs = [AL], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 609 | def IN8rr : I<0xEC, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 610 | "in{b}\t{%dx, %al|%AL, %DX}", []>; |
| 611 | let Defs = [AX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 612 | def IN16rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 613 | "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize; |
| 614 | let Defs = [EAX], Uses = [DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 615 | def IN32rr : I<0xED, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 616 | "in{l}\t{%dx, %eax|%EAX, %DX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 617 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 618 | let Defs = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 619 | def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 620 | "in{b}\t{$port, %al|%AL, $port}", []>; |
| 621 | let Defs = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 622 | def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 623 | "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize; |
| 624 | let Defs = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 625 | def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 626 | "in{l}\t{$port, %eax|%EAX, $port}", []>; |
Chris Lattner | 440bbc2 | 2004-04-13 17:19:31 +0000 | [diff] [blame] | 627 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 628 | let Uses = [DX, AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 629 | def OUT8rr : I<0xEE, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 630 | "out{b}\t{%al, %dx|%DX, %AL}", []>; |
| 631 | let Uses = [DX, AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 632 | def OUT16rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 633 | "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize; |
| 634 | let Uses = [DX, EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 635 | def OUT32rr : I<0xEF, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 636 | "out{l}\t{%eax, %dx|%DX, %EAX}", []>; |
Chris Lattner | ffff708 | 2004-08-01 07:44:35 +0000 | [diff] [blame] | 637 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 638 | let Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 639 | def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 640 | "out{b}\t{%al, $port|$port, %AL}", []>; |
| 641 | let Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 642 | def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 643 | "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize; |
| 644 | let Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 645 | def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 646 | "out{l}\t{%eax, $port|$port, %EAX}", []>; |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 647 | |
| 648 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 649 | // Move Instructions... |
| 650 | // |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 651 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 652 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 653 | "mov{b}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 654 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 655 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 656 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 657 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 658 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 659 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 660 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 661 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 662 | [(set GR8:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 663 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 664 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 665 | [(set GR16:$dst, imm:$src)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 666 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 667 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 668 | [(set GR32:$dst, imm:$src)]>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 669 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 670 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 671 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 672 | [(store (i8 imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 673 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 674 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 675 | [(store (i16 imm:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 676 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 677 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 678 | [(store (i32 imm:$src), addr:$dst)]>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 679 | |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame^] | 680 | let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 681 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 682 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 683 | [(set GR8:$dst, (load addr:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 684 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 685 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 686 | [(set GR16:$dst, (load addr:$src))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 687 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 688 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 689 | [(set GR32:$dst, (load addr:$src))]>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 690 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 691 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 692 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 693 | "mov{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 694 | [(store GR8:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 695 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 696 | "mov{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 697 | [(store GR16:$src, addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 698 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 699 | "mov{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 700 | [(store GR32:$src, addr:$dst)]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 701 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 702 | //===----------------------------------------------------------------------===// |
| 703 | // Fixed-Register Multiplication and Division Instructions... |
| 704 | // |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 705 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 706 | // Extra precision multiplication |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 707 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 708 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 709 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 710 | // This probably ought to be moved to a def : Pat<> if the |
| 711 | // syntax can be accepted. |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 712 | [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8 |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 713 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 714 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 715 | OpSize; // AX,DX = AX*GR16 |
Chris Lattner | a731c9f | 2008-01-11 07:18:17 +0000 | [diff] [blame] | 716 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 717 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>; |
| 718 | // EAX,EDX = EAX*GR32 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 719 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 720 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 721 | "mul{b}\t$src", |
Evan Cheng | cf74a7c | 2006-01-15 10:05:20 +0000 | [diff] [blame] | 722 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 723 | // This probably ought to be moved to a def : Pat<> if the |
| 724 | // syntax can be accepted. |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 725 | [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 726 | let mayLoad = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 727 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 728 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 729 | "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 730 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 731 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 732 | "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 733 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 734 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 735 | let neverHasSideEffects = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 736 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 737 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>; |
| 738 | // AL,AH = AL*GR8 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 739 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 740 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 741 | OpSize; // AX,DX = AX*GR16 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 742 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 743 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>; |
| 744 | // EAX,EDX = EAX*GR32 |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 745 | let mayLoad = 1 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 746 | let Defs = [AL,AH,EFLAGS], Uses = [AL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 747 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 748 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 749 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 750 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 751 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16] |
| 752 | let Defs = [EAX,EDX], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 753 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 754 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 755 | } |
Dan Gohman | c99da13 | 2008-11-18 21:29:14 +0000 | [diff] [blame] | 756 | } // neverHasSideEffects |
Chris Lattner | 1e6a715 | 2005-04-06 04:19:22 +0000 | [diff] [blame] | 757 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 758 | // unsigned division/remainder |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 759 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 760 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 761 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 762 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 763 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 764 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 765 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 766 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 767 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 768 | let mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 769 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 770 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 771 | "div{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 772 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 773 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 774 | "div{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 775 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 776 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 777 | "div{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 778 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 779 | |
Chris Lattner | fc75271 | 2004-08-01 09:52:59 +0000 | [diff] [blame] | 780 | // Signed division/remainder. |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 781 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 782 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 783 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 784 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 785 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 786 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 787 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 788 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 789 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 790 | let mayLoad = 1, mayLoad = 1 in { |
Dale Johannesen | 2cb48ea | 2008-10-07 18:54:28 +0000 | [diff] [blame] | 791 | let Defs = [AL,AH,EFLAGS], Uses = [AX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 792 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 793 | "idiv{b}\t$src", []>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 794 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 795 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 796 | "idiv{w}\t$src", []>, OpSize; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 797 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 798 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 799 | "idiv{l}\t$src", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 800 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 801 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 802 | //===----------------------------------------------------------------------===// |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 803 | // Two address Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 804 | // |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 805 | let isTwoAddress = 1 in { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 806 | |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 807 | // Conditional moves |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 808 | let Uses = [EFLAGS] in { |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 809 | let isCommutable = 1 in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 810 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 811 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 812 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 813 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 814 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 815 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 816 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 817 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 818 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 819 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 820 | X86_COND_B, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 821 | TB; |
Alkis Evlogimenos | a3f6684 | 2004-03-12 17:59:56 +0000 | [diff] [blame] | 822 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 823 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 824 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 825 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 826 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 827 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 828 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 829 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 830 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 831 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 832 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 833 | X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 834 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 835 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 836 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 837 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 838 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 839 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 840 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 841 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 842 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 843 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 844 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 845 | X86_COND_E, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 846 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 847 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 848 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 849 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 850 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 851 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 852 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 853 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 854 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 855 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 856 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 857 | X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 858 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 859 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 860 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 861 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 862 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 863 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 864 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 865 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 866 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 867 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 868 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 869 | X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 870 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 871 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 872 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 873 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 874 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 875 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 876 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 877 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 878 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 879 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 880 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 881 | X86_COND_A, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 882 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 883 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 884 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 885 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 886 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 887 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 888 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 889 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 890 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 891 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 892 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 893 | X86_COND_L, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 894 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 895 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 896 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 897 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 898 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 899 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 900 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 901 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 902 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 903 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 904 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 905 | X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 906 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 907 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 908 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 909 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 910 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 911 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 912 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 913 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 914 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 915 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 916 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 917 | X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 918 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 919 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 920 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 921 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 922 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 923 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 924 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 925 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 926 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 927 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 928 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 929 | X86_COND_G, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 930 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 931 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 932 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 933 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 934 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 935 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 936 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 937 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 938 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 939 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 940 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 941 | X86_COND_S, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 942 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 943 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 944 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 945 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 946 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 947 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 948 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 949 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 950 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 951 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 952 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 953 | X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 954 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 955 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 956 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 957 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 958 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 959 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 960 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 961 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 962 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 963 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 964 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 965 | X86_COND_P, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 966 | TB; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 967 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 968 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 969 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 970 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 971 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 972 | TB, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 973 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 974 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 975 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 976 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 977 | X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 71fb9ad | 2006-01-26 00:29:36 +0000 | [diff] [blame] | 978 | TB; |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 979 | } // isCommutable = 1 |
| 980 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 981 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 982 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 983 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 984 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 985 | X86_COND_NP, EFLAGS))]>, |
| 986 | TB; |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 987 | |
| 988 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] |
| 989 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 990 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 991 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 992 | X86_COND_B, EFLAGS))]>, |
| 993 | TB, OpSize; |
| 994 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32] |
| 995 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 996 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 997 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 998 | X86_COND_B, EFLAGS))]>, |
| 999 | TB; |
| 1000 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] |
| 1001 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1002 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 1003 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1004 | X86_COND_AE, EFLAGS))]>, |
| 1005 | TB, OpSize; |
| 1006 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] |
| 1007 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1008 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 1009 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1010 | X86_COND_AE, EFLAGS))]>, |
| 1011 | TB; |
| 1012 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] |
| 1013 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1014 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 1015 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1016 | X86_COND_E, EFLAGS))]>, |
| 1017 | TB, OpSize; |
| 1018 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] |
| 1019 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1020 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 1021 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1022 | X86_COND_E, EFLAGS))]>, |
| 1023 | TB; |
| 1024 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] |
| 1025 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1026 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 1027 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1028 | X86_COND_NE, EFLAGS))]>, |
| 1029 | TB, OpSize; |
| 1030 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] |
| 1031 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1032 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 1033 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1034 | X86_COND_NE, EFLAGS))]>, |
| 1035 | TB; |
| 1036 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] |
| 1037 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1038 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 1039 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1040 | X86_COND_BE, EFLAGS))]>, |
| 1041 | TB, OpSize; |
| 1042 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] |
| 1043 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1044 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 1045 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1046 | X86_COND_BE, EFLAGS))]>, |
| 1047 | TB; |
| 1048 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] |
| 1049 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1050 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 1051 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1052 | X86_COND_A, EFLAGS))]>, |
| 1053 | TB, OpSize; |
| 1054 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] |
| 1055 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1056 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 1057 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1058 | X86_COND_A, EFLAGS))]>, |
| 1059 | TB; |
| 1060 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16] |
| 1061 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1062 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 1063 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1064 | X86_COND_L, EFLAGS))]>, |
| 1065 | TB, OpSize; |
| 1066 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32] |
| 1067 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1068 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 1069 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1070 | X86_COND_L, EFLAGS))]>, |
| 1071 | TB; |
| 1072 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] |
| 1073 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1074 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 1075 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1076 | X86_COND_GE, EFLAGS))]>, |
| 1077 | TB, OpSize; |
| 1078 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] |
| 1079 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1080 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 1081 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1082 | X86_COND_GE, EFLAGS))]>, |
| 1083 | TB; |
| 1084 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] |
| 1085 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1086 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 1087 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1088 | X86_COND_LE, EFLAGS))]>, |
| 1089 | TB, OpSize; |
| 1090 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] |
| 1091 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1092 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 1093 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1094 | X86_COND_LE, EFLAGS))]>, |
| 1095 | TB; |
| 1096 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] |
| 1097 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1098 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 1099 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1100 | X86_COND_G, EFLAGS))]>, |
| 1101 | TB, OpSize; |
| 1102 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] |
| 1103 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1104 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 1105 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1106 | X86_COND_G, EFLAGS))]>, |
| 1107 | TB; |
| 1108 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] |
| 1109 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1110 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 1111 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1112 | X86_COND_S, EFLAGS))]>, |
| 1113 | TB, OpSize; |
| 1114 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] |
| 1115 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1116 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 1117 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1118 | X86_COND_S, EFLAGS))]>, |
| 1119 | TB; |
| 1120 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] |
| 1121 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1122 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 1123 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1124 | X86_COND_NS, EFLAGS))]>, |
| 1125 | TB, OpSize; |
| 1126 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] |
| 1127 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1128 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 1129 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1130 | X86_COND_NS, EFLAGS))]>, |
| 1131 | TB; |
| 1132 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] |
| 1133 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1134 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 1135 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1136 | X86_COND_P, EFLAGS))]>, |
| 1137 | TB, OpSize; |
| 1138 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] |
| 1139 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
| 1140 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 1141 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), |
| 1142 | X86_COND_P, EFLAGS))]>, |
| 1143 | TB; |
| 1144 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] |
| 1145 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
| 1146 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
| 1147 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), |
| 1148 | X86_COND_NP, EFLAGS))]>, |
| 1149 | TB, OpSize; |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1150 | } // Uses = [EFLAGS] |
| 1151 | |
| 1152 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1153 | // unary instructions |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1154 | let CodeSize = 2 in { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1155 | let Defs = [EFLAGS] in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1156 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1157 | [(set GR8:$dst, (ineg GR8:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1158 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1159 | [(set GR16:$dst, (ineg GR16:$src))]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1160 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1161 | [(set GR32:$dst, (ineg GR32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1162 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1163 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1164 | [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1165 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1166 | [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1167 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1168 | [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>; |
| 1169 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1170 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1171 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1172 | |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1173 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1174 | [(set GR8:$dst, (not GR8:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1175 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1176 | [(set GR16:$dst, (not GR16:$src))]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1177 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1178 | [(set GR32:$dst, (not GR32:$src))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1179 | let isTwoAddress = 0 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1180 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1181 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1182 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1183 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1184 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1185 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1186 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1187 | } // CodeSize |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1188 | |
Evan Cheng | b51a059 | 2005-12-10 00:48:20 +0000 | [diff] [blame] | 1189 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1190 | let Defs = [EFLAGS] in { |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1191 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1192 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1193 | [(set GR8:$dst, (add GR8:$src, 1))]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1194 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1195 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1196 | [(set GR16:$dst, (add GR16:$src, 1))]>, |
| 1197 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1198 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1199 | [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1200 | } |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1201 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1202 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1203 | [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1204 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1205 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, |
| 1206 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1207 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1208 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>, |
| 1209 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1210 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1211 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1212 | let CodeSize = 2 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1213 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1214 | [(set GR8:$dst, (add GR8:$src, -1))]>; |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1215 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1216 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1217 | [(set GR16:$dst, (add GR16:$src, -1))]>, |
| 1218 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1219 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1220 | [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1221 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1222 | |
Evan Cheng | 1693e48 | 2006-07-19 00:27:29 +0000 | [diff] [blame] | 1223 | let isTwoAddress = 0, CodeSize = 2 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1224 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 1225 | [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1226 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1227 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, |
| 1228 | OpSize, Requires<[In32BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1229 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 1230 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>, |
| 1231 | Requires<[In32BitMode]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1232 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1233 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1234 | |
| 1235 | // Logical operators... |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1236 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1237 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1238 | def AND8rr : I<0x20, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1239 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1240 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1241 | [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1242 | def AND16rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1243 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1244 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1245 | [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1246 | def AND32rr : I<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1247 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1248 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1249 | [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1250 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1251 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1252 | def AND8rm : I<0x22, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1253 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1254 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1255 | [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1256 | def AND16rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1257 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1258 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1259 | [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1260 | def AND32rm : I<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1261 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1262 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1263 | [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1264 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1265 | def AND8ri : Ii8<0x80, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1266 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1267 | "and{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1268 | [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1269 | def AND16ri : Ii16<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1270 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1271 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1272 | [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1273 | def AND32ri : Ii32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1274 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1275 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1276 | [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1277 | def AND16ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1278 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1279 | "and{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1280 | [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 1281 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1282 | def AND32ri8 : Ii8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1283 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1284 | "and{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1285 | [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1286 | |
| 1287 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1288 | def AND8mr : I<0x20, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1289 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1290 | "and{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1291 | [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1292 | def AND16mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1293 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1294 | "and{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1295 | [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1296 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1297 | def AND32mr : I<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1298 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1299 | "and{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1300 | [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1301 | def AND8mi : Ii8<0x80, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1302 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1303 | "and{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1304 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1305 | def AND16mi : Ii16<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1306 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1307 | "and{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1308 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1309 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1310 | def AND32mi : Ii32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1311 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1312 | "and{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1313 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1314 | def AND16mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1315 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1316 | "and{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1317 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1318 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1319 | def AND32mi8 : Ii8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1320 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1321 | "and{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | e3703d4 | 2006-01-14 01:18:49 +0000 | [diff] [blame] | 1322 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1323 | } |
| 1324 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1325 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1326 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1327 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1328 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1329 | [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1330 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1331 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1332 | [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1333 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1334 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1335 | [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1336 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1337 | def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1338 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1339 | [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1340 | def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1341 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1342 | [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1343 | def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1344 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1345 | [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1346 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1347 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1348 | "or{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1349 | [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1350 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1351 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1352 | [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1353 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1354 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1355 | [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1356 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1357 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1358 | "or{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1359 | [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1360 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1361 | "or{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1362 | [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1363 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1364 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1365 | "or{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1366 | [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1367 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1368 | "or{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1369 | [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1370 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1371 | "or{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1372 | [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1373 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1374 | "or{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1375 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1376 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1377 | "or{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1378 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1379 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1380 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1381 | "or{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1382 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1383 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1384 | "or{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1385 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1386 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1387 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1388 | "or{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1389 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1390 | } // isTwoAddress = 0 |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1391 | |
| 1392 | |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1393 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1394 | def XOR8rr : I<0x30, MRMDestReg, |
| 1395 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
| 1396 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
| 1397 | [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>; |
| 1398 | def XOR16rr : I<0x31, MRMDestReg, |
| 1399 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
| 1400 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
| 1401 | [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize; |
| 1402 | def XOR32rr : I<0x31, MRMDestReg, |
| 1403 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
| 1404 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
| 1405 | [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 1406 | } // isCommutable = 1 |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1407 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1408 | def XOR8rm : I<0x32, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1409 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1410 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1411 | [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1412 | def XOR16rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1413 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1414 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1415 | [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, |
| 1416 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1417 | def XOR32rm : I<0x33, MRMSrcMem , |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1418 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1419 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1420 | [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1421 | |
Bill Wendling | 75cf88f | 2008-05-29 03:46:36 +0000 | [diff] [blame] | 1422 | def XOR8ri : Ii8<0x80, MRM6r, |
| 1423 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 1424 | "xor{b}\t{$src2, $dst|$dst, $src2}", |
| 1425 | [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>; |
| 1426 | def XOR16ri : Ii16<0x81, MRM6r, |
| 1427 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 1428 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
| 1429 | [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize; |
| 1430 | def XOR32ri : Ii32<0x81, MRM6r, |
| 1431 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 1432 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
| 1433 | [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; |
| 1434 | def XOR16ri8 : Ii8<0x83, MRM6r, |
| 1435 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 1436 | "xor{w}\t{$src2, $dst|$dst, $src2}", |
| 1437 | [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>, |
| 1438 | OpSize; |
| 1439 | def XOR32ri8 : Ii8<0x83, MRM6r, |
| 1440 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 1441 | "xor{l}\t{$src2, $dst|$dst, $src2}", |
| 1442 | [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1443 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1444 | let isTwoAddress = 0 in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1445 | def XOR8mr : I<0x30, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1446 | (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1447 | "xor{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1448 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1449 | def XOR16mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1450 | (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1451 | "xor{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1452 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1453 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1454 | def XOR32mr : I<0x31, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1455 | (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1456 | "xor{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1457 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1458 | def XOR8mi : Ii8<0x80, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1459 | (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1460 | "xor{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1461 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1462 | def XOR16mi : Ii16<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1463 | (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1464 | "xor{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1465 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>, |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1466 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1467 | def XOR32mi : Ii32<0x81, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1468 | (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1469 | "xor{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 1470 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1471 | def XOR16mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1472 | (outs), (ins i16mem:$dst, i16i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1473 | "xor{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1474 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>, |
| 1475 | OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1476 | def XOR32mi8 : Ii8<0x83, MRM6m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1477 | (outs), (ins i32mem:$dst, i32i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1478 | "xor{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 0ef3a77 | 2005-12-13 01:41:36 +0000 | [diff] [blame] | 1479 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1480 | } // isTwoAddress = 0 |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1481 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1482 | |
| 1483 | // Shift instructions |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1484 | let Defs = [EFLAGS] in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1485 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1486 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1487 | "shl{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1488 | [(set GR8:$dst, (shl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1489 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1490 | "shl{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1491 | [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1492 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1493 | "shl{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1494 | [(set GR32:$dst, (shl GR32:$src, CL))]>; |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1495 | } // Uses = [CL] |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1496 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1497 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1498 | "shl{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1499 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1500 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1501 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1502 | "shl{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1503 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1504 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1505 | "shl{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1506 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f9b3f37 | 2008-01-11 18:00:50 +0000 | [diff] [blame] | 1507 | // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is |
| 1508 | // cheaper. |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 1509 | } // isConvertibleToThreeAddress = 1 |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1510 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1511 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1512 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1513 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1514 | "shl{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1515 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1516 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1517 | "shl{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1518 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1519 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1520 | "shl{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1521 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1522 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1523 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1524 | "shl{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1525 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1526 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1527 | "shl{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1528 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1529 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1530 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1531 | "shl{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 763b029 | 2005-12-13 02:34:51 +0000 | [diff] [blame] | 1532 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1533 | |
| 1534 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1535 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1536 | "shl{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1537 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1538 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1539 | "shl{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1540 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1541 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1542 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1543 | "shl{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1544 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1545 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1546 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1547 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1548 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1549 | "shr{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1550 | [(set GR8:$dst, (srl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1551 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1552 | "shr{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1553 | [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1554 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1555 | "shr{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1556 | [(set GR32:$dst, (srl GR32:$src, CL))]>; |
| 1557 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1558 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1559 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1560 | "shr{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1561 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1562 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1563 | "shr{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1564 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1565 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1566 | "shr{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1567 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1568 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1569 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1570 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1571 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1572 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1573 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1574 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1575 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1576 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1577 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1578 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
| 1579 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1580 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1581 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1582 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1583 | "shr{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1584 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1585 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1586 | "shr{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1587 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1588 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1589 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1590 | "shr{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1591 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1592 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1593 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1594 | "shr{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1595 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1596 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1597 | "shr{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1598 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1599 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1600 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1601 | "shr{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1602 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1603 | |
| 1604 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1605 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1606 | "shr{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1607 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1608 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1609 | "shr{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1610 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1611 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1612 | "shr{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1613 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1614 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1615 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1616 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1617 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1618 | "sar{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1619 | [(set GR8:$dst, (sra GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1620 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1621 | "sar{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1622 | [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1623 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1624 | "sar{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1625 | [(set GR32:$dst, (sra GR32:$src, CL))]>; |
| 1626 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1627 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1628 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1629 | "sar{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1630 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1631 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1632 | "sar{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1633 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
Chris Lattner | 3d36a9f | 2005-12-05 02:40:25 +0000 | [diff] [blame] | 1634 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1635 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1636 | "sar{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1637 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1638 | |
| 1639 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1640 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1641 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1642 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1643 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1644 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1645 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1646 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1647 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1648 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
| 1649 | |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1650 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1651 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1652 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1653 | "sar{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1654 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1655 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1656 | "sar{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1657 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1658 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1659 | "sar{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1660 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1661 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1662 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1663 | "sar{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1664 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1665 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1666 | "sar{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1667 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1668 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1669 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1670 | "sar{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 85dd889 | 2005-12-13 07:24:22 +0000 | [diff] [blame] | 1671 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1672 | |
| 1673 | // Shift by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1674 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1675 | "sar{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1676 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1677 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1678 | "sar{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1679 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1680 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1681 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1682 | "sar{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1683 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | f29ed09 | 2004-08-11 05:07:25 +0000 | [diff] [blame] | 1684 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1685 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1686 | // Rotate instructions |
| 1687 | // FIXME: provide shorter instructions when imm8 == 1 |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1688 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1689 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1690 | "rol{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1691 | [(set GR8:$dst, (rotl GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1692 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1693 | "rol{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1694 | [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1695 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1696 | "rol{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1697 | [(set GR32:$dst, (rotl GR32:$src, CL))]>; |
| 1698 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1699 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1700 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1701 | "rol{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1702 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1703 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1704 | "rol{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1705 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1706 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1707 | "rol{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1708 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1709 | |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1710 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1711 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1712 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1713 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1714 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1715 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1716 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1717 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1718 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1719 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
| 1720 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1721 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1722 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1723 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1724 | "rol{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1725 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1726 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1727 | "rol{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1728 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1729 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1730 | "rol{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1731 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1732 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1733 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1734 | "rol{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1735 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1736 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1737 | "rol{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1738 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1739 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1740 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1741 | "rol{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1742 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1743 | |
| 1744 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1745 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1746 | "rol{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1747 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1748 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1749 | "rol{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1750 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1751 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1752 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1753 | "rol{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1754 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1755 | } |
| 1756 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1757 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1758 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1759 | "ror{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1760 | [(set GR8:$dst, (rotr GR8:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1761 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1762 | "ror{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1763 | [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1764 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1765 | "ror{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1766 | [(set GR32:$dst, (rotr GR32:$src, CL))]>; |
| 1767 | } |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1768 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1769 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1770 | "ror{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1771 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1772 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1773 | "ror{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1774 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1775 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1776 | "ror{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1777 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1778 | |
| 1779 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1780 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1781 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1782 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1783 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1784 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1785 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1786 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1787 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1788 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
| 1789 | |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1790 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1791 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1792 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1793 | "ror{b}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1794 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1795 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1796 | "ror{w}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1797 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1798 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1799 | "ror{l}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1800 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; |
| 1801 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1802 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1803 | "ror{b}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1804 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1805 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1806 | "ror{w}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1807 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 1808 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1809 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1810 | "ror{l}\t{$src, $dst|$dst, $src}", |
Evan Cheng | eb422a7 | 2006-01-11 23:20:05 +0000 | [diff] [blame] | 1811 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1812 | |
| 1813 | // Rotate by 1 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1814 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1815 | "ror{b}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1816 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1817 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1818 | "ror{w}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1819 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 1820 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1821 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1822 | "ror{l}\t$dst", |
Evan Cheng | 09c5457 | 2006-06-29 00:36:51 +0000 | [diff] [blame] | 1823 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 40ff633 | 2005-01-19 07:50:03 +0000 | [diff] [blame] | 1824 | } |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | // Double shift instructions (generalizations of rotate) |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1829 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1830 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1831 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1832 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1833 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1834 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1835 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1836 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1837 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1838 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1839 | TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1840 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1841 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1842 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1843 | TB, OpSize; |
| 1844 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1845 | |
| 1846 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1847 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1848 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1849 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1850 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1851 | (i8 imm:$src3)))]>, |
| 1852 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1853 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1854 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1855 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1856 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1857 | (i8 imm:$src3)))]>, |
| 1858 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1859 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1860 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1861 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1862 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1863 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1864 | TB, OpSize; |
| 1865 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1866 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1867 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1868 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1869 | (i8 imm:$src3)))]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1870 | TB, OpSize; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 1871 | } |
Chris Lattner | 0e967d4 | 2004-08-01 08:13:11 +0000 | [diff] [blame] | 1872 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1873 | let isTwoAddress = 0 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1874 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1875 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1876 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1877 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1878 | addr:$dst)]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1879 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1880 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1881 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1882 | addr:$dst)]>, TB; |
| 1883 | } |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1884 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1885 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1886 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1887 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1888 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1889 | TB; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 1890 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1891 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1892 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1893 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1894 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 1895 | TB; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1896 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1897 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1898 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1899 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1900 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1901 | addr:$dst)]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1902 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1903 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1904 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1905 | addr:$dst)]>, TB, OpSize; |
| 1906 | } |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1907 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1908 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1909 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1910 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1911 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1912 | TB, OpSize; |
| 1913 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1914 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1915 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 1916 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 1917 | (i8 imm:$src3)), addr:$dst)]>, |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 1918 | TB, OpSize; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1919 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1920 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1921 | |
| 1922 | |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1923 | // Arithmetic. |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1924 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1925 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1926 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), |
| 1927 | (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1928 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1929 | [(set GR8:$dst, (add GR8:$src1, GR8:$src2)), |
| 1930 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1931 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1932 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), |
| 1933 | (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1934 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1935 | [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), |
| 1936 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1937 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), |
| 1938 | (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1939 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1940 | [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), |
| 1941 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1942 | } // end isConvertibleToThreeAddress |
| 1943 | } // end isCommutable |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1944 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), |
| 1945 | (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1946 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1947 | [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))), |
| 1948 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1949 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), |
| 1950 | (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1951 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1952 | [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))), |
| 1953 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1954 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), |
| 1955 | (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1956 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1957 | [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), |
| 1958 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1959 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1960 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1961 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1962 | [(set GR8:$dst, (add GR8:$src1, imm:$src2)), |
| 1963 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 1964 | |
| 1965 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1966 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), |
| 1967 | (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1968 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1969 | [(set GR16:$dst, (add GR16:$src1, imm:$src2)), |
| 1970 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1971 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), |
| 1972 | (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1973 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1974 | [(set GR32:$dst, (add GR32:$src1, imm:$src2)), |
| 1975 | (implicit EFLAGS)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1976 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), |
| 1977 | (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1978 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1979 | [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)), |
| 1980 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 1981 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), |
| 1982 | (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1983 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1984 | [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)), |
| 1985 | (implicit EFLAGS)]>; |
Evan Cheng | 09e3c80 | 2006-05-19 18:40:54 +0000 | [diff] [blame] | 1986 | } |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 1987 | |
| 1988 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1989 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1990 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1991 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst), |
| 1992 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1993 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1994 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 1995 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst), |
| 1996 | (implicit EFLAGS)]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 1997 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1998 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1999 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2000 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst), |
| 2001 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2002 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2003 | "add{b}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2004 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst), |
| 2005 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2006 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2007 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2008 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst), |
| 2009 | (implicit EFLAGS)]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2010 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2011 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2012 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2013 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst), |
| 2014 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2015 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2016 | "add{w}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2017 | [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst), |
| 2018 | (implicit EFLAGS)]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2019 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2020 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2021 | "add{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2022 | [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst), |
| 2023 | (implicit EFLAGS)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2024 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2025 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2026 | let Uses = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2027 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2028 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2029 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2030 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2031 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2032 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2033 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2034 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2035 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2036 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2037 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2038 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2039 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2040 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2041 | |
| 2042 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2043 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2044 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2045 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2046 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2047 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | e3b3c00 | 2008-12-01 23:44:08 +0000 | [diff] [blame] | 2048 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2049 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2050 | "adc{l}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2051 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2052 | } |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2053 | } // Uses = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2054 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2055 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2056 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2057 | [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2058 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2059 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2060 | [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2061 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2062 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2063 | [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2064 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2065 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2066 | [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2067 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2068 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2069 | [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2070 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2071 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2072 | [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2073 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2074 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2075 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2076 | [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2077 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2078 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2079 | [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2080 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2081 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2082 | [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2083 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2084 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2085 | [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2086 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2087 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2088 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2089 | [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2090 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2091 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2092 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2093 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2094 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2095 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2096 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2097 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2098 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2099 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2100 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2101 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2102 | "sub{b}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 2103 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2104 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2105 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 2106 | [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2107 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2108 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2109 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | c937ffa | 2005-12-13 02:40:18 +0000 | [diff] [blame] | 2110 | [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2111 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2112 | "sub{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2113 | [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>, |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2114 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2115 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2116 | "sub{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2117 | [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2118 | } |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2119 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2120 | let Uses = [EFLAGS] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2121 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2122 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2123 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; |
Chris Lattner | d93d3b0 | 2004-10-06 04:01:02 +0000 | [diff] [blame] | 2124 | |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2125 | let isTwoAddress = 0 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2126 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2127 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2128 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2129 | def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2130 | "sbb{b}\t{$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2131 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2132 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2133 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Nate Begeman | 551bf3f | 2006-02-17 05:43:56 +0000 | [diff] [blame] | 2134 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2135 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2136 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2137 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; |
Chris Lattner | 57a0230 | 2004-08-11 04:31:00 +0000 | [diff] [blame] | 2138 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2139 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2140 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2141 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2142 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2143 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2144 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2145 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2146 | "sbb{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2147 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 2148 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2149 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2150 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2151 | let Defs = [EFLAGS] in { |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2152 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2153 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2154 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2155 | [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2156 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2157 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2158 | [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB; |
Chris Lattner | 10197ff | 2005-01-03 01:27:59 +0000 | [diff] [blame] | 2159 | } |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2160 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2161 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2162 | [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2163 | TB, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2164 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2165 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2166 | [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2167 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2168 | } // end Two Address instructions |
| 2169 | |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2170 | // Suprisingly enough, these are not two address instructions! |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2171 | let Defs = [EFLAGS] in { |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2172 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2173 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2174 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2175 | [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize; |
| 2176 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2177 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2178 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2179 | [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>; |
| 2180 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2181 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2182 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2183 | [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2184 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2185 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2186 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2187 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2188 | [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>; |
Chris Lattner | f5d3a83 | 2004-08-11 05:31:07 +0000 | [diff] [blame] | 2189 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2190 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2191 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2192 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2193 | [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>, |
Evan Cheng | f281e02 | 2005-12-12 23:47:46 +0000 | [diff] [blame] | 2194 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2195 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2196 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2197 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2198 | [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>; |
| 2199 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2200 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2201 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2202 | [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, |
Evan Cheng | 9b6b642 | 2005-12-13 00:14:11 +0000 | [diff] [blame] | 2203 | OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2204 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2205 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2206 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2207 | [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2208 | } // Defs = [EFLAGS] |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2209 | |
| 2210 | //===----------------------------------------------------------------------===// |
| 2211 | // Test instructions are just like AND, except they don't generate a result. |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2212 | // |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2213 | let Defs = [EFLAGS] in { |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2214 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2215 | def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2216 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2217 | [(X86cmp (and_su GR8:$src1, GR8:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2218 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2219 | def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2220 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2221 | [(X86cmp (and_su GR16:$src1, GR16:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2222 | (implicit EFLAGS)]>, |
| 2223 | OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2224 | def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2225 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2226 | [(X86cmp (and_su GR32:$src1, GR32:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2227 | (implicit EFLAGS)]>; |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2228 | } |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2229 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2230 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2231 | "test{b}\t{$src2, $src1|$src1, $src2}", |
| 2232 | [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0), |
| 2233 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2234 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2235 | "test{w}\t{$src2, $src1|$src1, $src2}", |
| 2236 | [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0), |
| 2237 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2238 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2239 | "test{l}\t{$src2, $src1|$src1, $src2}", |
| 2240 | [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0), |
| 2241 | (implicit EFLAGS)]>; |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2242 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2243 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2244 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2245 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2246 | [(X86cmp (and_su GR8:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2247 | (implicit EFLAGS)]>; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2248 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2249 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2250 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2251 | [(X86cmp (and_su GR16:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2252 | (implicit EFLAGS)]>, OpSize; |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2253 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2254 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2255 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 2256 | [(X86cmp (and_su GR32:$src1, imm:$src2), 0), |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2257 | (implicit EFLAGS)]>; |
Evan Cheng | 734503b | 2006-09-11 02:19:56 +0000 | [diff] [blame] | 2258 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2259 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2260 | (outs), (ins i8mem:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2261 | "test{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2262 | [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0), |
| 2263 | (implicit EFLAGS)]>; |
| 2264 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2265 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2266 | "test{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2267 | [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0), |
| 2268 | (implicit EFLAGS)]>, OpSize; |
| 2269 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2270 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2271 | "test{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2272 | [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2273 | (implicit EFLAGS)]>; |
| 2274 | } // Defs = [EFLAGS] |
| 2275 | |
| 2276 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2277 | // Condition code ops, incl. set if equal/not equal/... |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2278 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2279 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2280 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2281 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 2282 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2283 | let Uses = [EFLAGS] in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2284 | def SETEr : I<0x94, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2285 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2286 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2287 | [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2288 | TB; // GR8 = == |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2289 | def SETEm : I<0x94, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2290 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2291 | "sete\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2292 | [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2293 | TB; // [mem8] = == |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2294 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2295 | def SETNEr : I<0x95, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2296 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2297 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2298 | [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2299 | TB; // GR8 = != |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2300 | def SETNEm : I<0x95, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2301 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2302 | "setne\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2303 | [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2304 | TB; // [mem8] = != |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2305 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2306 | def SETLr : I<0x9C, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2307 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2308 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2309 | [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2310 | TB; // GR8 = < signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2311 | def SETLm : I<0x9C, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2312 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2313 | "setl\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2314 | [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2315 | TB; // [mem8] = < signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2316 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2317 | def SETGEr : I<0x9D, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2318 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2319 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2320 | [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2321 | TB; // GR8 = >= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2322 | def SETGEm : I<0x9D, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2323 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2324 | "setge\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2325 | [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2326 | TB; // [mem8] = >= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2327 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2328 | def SETLEr : I<0x9E, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2329 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2330 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2331 | [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2332 | TB; // GR8 = <= signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2333 | def SETLEm : I<0x9E, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2334 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2335 | "setle\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2336 | [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2337 | TB; // [mem8] = <= signed |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2338 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2339 | def SETGr : I<0x9F, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2340 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2341 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2342 | [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2343 | TB; // GR8 = > signed |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2344 | def SETGm : I<0x9F, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2345 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2346 | "setg\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2347 | [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2348 | TB; // [mem8] = > signed |
| 2349 | |
| 2350 | def SETBr : I<0x92, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2351 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2352 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2353 | [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2354 | TB; // GR8 = < unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2355 | def SETBm : I<0x92, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2356 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2357 | "setb\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2358 | [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2359 | TB; // [mem8] = < unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2360 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2361 | def SETAEr : I<0x93, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2362 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2363 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2364 | [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2365 | TB; // GR8 = >= unsign |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2366 | def SETAEm : I<0x93, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2367 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2368 | "setae\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2369 | [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2370 | TB; // [mem8] = >= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2371 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2372 | def SETBEr : I<0x96, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2373 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2374 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2375 | [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2376 | TB; // GR8 = <= unsign |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2377 | def SETBEm : I<0x96, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2378 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2379 | "setbe\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2380 | [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2381 | TB; // [mem8] = <= unsign |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2382 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2383 | def SETAr : I<0x97, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2384 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2385 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2386 | [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2387 | TB; // GR8 = > signed |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2388 | def SETAm : I<0x97, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2389 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2390 | "seta\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2391 | [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>, |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 2392 | TB; // [mem8] = > signed |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2393 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2394 | def SETSr : I<0x98, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2395 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2396 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2397 | [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2398 | TB; // GR8 = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2399 | def SETSm : I<0x98, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2400 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2401 | "sets\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2402 | [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2403 | TB; // [mem8] = <sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2404 | def SETNSr : I<0x99, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2405 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2406 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2407 | [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2408 | TB; // GR8 = !<sign bit> |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2409 | def SETNSm : I<0x99, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2410 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2411 | "setns\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2412 | [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2413 | TB; // [mem8] = !<sign bit> |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2414 | |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2415 | def SETPr : I<0x9A, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2416 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2417 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2418 | [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2419 | TB; // GR8 = parity |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2420 | def SETPm : I<0x9A, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2421 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2422 | "setp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2423 | [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2424 | TB; // [mem8] = parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2425 | def SETNPr : I<0x9B, MRM0r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2426 | (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2427 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2428 | [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>, |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2429 | TB; // GR8 = not parity |
Chris Lattner | cc65bee | 2005-01-02 02:35:46 +0000 | [diff] [blame] | 2430 | def SETNPm : I<0x9B, MRM0m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2431 | (outs), (ins i8mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2432 | "setnp\t$dst", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2433 | [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>, |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 2434 | TB; // [mem8] = not parity |
Bill Wendling | 9f24874 | 2008-12-02 00:07:05 +0000 | [diff] [blame] | 2435 | |
| 2436 | def SETOr : I<0x90, MRM0r, |
| 2437 | (outs GR8 :$dst), (ins), |
| 2438 | "seto\t$dst", |
| 2439 | [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>, |
| 2440 | TB; // GR8 = overflow |
| 2441 | def SETOm : I<0x90, MRM0m, |
| 2442 | (outs), (ins i8mem:$dst), |
| 2443 | "seto\t$dst", |
| 2444 | [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>, |
| 2445 | TB; // [mem8] = overflow |
| 2446 | def SETNOr : I<0x91, MRM0r, |
| 2447 | (outs GR8 :$dst), (ins), |
| 2448 | "setno\t$dst", |
| 2449 | [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>, |
| 2450 | TB; // GR8 = not overflow |
| 2451 | def SETNOm : I<0x91, MRM0m, |
| 2452 | (outs), (ins i8mem:$dst), |
| 2453 | "setno\t$dst", |
| 2454 | [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>, |
| 2455 | TB; // [mem8] = not overflow |
| 2456 | |
| 2457 | def SETCr : I<0x92, MRM0r, |
| 2458 | (outs GR8 :$dst), (ins), |
| 2459 | "setc\t$dst", |
| 2460 | [(set GR8:$dst, (X86setcc X86_COND_C, EFLAGS))]>, |
| 2461 | TB; // GR8 = carry |
| 2462 | def SETCm : I<0x92, MRM0m, |
| 2463 | (outs), (ins i8mem:$dst), |
| 2464 | "setc\t$dst", |
| 2465 | [(store (X86setcc X86_COND_C, EFLAGS), addr:$dst)]>, |
| 2466 | TB; // [mem8] = carry |
| 2467 | def SETNCr : I<0x93, MRM0r, |
| 2468 | (outs GR8 :$dst), (ins), |
| 2469 | "setnc\t$dst", |
| 2470 | [(set GR8:$dst, (X86setcc X86_COND_NC, EFLAGS))]>, |
| 2471 | TB; // GR8 = not carry |
| 2472 | def SETNCm : I<0x93, MRM0m, |
| 2473 | (outs), (ins i8mem:$dst), |
| 2474 | "setnc\t$dst", |
| 2475 | [(store (X86setcc X86_COND_NC, EFLAGS), addr:$dst)]>, |
| 2476 | TB; // [mem8] = not carry |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2477 | } // Uses = [EFLAGS] |
| 2478 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2479 | |
| 2480 | // Integer comparisons |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 2481 | let Defs = [EFLAGS] in { |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2482 | def CMP8rr : I<0x38, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2483 | (outs), (ins GR8 :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2484 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2485 | [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2486 | def CMP16rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2487 | (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2488 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2489 | [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2490 | def CMP32rr : I<0x39, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2491 | (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2492 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2493 | [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2494 | def CMP8mr : I<0x38, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2495 | (outs), (ins i8mem :$src1, GR8 :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2496 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2497 | [(X86cmp (loadi8 addr:$src1), GR8:$src2), |
| 2498 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2499 | def CMP16mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2500 | (outs), (ins i16mem:$src1, GR16:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2501 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2502 | [(X86cmp (loadi16 addr:$src1), GR16:$src2), |
| 2503 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2504 | def CMP32mr : I<0x39, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2505 | (outs), (ins i32mem:$src1, GR32:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2506 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2507 | [(X86cmp (loadi32 addr:$src1), GR32:$src2), |
| 2508 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2509 | def CMP8rm : I<0x3A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2510 | (outs), (ins GR8 :$src1, i8mem :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2511 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2512 | [(X86cmp GR8:$src1, (loadi8 addr:$src2)), |
| 2513 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2514 | def CMP16rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2515 | (outs), (ins GR16:$src1, i16mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2516 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2517 | [(X86cmp GR16:$src1, (loadi16 addr:$src2)), |
| 2518 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2519 | def CMP32rm : I<0x3B, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2520 | (outs), (ins GR32:$src1, i32mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2521 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2522 | [(X86cmp GR32:$src1, (loadi32 addr:$src2)), |
| 2523 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2524 | def CMP8ri : Ii8<0x80, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2525 | (outs), (ins GR8:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2526 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2527 | [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2528 | def CMP16ri : Ii16<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2529 | (outs), (ins GR16:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2530 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2531 | [(X86cmp GR16:$src1, imm:$src2), |
| 2532 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2533 | def CMP32ri : Ii32<0x81, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2534 | (outs), (ins GR32:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2535 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2536 | [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2537 | def CMP8mi : Ii8 <0x80, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2538 | (outs), (ins i8mem :$src1, i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2539 | "cmp{b}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2540 | [(X86cmp (loadi8 addr:$src1), imm:$src2), |
| 2541 | (implicit EFLAGS)]>; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2542 | def CMP16mi : Ii16<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2543 | (outs), (ins i16mem:$src1, i16imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2544 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2545 | [(X86cmp (loadi16 addr:$src1), imm:$src2), |
| 2546 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 3a173df | 2004-10-03 20:35:00 +0000 | [diff] [blame] | 2547 | def CMP32mi : Ii32<0x81, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2548 | (outs), (ins i32mem:$src1, i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2549 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2550 | [(X86cmp (loadi32 addr:$src1), imm:$src2), |
| 2551 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2552 | def CMP16ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2553 | (outs), (ins GR16:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2554 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2555 | [(X86cmp GR16:$src1, i16immSExt8:$src2), |
| 2556 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2557 | def CMP16mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2558 | (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2559 | "cmp{w}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2560 | [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2), |
| 2561 | (implicit EFLAGS)]>, OpSize; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2562 | def CMP32mi8 : Ii8<0x83, MRM7m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2563 | (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2564 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2565 | [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2), |
| 2566 | (implicit EFLAGS)]>; |
Chris Lattner | 29b4dd0 | 2006-03-23 16:13:50 +0000 | [diff] [blame] | 2567 | def CMP32ri8 : Ii8<0x83, MRM7r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2568 | (outs), (ins GR32:$src1, i32i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2569 | "cmp{l}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2570 | [(X86cmp GR32:$src1, i32immSExt8:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 2571 | (implicit EFLAGS)]>; |
| 2572 | } // Defs = [EFLAGS] |
| 2573 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 2574 | // Sign/Zero extenders |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2575 | // Use movsbl intead of movsbw; we don't care about the high 16 bits |
| 2576 | // of the register here. This has a smaller encoding and avoids a |
| 2577 | // partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2578 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2579 | "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2580 | [(set GR16:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2581 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2582 | "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2583 | [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2584 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2585 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2586 | [(set GR32:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2587 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2588 | "movs{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2589 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2590 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2591 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2592 | [(set GR32:$dst, (sext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2593 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2594 | "movs{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2595 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; |
Alkis Evlogimenos | a7be982 | 2004-02-17 09:14:23 +0000 | [diff] [blame] | 2596 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2597 | // Use movzbl intead of movzbw; we don't care about the high 16 bits |
| 2598 | // of the register here. This has a smaller encoding and avoids a |
| 2599 | // partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2600 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2601 | "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2602 | [(set GR16:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2603 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2604 | "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
| 2605 | [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2606 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2607 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2608 | [(set GR32:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2609 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2610 | "movz{bl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2611 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2612 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2613 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2614 | [(set GR32:$dst, (zext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2615 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2616 | "movz{wl|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2617 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 2618 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2619 | let neverHasSideEffects = 1 in { |
| 2620 | let Defs = [AX], Uses = [AL] in |
| 2621 | def CBW : I<0x98, RawFrm, (outs), (ins), |
| 2622 | "{cbtw|cbw}", []>, OpSize; // AX = signext(AL) |
| 2623 | let Defs = [EAX], Uses = [AX] in |
| 2624 | def CWDE : I<0x98, RawFrm, (outs), (ins), |
| 2625 | "{cwtl|cwde}", []>; // EAX = signext(AX) |
Evan Cheng | f91c101 | 2006-05-31 22:05:11 +0000 | [diff] [blame] | 2626 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2627 | let Defs = [AX,DX], Uses = [AX] in |
| 2628 | def CWD : I<0x99, RawFrm, (outs), (ins), |
| 2629 | "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX) |
| 2630 | let Defs = [EAX,EDX], Uses = [EAX] in |
| 2631 | def CDQ : I<0x99, RawFrm, (outs), (ins), |
| 2632 | "{cltd|cdq}", []>; // EDX:EAX = signext(EAX) |
| 2633 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2634 | |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2635 | //===----------------------------------------------------------------------===// |
| 2636 | // Alias Instructions |
| 2637 | //===----------------------------------------------------------------------===// |
| 2638 | |
| 2639 | // Alias instructions that map movr0 to xor. |
| 2640 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
Bill Wendling | bd0879d | 2008-05-29 01:02:09 +0000 | [diff] [blame] | 2641 | let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2642 | def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2643 | "xor{b}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2644 | [(set GR8:$dst, 0)]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2645 | // Use xorl instead of xorw since we don't care about the high 16 bits, |
| 2646 | // it's smaller, and it avoids a partial-register update. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2647 | def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins), |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 2648 | "xor{l}\t${dst:subreg32}, ${dst:subreg32}", |
| 2649 | [(set GR16:$dst, 0)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2650 | def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2651 | "xor{l}\t$dst, $dst", |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2652 | [(set GR32:$dst, 0)]>; |
Dan Gohman | 1ab7989 | 2007-09-07 21:32:51 +0000 | [diff] [blame] | 2653 | } |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 2654 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2655 | // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only |
| 2656 | // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX). |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2657 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2658 | def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2659 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2660 | def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2661 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2662 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2663 | def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2664 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2665 | def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2666 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2667 | } // neverHasSideEffects |
| 2668 | |
Dan Gohman | 15511cf | 2008-12-03 18:15:48 +0000 | [diff] [blame^] | 2669 | let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2670 | def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2671 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2672 | def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2673 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 2674 | } |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2675 | let mayStore = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2676 | def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2677 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2678 | def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2679 | "mov{l}\t{$src, $dst|$dst, $src}", []>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 2680 | } |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 2681 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2682 | //===----------------------------------------------------------------------===// |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 2683 | // Thread Local Storage Instructions |
| 2684 | // |
| 2685 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 2686 | let Uses = [EBX] in |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 2687 | def TLS_addr32 : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym), |
| 2688 | "leal\t${sym:mem}(,%ebx,1), $dst", |
| 2689 | [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 2690 | |
Lauro Ramos Venancio | 7d2cc2b | 2007-04-22 22:50:52 +0000 | [diff] [blame] | 2691 | let AddedComplexity = 10 in |
Anton Korobeynikov | 6625eff | 2008-05-04 21:36:32 +0000 | [diff] [blame] | 2692 | def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2693 | "movl\t%gs:($src), $dst", |
Lauro Ramos Venancio | ede1d78 | 2007-04-23 01:28:10 +0000 | [diff] [blame] | 2694 | [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>; |
| 2695 | |
| 2696 | let AddedComplexity = 15 in |
Nicolas Geoffray | b74f370 | 2008-10-25 15:22:06 +0000 | [diff] [blame] | 2697 | def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2698 | "movl\t%gs:${src:mem}, $dst", |
Lauro Ramos Venancio | ede1d78 | 2007-04-23 01:28:10 +0000 | [diff] [blame] | 2699 | [(set GR32:$dst, |
Nicolas Geoffray | b74f370 | 2008-10-25 15:22:06 +0000 | [diff] [blame] | 2700 | (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>, |
| 2701 | SegGS; |
Lauro Ramos Venancio | 7d2cc2b | 2007-04-22 22:50:52 +0000 | [diff] [blame] | 2702 | |
Nicolas Geoffray | b74f370 | 2008-10-25 15:22:06 +0000 | [diff] [blame] | 2703 | def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2704 | "movl\t%gs:0, $dst", |
Nicolas Geoffray | b74f370 | 2008-10-25 15:22:06 +0000 | [diff] [blame] | 2705 | [(set GR32:$dst, X86TLStp)]>, SegGS; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 2706 | |
| 2707 | //===----------------------------------------------------------------------===// |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2708 | // DWARF Pseudo Instructions |
| 2709 | // |
| 2710 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2711 | def DWARF_LOC : I<0, Pseudo, (outs), |
| 2712 | (ins i32imm:$line, i32imm:$col, i32imm:$file), |
Dan Gohman | 6b5766e | 2007-09-24 19:25:06 +0000 | [diff] [blame] | 2713 | ".loc\t${file:debug} ${line:debug} ${col:debug}", |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2714 | [(dwarf_loc (i32 imm:$line), (i32 imm:$col), |
| 2715 | (i32 imm:$file))]>; |
| 2716 | |
Evan Cheng | 3c992d2 | 2006-03-07 02:02:57 +0000 | [diff] [blame] | 2717 | //===----------------------------------------------------------------------===// |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 2718 | // EH Pseudo Instructions |
| 2719 | // |
| 2720 | let isTerminator = 1, isReturn = 1, isBarrier = 1, |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 2721 | hasCtrlDep = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 2722 | def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 2723 | "ret\t#eh_return, addr: $addr", |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 2724 | [(X86ehret GR32:$addr)]>; |
| 2725 | |
| 2726 | } |
| 2727 | |
| 2728 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 2729 | // Atomic support |
| 2730 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2731 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2732 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 2733 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 2734 | let Constraints = "$val = $dst" in { |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 2735 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
| 2736 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
| 2737 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; |
| 2738 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
| 2739 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
| 2740 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, |
| 2741 | OpSize; |
| 2742 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), |
| 2743 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
| 2744 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; |
| 2745 | } |
| 2746 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2747 | // Atomic compare and swap. |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 2748 | let Defs = [EAX, EFLAGS], Uses = [EAX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2749 | def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2750 | "lock\n\tcmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 2751 | [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2752 | } |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 2753 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { |
Anton Korobeynikov | f88a6fa | 2008-07-22 16:22:48 +0000 | [diff] [blame] | 2754 | def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2755 | "lock\n\tcmpxchg8b\t$ptr", |
Andrew Lenharth | d19189e | 2008-03-05 01:15:49 +0000 | [diff] [blame] | 2756 | [(X86cas8 addr:$ptr)]>, TB, LOCK; |
| 2757 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 2758 | |
| 2759 | let Defs = [AX, EFLAGS], Uses = [AX] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2760 | def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2761 | "lock\n\tcmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 2762 | [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2763 | } |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 2764 | let Defs = [AL, EFLAGS], Uses = [AL] in { |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2765 | def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2766 | "lock\n\tcmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", |
Evan Cheng | 32967d2 | 2008-03-04 03:20:06 +0000 | [diff] [blame] | 2767 | [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2768 | } |
| 2769 | |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2770 | // Atomic exchange and add |
| 2771 | let Constraints = "$val = $dst", Defs = [EFLAGS] in { |
| 2772 | def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2773 | "lock\n\txadd{l}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 2774 | [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2775 | TB, LOCK; |
| 2776 | def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2777 | "lock\n\txadd{w}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 2778 | [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2779 | TB, OpSize, LOCK; |
| 2780 | def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2781 | "lock\n\txadd{b}\t{$val, $ptr|$ptr, $val}", |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 2782 | [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>, |
Evan Cheng | 7e03280 | 2008-04-18 20:55:36 +0000 | [diff] [blame] | 2783 | TB, LOCK; |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 2784 | } |
| 2785 | |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 2786 | // Atomic exchange, and, or, xor |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2787 | let Constraints = "$val = $dst", Defs = [EFLAGS], |
| 2788 | usesCustomDAGSchedInserter = 1 in { |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2789 | def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2790 | "#ATOMAND32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2791 | [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2792 | def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2793 | "#ATOMOR32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2794 | [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2795 | def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2796 | "#ATOMXOR32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2797 | [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>; |
Andrew Lenharth | 507a58a | 2008-06-14 05:48:15 +0000 | [diff] [blame] | 2798 | def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 2887310 | 2008-06-25 08:15:39 +0000 | [diff] [blame] | 2799 | "#ATOMNAND32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2800 | [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2801 | def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2802 | "#ATOMMIN32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2803 | [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2804 | def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2805 | "#ATOMMAX32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2806 | [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2807 | def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2808 | "#ATOMUMIN32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2809 | [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>; |
Dan Gohman | 9499b71 | 2008-05-12 20:22:45 +0000 | [diff] [blame] | 2810 | def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2811 | "#ATOMUMAX32 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2812 | [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2813 | |
| 2814 | def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2815 | "#ATOMAND16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2816 | [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2817 | def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2818 | "#ATOMOR16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2819 | [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2820 | def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2821 | "#ATOMXOR16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2822 | [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2823 | def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2824 | "#ATOMNAND16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2825 | [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2826 | def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), |
| 2827 | "#ATOMMIN16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2828 | [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2829 | def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2830 | "#ATOMMAX16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2831 | [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2832 | def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2833 | "#ATOMUMIN16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2834 | [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2835 | def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val), |
| 2836 | "#ATOMUMAX16 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2837 | [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2838 | |
| 2839 | def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
| 2840 | "#ATOMAND8 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2841 | [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2842 | def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
| 2843 | "#ATOMOR8 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2844 | [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2845 | def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
| 2846 | "#ATOMXOR8 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2847 | [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>; |
Dale Johannesen | 140be2d | 2008-08-19 18:47:28 +0000 | [diff] [blame] | 2848 | def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), |
| 2849 | "#ATOMNAND8 PSUEDO!", |
Dale Johannesen | e00a8a2 | 2008-08-28 02:44:49 +0000 | [diff] [blame] | 2850 | [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>; |
Mon P Wang | 63307c3 | 2008-05-05 19:05:59 +0000 | [diff] [blame] | 2851 | } |
| 2852 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 2853 | let Constraints = "$val1 = $dst1, $val2 = $dst2", |
| 2854 | Defs = [EFLAGS, EAX, EBX, ECX, EDX], |
| 2855 | Uses = [EAX, EBX, ECX, EDX], |
Dale Johannesen | 1b54c7f | 2008-10-03 19:41:08 +0000 | [diff] [blame] | 2856 | mayLoad = 1, mayStore = 1, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 2857 | usesCustomDAGSchedInserter = 1 in { |
| 2858 | def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2859 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2860 | "#ATOMAND6432 PSUEDO!", []>; |
| 2861 | def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2862 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2863 | "#ATOMOR6432 PSUEDO!", []>; |
| 2864 | def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2865 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2866 | "#ATOMXOR6432 PSUEDO!", []>; |
| 2867 | def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2868 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2869 | "#ATOMNAND6432 PSUEDO!", []>; |
| 2870 | def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2871 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2872 | "#ATOMADD6432 PSUEDO!", []>; |
| 2873 | def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2874 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2875 | "#ATOMSUB6432 PSUEDO!", []>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 2876 | def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), |
| 2877 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |
| 2878 | "#ATOMSWAP6432 PSUEDO!", []>; |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 2879 | } |
| 2880 | |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 2881 | //===----------------------------------------------------------------------===// |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2882 | // Non-Instruction Patterns |
| 2883 | //===----------------------------------------------------------------------===// |
| 2884 | |
Bill Wendling | 056292f | 2008-09-16 21:48:12 +0000 | [diff] [blame] | 2885 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2886 | def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; |
Nate Begeman | 37efe67 | 2006-04-22 18:53:45 +0000 | [diff] [blame] | 2887 | def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; |
Nate Begeman | 6795ebb | 2008-04-12 00:47:57 +0000 | [diff] [blame] | 2888 | def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2889 | def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; |
| 2890 | def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; |
| 2891 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2892 | def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), |
| 2893 | (ADD32ri GR32:$src1, tconstpool:$src2)>; |
| 2894 | def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), |
| 2895 | (ADD32ri GR32:$src1, tjumptable:$src2)>; |
| 2896 | def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), |
| 2897 | (ADD32ri GR32:$src1, tglobaladdr:$src2)>; |
| 2898 | def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), |
| 2899 | (ADD32ri GR32:$src1, texternalsym:$src2)>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2900 | |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 2901 | def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2902 | (MOV32mi addr:$dst, tglobaladdr:$src)>; |
Evan Cheng | fc8feb1 | 2006-05-19 07:30:36 +0000 | [diff] [blame] | 2903 | def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 2904 | (MOV32mi addr:$dst, texternalsym:$src)>; |
| 2905 | |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2906 | // Calls |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 2907 | // tailcall stuff |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2908 | def : Pat<(X86tailcall GR32:$dst), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 2909 | (TAILCALL)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 2910 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2911 | def : Pat<(X86tailcall (i32 tglobaladdr:$dst)), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 2912 | (TAILCALL)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2913 | def : Pat<(X86tailcall (i32 texternalsym:$dst)), |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 2914 | (TAILCALL)>; |
| 2915 | |
| 2916 | def : Pat<(X86tcret GR32:$dst, imm:$off), |
| 2917 | (TCRETURNri GR32:$dst, imm:$off)>; |
| 2918 | |
| 2919 | def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), |
| 2920 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
| 2921 | |
| 2922 | def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), |
| 2923 | (TCRETURNdi texternalsym:$dst, imm:$off)>; |
Evan Cheng | fea89c1 | 2006-04-27 08:40:39 +0000 | [diff] [blame] | 2924 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2925 | def : Pat<(X86call (i32 tglobaladdr:$dst)), |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2926 | (CALLpcrel32 tglobaladdr:$dst)>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2927 | def : Pat<(X86call (i32 texternalsym:$dst)), |
Evan Cheng | 8700e14 | 2006-01-11 06:09:51 +0000 | [diff] [blame] | 2928 | (CALLpcrel32 texternalsym:$dst)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2929 | |
| 2930 | // X86 specific add which produces a flag. |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2931 | def : Pat<(addc GR32:$src1, GR32:$src2), |
| 2932 | (ADD32rr GR32:$src1, GR32:$src2)>; |
| 2933 | def : Pat<(addc GR32:$src1, (load addr:$src2)), |
| 2934 | (ADD32rm GR32:$src1, addr:$src2)>; |
| 2935 | def : Pat<(addc GR32:$src1, imm:$src2), |
| 2936 | (ADD32ri GR32:$src1, imm:$src2)>; |
| 2937 | def : Pat<(addc GR32:$src1, i32immSExt8:$src2), |
| 2938 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2939 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 2940 | def : Pat<(subc GR32:$src1, GR32:$src2), |
| 2941 | (SUB32rr GR32:$src1, GR32:$src2)>; |
| 2942 | def : Pat<(subc GR32:$src1, (load addr:$src2)), |
| 2943 | (SUB32rm GR32:$src1, addr:$src2)>; |
| 2944 | def : Pat<(subc GR32:$src1, imm:$src2), |
| 2945 | (SUB32ri GR32:$src1, imm:$src2)>; |
| 2946 | def : Pat<(subc GR32:$src1, i32immSExt8:$src2), |
| 2947 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2948 | |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2949 | // Comparisons. |
| 2950 | |
| 2951 | // TEST R,R is smaller than CMP R,0 |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2952 | def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2953 | (TEST8rr GR8:$src1, GR8:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2954 | def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2955 | (TEST16rr GR16:$src1, GR16:$src1)>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 2956 | def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)), |
Chris Lattner | ffc0b26 | 2006-09-07 20:33:45 +0000 | [diff] [blame] | 2957 | (TEST32rr GR32:$src1, GR32:$src1)>; |
| 2958 | |
Duncan Sands | f9c98e6 | 2008-01-23 20:39:46 +0000 | [diff] [blame] | 2959 | // zextload bool -> zextload byte |
Evan Cheng | e5d9343 | 2006-01-17 07:02:46 +0000 | [diff] [blame] | 2960 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2961 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; |
| 2962 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 2963 | |
| 2964 | // extload bool -> extload byte |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 2965 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; |
Bill Wendling | 449416d | 2008-08-22 20:51:05 +0000 | [diff] [blame] | 2966 | def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>, |
| 2967 | Requires<[In32BitMode]>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 2968 | def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; |
Bill Wendling | 449416d | 2008-08-22 20:51:05 +0000 | [diff] [blame] | 2969 | def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>, |
| 2970 | Requires<[In32BitMode]>; |
Evan Cheng | 4713724 | 2006-05-05 08:23:07 +0000 | [diff] [blame] | 2971 | def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; |
| 2972 | def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2973 | |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 2974 | // anyext |
Bill Wendling | 449416d | 2008-08-22 20:51:05 +0000 | [diff] [blame] | 2975 | def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>, |
| 2976 | Requires<[In32BitMode]>; |
| 2977 | def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>, |
| 2978 | Requires<[In32BitMode]>; |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 2979 | def : Pat<(i32 (anyext GR16:$src)), |
| 2980 | (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 2981 | |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 2982 | // (and (i32 load), 255) -> (zextload i8) |
Evan Cheng | d47e0b6 | 2008-09-29 17:26:18 +0000 | [diff] [blame] | 2983 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))), |
| 2984 | (MOVZX32rm8 addr:$src)>; |
| 2985 | def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))), |
| 2986 | (MOVZX32rm16 addr:$src)>; |
Evan Cheng | 1314b00 | 2007-12-13 00:43:27 +0000 | [diff] [blame] | 2987 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 2988 | //===----------------------------------------------------------------------===// |
| 2989 | // Some peepholes |
| 2990 | //===----------------------------------------------------------------------===// |
| 2991 | |
Dan Gohman | 63f9720 | 2008-10-17 01:33:43 +0000 | [diff] [blame] | 2992 | // Odd encoding trick: -128 fits into an 8-bit immediate field while |
| 2993 | // +128 doesn't, so in this special case use a sub instead of an add. |
| 2994 | def : Pat<(add GR16:$src1, 128), |
| 2995 | (SUB16ri8 GR16:$src1, -128)>; |
| 2996 | def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), |
| 2997 | (SUB16mi8 addr:$dst, -128)>; |
| 2998 | def : Pat<(add GR32:$src1, 128), |
| 2999 | (SUB32ri8 GR32:$src1, -128)>; |
| 3000 | def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), |
| 3001 | (SUB32mi8 addr:$dst, -128)>; |
| 3002 | |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3003 | // r & (2^16-1) ==> movz |
| 3004 | def : Pat<(and GR32:$src1, 0xffff), |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3005 | (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>; |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3006 | // r & (2^8-1) ==> movz |
| 3007 | def : Pat<(and GR32:$src1, 0xff), |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3008 | (MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1), |
| 3009 | x86_subreg_8bit)))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3010 | Requires<[In32BitMode]>; |
| 3011 | // r & (2^8-1) ==> movz |
| 3012 | def : Pat<(and GR16:$src1, 0xff), |
Dan Gohman | 0bfa1bf | 2008-08-20 21:27:32 +0000 | [diff] [blame] | 3013 | (MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1), |
| 3014 | x86_subreg_8bit)))>, |
| 3015 | Requires<[In32BitMode]>; |
| 3016 | |
| 3017 | // sext_inreg patterns |
| 3018 | def : Pat<(sext_inreg GR32:$src, i16), |
| 3019 | (MOVSX32rr16 (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)))>; |
| 3020 | def : Pat<(sext_inreg GR32:$src, i8), |
| 3021 | (MOVSX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), |
| 3022 | x86_subreg_8bit)))>, |
| 3023 | Requires<[In32BitMode]>; |
| 3024 | def : Pat<(sext_inreg GR16:$src, i8), |
| 3025 | (MOVSX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), |
| 3026 | x86_subreg_8bit)))>, |
| 3027 | Requires<[In32BitMode]>; |
| 3028 | |
| 3029 | // trunc patterns |
| 3030 | def : Pat<(i16 (trunc GR32:$src)), |
| 3031 | (i16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>; |
| 3032 | def : Pat<(i8 (trunc GR32:$src)), |
| 3033 | (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>, |
| 3034 | Requires<[In32BitMode]>; |
| 3035 | def : Pat<(i8 (trunc GR16:$src)), |
| 3036 | (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src), x86_subreg_8bit))>, |
Dan Gohman | 8a1510d | 2008-08-06 18:27:21 +0000 | [diff] [blame] | 3037 | Requires<[In32BitMode]>; |
Dan Gohman | 11ba3b1 | 2008-07-30 18:09:17 +0000 | [diff] [blame] | 3038 | |
Evan Cheng | cfa260b | 2006-01-06 02:31:59 +0000 | [diff] [blame] | 3039 | // (shl x, 1) ==> (add x, x) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3040 | def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; |
| 3041 | def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; |
| 3042 | def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3043 | |
Evan Cheng | eb9f892 | 2008-08-30 02:03:58 +0000 | [diff] [blame] | 3044 | // (shl x (and y, 31)) ==> (shl x, y) |
| 3045 | def : Pat<(shl GR8:$src1, (and CL:$amt, 31)), |
| 3046 | (SHL8rCL GR8:$src1)>; |
| 3047 | def : Pat<(shl GR16:$src1, (and CL:$amt, 31)), |
| 3048 | (SHL16rCL GR16:$src1)>; |
| 3049 | def : Pat<(shl GR32:$src1, (and CL:$amt, 31)), |
| 3050 | (SHL32rCL GR32:$src1)>; |
| 3051 | def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3052 | (SHL8mCL addr:$dst)>; |
| 3053 | def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3054 | (SHL16mCL addr:$dst)>; |
| 3055 | def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3056 | (SHL32mCL addr:$dst)>; |
| 3057 | |
| 3058 | def : Pat<(srl GR8:$src1, (and CL:$amt, 31)), |
| 3059 | (SHR8rCL GR8:$src1)>; |
| 3060 | def : Pat<(srl GR16:$src1, (and CL:$amt, 31)), |
| 3061 | (SHR16rCL GR16:$src1)>; |
| 3062 | def : Pat<(srl GR32:$src1, (and CL:$amt, 31)), |
| 3063 | (SHR32rCL GR32:$src1)>; |
| 3064 | def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3065 | (SHR8mCL addr:$dst)>; |
| 3066 | def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3067 | (SHR16mCL addr:$dst)>; |
| 3068 | def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3069 | (SHR32mCL addr:$dst)>; |
| 3070 | |
| 3071 | def : Pat<(sra GR8:$src1, (and CL:$amt, 31)), |
| 3072 | (SAR8rCL GR8:$src1)>; |
| 3073 | def : Pat<(sra GR16:$src1, (and CL:$amt, 31)), |
| 3074 | (SAR16rCL GR16:$src1)>; |
| 3075 | def : Pat<(sra GR32:$src1, (and CL:$amt, 31)), |
| 3076 | (SAR32rCL GR32:$src1)>; |
| 3077 | def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3078 | (SAR8mCL addr:$dst)>; |
| 3079 | def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3080 | (SAR16mCL addr:$dst)>; |
| 3081 | def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst), |
| 3082 | (SAR32mCL addr:$dst)>; |
| 3083 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3084 | // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3085 | def : Pat<(or (srl GR32:$src1, CL:$amt), |
| 3086 | (shl GR32:$src2, (sub 32, CL:$amt))), |
| 3087 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 68b951a | 2006-01-19 01:56:29 +0000 | [diff] [blame] | 3088 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3089 | def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3090 | (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 3091 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3092 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3093 | def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 3094 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3095 | (SHRD32rrCL GR32:$src1, GR32:$src2)>; |
| 3096 | |
| 3097 | def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 3098 | (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3099 | addr:$dst), |
| 3100 | (SHRD32mrCL addr:$dst, GR32:$src2)>; |
| 3101 | |
| 3102 | def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 3103 | (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 3104 | |
| 3105 | def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1), |
| 3106 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3107 | (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 3108 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3109 | // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3110 | def : Pat<(or (shl GR32:$src1, CL:$amt), |
| 3111 | (srl GR32:$src2, (sub 32, CL:$amt))), |
| 3112 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3113 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3114 | def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3115 | (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), |
| 3116 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3117 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3118 | def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))), |
| 3119 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3120 | (SHLD32rrCL GR32:$src1, GR32:$src2)>; |
| 3121 | |
| 3122 | def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))), |
| 3123 | (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))), |
| 3124 | addr:$dst), |
| 3125 | (SHLD32mrCL addr:$dst, GR32:$src2)>; |
| 3126 | |
| 3127 | def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)), |
| 3128 | (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>; |
| 3129 | |
| 3130 | def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1), |
| 3131 | GR32:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3132 | (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>; |
| 3133 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3134 | // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3135 | def : Pat<(or (srl GR16:$src1, CL:$amt), |
| 3136 | (shl GR16:$src2, (sub 16, CL:$amt))), |
| 3137 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3138 | |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3139 | def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3140 | (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 3141 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3142 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3143 | def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))), |
| 3144 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3145 | (SHRD16rrCL GR16:$src1, GR16:$src2)>; |
| 3146 | |
| 3147 | def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 3148 | (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3149 | addr:$dst), |
| 3150 | (SHRD16mrCL addr:$dst, GR16:$src2)>; |
| 3151 | |
| 3152 | def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 3153 | (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 3154 | |
| 3155 | def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1), |
| 3156 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3157 | (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 3158 | |
Evan Cheng | 956044c | 2006-01-19 23:26:24 +0000 | [diff] [blame] | 3159 | // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3160 | def : Pat<(or (shl GR16:$src1, CL:$amt), |
| 3161 | (srl GR16:$src2, (sub 16, CL:$amt))), |
| 3162 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
Evan Cheng | 21d5443 | 2006-01-20 01:13:30 +0000 | [diff] [blame] | 3163 | |
| 3164 | def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 3165 | (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), |
| 3166 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3167 | |
Dan Gohman | 74feef2 | 2008-10-17 01:23:35 +0000 | [diff] [blame] | 3168 | def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))), |
| 3169 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3170 | (SHLD16rrCL GR16:$src1, GR16:$src2)>; |
| 3171 | |
| 3172 | def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))), |
| 3173 | (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))), |
| 3174 | addr:$dst), |
| 3175 | (SHLD16mrCL addr:$dst, GR16:$src2)>; |
| 3176 | |
| 3177 | def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)), |
| 3178 | (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>; |
| 3179 | |
| 3180 | def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1), |
| 3181 | GR16:$src2, (i8 imm:$amt2)), addr:$dst), |
| 3182 | (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>; |
| 3183 | |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3184 | //===----------------------------------------------------------------------===// |
| 3185 | // Floating Point Stack Support |
| 3186 | //===----------------------------------------------------------------------===// |
| 3187 | |
| 3188 | include "X86InstrFPStack.td" |
| 3189 | |
| 3190 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 3191 | // X86-64 Support |
| 3192 | //===----------------------------------------------------------------------===// |
| 3193 | |
Chris Lattner | 36fe6d2 | 2008-01-10 05:50:42 +0000 | [diff] [blame] | 3194 | include "X86Instr64bit.td" |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 3195 | |
| 3196 | //===----------------------------------------------------------------------===// |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 3197 | // XMM Floating point support (requires SSE / SSE2) |
| 3198 | //===----------------------------------------------------------------------===// |
| 3199 | |
| 3200 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 3201 | |
| 3202 | //===----------------------------------------------------------------------===// |
| 3203 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) |
| 3204 | //===----------------------------------------------------------------------===// |
| 3205 | |
| 3206 | include "X86InstrMMX.td" |