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Arnold Schwaighofer48abc5c2007-10-12 21:30:57 +00001//===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
John Criswell856ba762003-10-21 15:17:13 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
John Criswell856ba762003-10-21 15:17:13 +00007//
8//===----------------------------------------------------------------------===//
Chris Lattner1cca5e32003-08-03 21:54:21 +00009//
10// This file describes the X86 instruction set, defining the instructions, and
11// properties of the instructions which are needed for code generation, machine
12// code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
Evan Chengaed7c722005-12-17 01:24:02 +000016//===----------------------------------------------------------------------===//
17// X86 specific DAG Nodes.
18//
19
Evan Chenge3413162006-01-09 18:33:28 +000020def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
23
Evan Cheng71fb9ad2006-01-26 00:29:36 +000024def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
Evan Chengaed7c722005-12-17 01:24:02 +000025
Evan Chenge5f62042007-09-29 00:00:36 +000026def SDTX86Cmov : SDTypeProfile<1, 4,
Evan Cheng0488db92007-09-25 01:57:46 +000027 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
Evan Chengaed7c722005-12-17 01:24:02 +000029
Dan Gohman076aee32009-03-04 19:44:21 +000030// Unary and binary operator instructions that set EFLAGS as a side-effect.
31def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
32 [SDTCisInt<0>]>;
33def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
34 [SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>,
36 SDTCisInt<0>]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +000037
Evan Chenge5f62042007-09-29 00:00:36 +000038def SDTX86BrCond : SDTypeProfile<0, 3,
Evan Cheng0488db92007-09-25 01:57:46 +000039 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Evan Chengaed7c722005-12-17 01:24:02 +000041
Evan Chenge5f62042007-09-29 00:00:36 +000042def SDTX86SetCC : SDTypeProfile<1, 2,
Evan Cheng0488db92007-09-25 01:57:46 +000043 [SDTCisVT<0, i8>,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
Evan Chengd5781fc2005-12-21 20:21:51 +000045
Andrew Lenharth26ed8692008-03-01 21:52:34 +000046def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 SDTCisVT<2, i8>]>;
Andrew Lenharthd19189e2008-03-05 01:15:49 +000048def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
Andrew Lenharth26ed8692008-03-01 21:52:34 +000049
Dale Johannesen48c1bc22008-10-02 18:53:47 +000050def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
51 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
Chris Lattner447ff682008-03-11 03:23:40 +000052def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
Evan Cheng898101c2005-12-19 23:12:38 +000053
Bill Wendlingc69107c2007-11-13 09:19:02 +000054def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
55def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
56 SDTCisVT<1, i32> ]>;
Evan Chenge3413162006-01-09 18:33:28 +000057
Dan Gohmand35121a2008-05-29 19:57:41 +000058def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
Evan Chenge3413162006-01-09 18:33:28 +000059
Evan Cheng67f92a72006-01-11 22:15:48 +000060def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61
Evan Chenge3413162006-01-09 18:33:28 +000062def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
Evan Chengd90eb7f2006-01-05 00:27:02 +000063
Evan Cheng71fb8342006-02-25 10:02:21 +000064def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65
Rafael Espindola2ee3db32009-04-17 14:35:58 +000066def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +000067
Rafael Espindola094fad32009-04-08 21:14:34 +000068def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +000069
Anton Korobeynikov2365f512007-07-14 14:06:15 +000070def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +000072def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73
Evan Cheng18efe262007-12-14 02:13:44 +000074def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
75def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
Evan Chenge3413162006-01-09 18:33:28 +000076def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
77def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
Evan Chengb077b842005-12-21 02:39:21 +000078
Evan Chenge5f62042007-09-29 00:00:36 +000079def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
Evan Chengb077b842005-12-21 02:39:21 +000080
Dan Gohmanc7a37d42008-12-23 22:45:23 +000081def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82
Evan Chenge5f62042007-09-29 00:00:36 +000083def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
Evan Chenge3413162006-01-09 18:33:28 +000084def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
Evan Cheng0488db92007-09-25 01:57:46 +000085 [SDNPHasChain]>;
Evan Chenge5f62042007-09-29 00:00:36 +000086def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
Evan Chengb077b842005-12-21 02:39:21 +000087
Andrew Lenharth26ed8692008-03-01 21:52:34 +000088def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
89 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 SDNPMayLoad]>;
Andrew Lenharthd19189e2008-03-05 01:15:49 +000091def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
92 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 SDNPMayLoad]>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +000094def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
95 [SDNPHasChain, SDNPMayStore,
96 SDNPMayLoad, SDNPMemOperand]>;
97def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
98 [SDNPHasChain, SDNPMayStore,
99 SDNPMayLoad, SDNPMemOperand]>;
100def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
101 [SDNPHasChain, SDNPMayStore,
102 SDNPMayLoad, SDNPMemOperand]>;
103def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
Dale Johannesen880ae362008-10-03 22:25:52 +0000112def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
Evan Chenge3413162006-01-09 18:33:28 +0000115def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
116 [SDNPHasChain, SDNPOptInFlag]>;
Evan Chengb077b842005-12-21 02:39:21 +0000117
Evan Chenge3413162006-01-09 18:33:28 +0000118def X86callseq_start :
119 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
Evan Chengbb7b8442006-08-11 09:03:33 +0000120 [SDNPHasChain, SDNPOutFlag]>;
Evan Chenge3413162006-01-09 18:33:28 +0000121def X86callseq_end :
122 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000123 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Evan Chengb077b842005-12-21 02:39:21 +0000124
Evan Chenge3413162006-01-09 18:33:28 +0000125def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
126 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
Evan Chengaed7c722005-12-17 01:24:02 +0000127
Evan Chengfb914c42006-05-20 01:40:16 +0000128def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
Evan Chengfea89c12006-04-27 08:40:39 +0000129 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
130
Evan Cheng67f92a72006-01-11 22:15:48 +0000131def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000132 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
Evan Cheng67f92a72006-01-11 22:15:48 +0000133def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000134 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
135 SDNPMayLoad]>;
Evan Cheng67f92a72006-01-11 22:15:48 +0000136
Evan Chenge3413162006-01-09 18:33:28 +0000137def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
Chris Lattnerba7e7562008-01-10 07:59:24 +0000138 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
Evan Chengd90eb7f2006-01-05 00:27:02 +0000139
Evan Cheng0085a282006-11-30 21:55:46 +0000140def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
141def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
Evan Cheng71fb8342006-02-25 10:02:21 +0000142
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000143def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
Anton Korobeynikov6625eff2008-05-04 21:36:32 +0000144 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Rafael Espindola094fad32009-04-08 21:14:34 +0000145def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
146 SDT_X86SegmentBaseAddress, []>;
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000147
Anton Korobeynikov2365f512007-07-14 14:06:15 +0000148def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
149 [SDNPHasChain]>;
150
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000151def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
152 [SDNPHasChain, SDNPOptInFlag]>;
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +0000153
Dan Gohman076aee32009-03-04 19:44:21 +0000154def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
155def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
156def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
157def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
158def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
159def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +0000160
Evan Cheng73f24c92009-03-30 21:36:47 +0000161def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
162
Evan Chengaed7c722005-12-17 01:24:02 +0000163//===----------------------------------------------------------------------===//
164// X86 Operand Definitions.
165//
166
Chris Lattner66fa1dc2004-08-11 02:25:00 +0000167// *mem - Operand definitions for the funky X86 addressing mode operands.
168//
Evan Chengaf78ef52006-05-17 21:21:41 +0000169class X86MemOperand<string printMethod> : Operand<iPTR> {
Nate Begeman391c5d22005-11-30 18:54:35 +0000170 let PrintMethod = printMethod;
Rafael Espindola094fad32009-04-08 21:14:34 +0000171 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
Chris Lattner66fa1dc2004-08-11 02:25:00 +0000172}
Nate Begeman391c5d22005-11-30 18:54:35 +0000173
Chris Lattner45432512005-12-17 19:47:05 +0000174def i8mem : X86MemOperand<"printi8mem">;
175def i16mem : X86MemOperand<"printi16mem">;
176def i32mem : X86MemOperand<"printi32mem">;
177def i64mem : X86MemOperand<"printi64mem">;
Evan Cheng470a6ad2006-02-22 02:26:30 +0000178def i128mem : X86MemOperand<"printi128mem">;
Chris Lattner45432512005-12-17 19:47:05 +0000179def f32mem : X86MemOperand<"printf32mem">;
180def f64mem : X86MemOperand<"printf64mem">;
Dale Johannesen59a58732007-08-05 18:49:15 +0000181def f80mem : X86MemOperand<"printf80mem">;
Evan Cheng223547a2006-01-31 22:28:30 +0000182def f128mem : X86MemOperand<"printf128mem">;
Nate Begeman391c5d22005-11-30 18:54:35 +0000183
Dan Gohman21e3dfb2009-04-13 16:09:41 +0000184// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
185// plain GR64, so that it doesn't potentially require a REX prefix.
186def i8mem_NOREX : Operand<i64> {
187 let PrintMethod = "printi8mem";
188 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX, i32imm, i8imm);
189}
190
Evan Cheng25ab6902006-09-08 06:48:29 +0000191def lea32mem : Operand<i32> {
Rafael Espindola094fad32009-04-08 21:14:34 +0000192 let PrintMethod = "printlea32mem";
Evan Cheng25ab6902006-09-08 06:48:29 +0000193 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
194}
195
Nate Begeman16b04f32005-07-15 00:38:55 +0000196def SSECC : Operand<i8> {
197 let PrintMethod = "printSSECC";
198}
Chris Lattner66fa1dc2004-08-11 02:25:00 +0000199
Evan Cheng7ccced62006-02-18 00:15:05 +0000200def piclabel: Operand<i32> {
201 let PrintMethod = "printPICLabel";
202}
203
Chris Lattnerf124d5e2005-11-18 01:04:42 +0000204// A couple of more descriptive operand definitions.
205// 16-bits but only 8 bits are significant.
206def i16i8imm : Operand<i16>;
207// 32-bits but only 8 bits are significant.
208def i32i8imm : Operand<i32>;
209
Evan Chengd35b8c12005-12-04 08:19:43 +0000210// Branch targets have OtherVT type.
211def brtarget : Operand<OtherVT>;
212
Evan Chengaed7c722005-12-17 01:24:02 +0000213//===----------------------------------------------------------------------===//
214// X86 Complex Pattern Definitions.
215//
216
Evan Chengec693f72005-12-08 02:01:35 +0000217// Define X86 specific addressing mode.
Rafael Espindola094fad32009-04-08 21:14:34 +0000218def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
Evan Cheng25ab6902006-09-08 06:48:29 +0000219def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
Evan Chengaf9db752006-10-11 21:03:53 +0000220 [add, mul, shl, or, frameindex], []>;
Evan Chengec693f72005-12-08 02:01:35 +0000221
Evan Chengaed7c722005-12-17 01:24:02 +0000222//===----------------------------------------------------------------------===//
Evan Chengbbc8ddb2005-12-20 22:59:51 +0000223// X86 Instruction Predicate Definitions.
Evan Cheng28b514392006-12-05 19:50:18 +0000224def HasMMX : Predicate<"Subtarget->hasMMX()">;
225def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
226def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
227def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
Bill Wendlingbb1ee052007-04-10 22:10:25 +0000228def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
Nate Begeman63ec90a2008-02-03 07:18:54 +0000229def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
230def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
Dale Johannesenf1fc3a82007-09-23 14:52:20 +0000231def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
232def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
Evan Cheng28b514392006-12-05 19:50:18 +0000233def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
234def In64BitMode : Predicate<"Subtarget->is64Bit()">;
235def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
236def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
237def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
Evan Chengb7a75a52008-09-26 23:41:32 +0000238def OptForSpeed : Predicate<"!OptForSize">;
Evan Chengccb69762009-01-02 05:35:45 +0000239def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
Evan Chengbbc8ddb2005-12-20 22:59:51 +0000240
241//===----------------------------------------------------------------------===//
Evan Chengc64a1a92007-07-31 08:04:03 +0000242// X86 Instruction Format Definitions.
Evan Chengaed7c722005-12-17 01:24:02 +0000243//
244
Evan Chengc64a1a92007-07-31 08:04:03 +0000245include "X86InstrFormats.td"
Chris Lattner1cca5e32003-08-03 21:54:21 +0000246
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +0000247//===----------------------------------------------------------------------===//
Chris Lattnerf124d5e2005-11-18 01:04:42 +0000248// Pattern fragments...
249//
Evan Chengd9558e02006-01-06 00:43:03 +0000250
251// X86 specific condition code. These correspond to CondCode in
Nate Begeman9a225302007-05-06 04:00:55 +0000252// X86InstrInfo.h. They must be kept in synch.
Dan Gohman653456c2009-01-07 00:15:08 +0000253def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
254def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
255def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
256def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
257def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
258def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
259def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
260def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
261def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
262def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
Evan Chengd9558e02006-01-06 00:43:03 +0000263def X86_COND_NO : PatLeaf<(i8 10)>;
Dan Gohman653456c2009-01-07 00:15:08 +0000264def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
Evan Chengd9558e02006-01-06 00:43:03 +0000265def X86_COND_NS : PatLeaf<(i8 12)>;
Dan Gohman653456c2009-01-07 00:15:08 +0000266def X86_COND_O : PatLeaf<(i8 13)>;
267def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
268def X86_COND_S : PatLeaf<(i8 15)>;
Evan Chengd9558e02006-01-06 00:43:03 +0000269
Evan Cheng9b6b6422005-12-13 00:14:11 +0000270def i16immSExt8 : PatLeaf<(i16 imm), [{
271 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
Evan Chengb3558542005-12-13 00:01:09 +0000272 // sign extended field.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000273 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
Chris Lattnerf124d5e2005-11-18 01:04:42 +0000274}]>;
275
Evan Cheng9b6b6422005-12-13 00:14:11 +0000276def i32immSExt8 : PatLeaf<(i32 imm), [{
277 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
Evan Chengb3558542005-12-13 00:01:09 +0000278 // sign extended field.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000279 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
Evan Chengb3558542005-12-13 00:01:09 +0000280}]>;
281
Evan Cheng605c4152005-12-13 01:57:51 +0000282// Helper fragments for loads.
Evan Chengb6564432008-05-13 18:59:59 +0000283// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
284// known to be 32-bit aligned or better. Ditto for i8 to i16.
Dan Gohman33586292008-10-15 06:50:19 +0000285def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
Dan Gohman67ca6be2008-08-20 15:24:22 +0000286 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattnerc2406f22009-04-10 00:16:23 +0000287 if (const Value *Src = LD->getSrcValue())
288 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000289 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000290 return false;
Dan Gohman67ca6be2008-08-20 15:24:22 +0000291 ISD::LoadExtType ExtType = LD->getExtensionType();
292 if (ExtType == ISD::NON_EXTLOAD)
293 return true;
294 if (ExtType == ISD::EXTLOAD)
295 return LD->getAlignment() >= 2 && !LD->isVolatile();
Evan Chengfa7fd332008-05-13 00:54:02 +0000296 return false;
297}]>;
298
Dan Gohman33586292008-10-15 06:50:19 +0000299def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Evan Chengca57f782008-09-24 23:27:55 +0000300 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattnerc2406f22009-04-10 00:16:23 +0000301 if (const Value *Src = LD->getSrcValue())
302 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000303 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000304 return false;
Evan Chengca57f782008-09-24 23:27:55 +0000305 ISD::LoadExtType ExtType = LD->getExtensionType();
306 if (ExtType == ISD::EXTLOAD)
307 return LD->getAlignment() >= 2 && !LD->isVolatile();
308 return false;
309}]>;
310
Dan Gohman33586292008-10-15 06:50:19 +0000311def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Dan Gohman67ca6be2008-08-20 15:24:22 +0000312 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattnerc2406f22009-04-10 00:16:23 +0000313 if (const Value *Src = LD->getSrcValue())
314 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000315 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000316 return false;
Dan Gohman67ca6be2008-08-20 15:24:22 +0000317 ISD::LoadExtType ExtType = LD->getExtensionType();
318 if (ExtType == ISD::NON_EXTLOAD)
319 return true;
320 if (ExtType == ISD::EXTLOAD)
321 return LD->getAlignment() >= 4 && !LD->isVolatile();
Evan Chengfa7fd332008-05-13 00:54:02 +0000322 return false;
323}]>;
324
Dan Gohman33586292008-10-15 06:50:19 +0000325def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
Evan Chengd47e0b62008-09-29 17:26:18 +0000326 LoadSDNode *LD = cast<LoadSDNode>(N);
Chris Lattnerc2406f22009-04-10 00:16:23 +0000327 if (const Value *Src = LD->getSrcValue())
328 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000329 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000330 return false;
Evan Chengd47e0b62008-09-29 17:26:18 +0000331 if (LD->isVolatile())
332 return false;
Evan Chengd47e0b62008-09-29 17:26:18 +0000333 ISD::LoadExtType ExtType = LD->getExtensionType();
334 if (ExtType == ISD::NON_EXTLOAD)
335 return true;
336 if (ExtType == ISD::EXTLOAD)
337 return LD->getAlignment() >= 4;
338 return false;
339}]>;
340
Nate Begeman51a04372009-01-26 01:24:32 +0000341def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
Chris Lattnerc2406f22009-04-10 00:16:23 +0000342 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
343 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
344 return PT->getAddressSpace() == 256;
Nate Begeman51a04372009-01-26 01:24:32 +0000345 return false;
346}]>;
347
Chris Lattner1777d0c2009-05-05 18:52:19 +0000348def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
349 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
350 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
351 return PT->getAddressSpace() == 257;
352 return false;
353}]>;
354
Chris Lattnerc2406f22009-04-10 00:16:23 +0000355def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
356 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
357 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000358 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000359 return false;
360 return true;
361}]>;
362def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
363 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000365 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000366 return false;
367 return true;
368}]>;
Evan Cheng06a8aa12006-03-17 19:55:52 +0000369
Chris Lattnerc2406f22009-04-10 00:16:23 +0000370def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
371 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
372 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000373 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000374 return false;
375 return true;
376}]>;
377def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
378 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000380 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000381 return false;
382 return true;
383}]>;
384def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
385 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
386 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
Mon P Wanga7e01d72009-04-27 07:22:10 +0000387 if (PT->getAddressSpace() > 255)
Chris Lattnerc2406f22009-04-10 00:16:23 +0000388 return false;
389 return true;
390}]>;
Evan Cheng7a7e8372005-12-14 02:22:27 +0000391
Evan Cheng466685d2006-10-09 20:57:25 +0000392def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
393def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
394def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
Evan Cheng7a7e8372005-12-14 02:22:27 +0000395
Evan Cheng466685d2006-10-09 20:57:25 +0000396def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
397def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
398def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
399def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
400def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
401def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
Evan Cheng7a7e8372005-12-14 02:22:27 +0000402
Evan Cheng466685d2006-10-09 20:57:25 +0000403def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
404def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
405def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
406def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
407def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
408def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
Evan Cheng747a90d2006-02-21 02:24:38 +0000409
Chris Lattnerce2bcc82008-02-19 17:37:35 +0000410
411// An 'and' node with a single use.
412def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
Evan Cheng07b7ea12008-03-04 00:40:35 +0000413 return N->hasOneUse();
Chris Lattnerce2bcc82008-02-19 17:37:35 +0000414}]>;
Dan Gohman21e3dfb2009-04-13 16:09:41 +0000415// An 'srl' node with a single use.
416def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
417 return N->hasOneUse();
418}]>;
419// An 'trunc' node with a single use.
420def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
421 return N->hasOneUse();
422}]>;
Chris Lattnerce2bcc82008-02-19 17:37:35 +0000423
Dan Gohman74feef22008-10-17 01:23:35 +0000424// 'shld' and 'shrd' instruction patterns. Note that even though these have
425// the srl and shl in their patterns, the C++ code must still check for them,
426// because predicates are tested before children nodes are explored.
427
428def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
429 (or (srl node:$src1, node:$amt1),
430 (shl node:$src2, node:$amt2)), [{
431 assert(N->getOpcode() == ISD::OR);
432 return N->getOperand(0).getOpcode() == ISD::SRL &&
433 N->getOperand(1).getOpcode() == ISD::SHL &&
434 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
435 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
436 N->getOperand(0).getConstantOperandVal(1) ==
437 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
438}]>;
439
440def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
441 (or (shl node:$src1, node:$amt1),
442 (srl node:$src2, node:$amt2)), [{
443 assert(N->getOpcode() == ISD::OR);
444 return N->getOperand(0).getOpcode() == ISD::SHL &&
445 N->getOperand(1).getOpcode() == ISD::SRL &&
446 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
447 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
448 N->getOperand(0).getConstantOperandVal(1) ==
449 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
450}]>;
451
Chris Lattnerf124d5e2005-11-18 01:04:42 +0000452//===----------------------------------------------------------------------===//
Chris Lattner1cca5e32003-08-03 21:54:21 +0000453// Instruction list...
454//
455
Chris Lattnerf18c0742006-10-12 17:42:56 +0000456// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
457// a stack adjustment and the codegen must know that they may modify the stack
458// pointer before prolog-epilog rewriting occurs.
Chris Lattner447ff682008-03-11 03:23:40 +0000459// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
460// sub / add which can clobber EFLAGS.
Evan Cheng8decf6b2007-09-28 01:19:48 +0000461let Defs = [ESP, EFLAGS], Uses = [ESP] in {
Dan Gohman6d4b0522008-10-01 18:28:06 +0000462def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
463 "#ADJCALLSTACKDOWN",
Chris Lattnere563bbc2008-10-11 22:08:30 +0000464 [(X86callseq_start timm:$amt)]>,
Dan Gohman6d4b0522008-10-01 18:28:06 +0000465 Requires<[In32BitMode]>;
466def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
467 "#ADJCALLSTACKUP",
Chris Lattnere563bbc2008-10-11 22:08:30 +0000468 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
Dan Gohman6d4b0522008-10-01 18:28:06 +0000469 Requires<[In32BitMode]>;
Evan Cheng071a2792007-09-11 19:55:27 +0000470}
Evan Cheng4a460802006-01-11 00:33:36 +0000471
472// Nop
Chris Lattnerba7e7562008-01-10 07:59:24 +0000473let neverHasSideEffects = 1 in
474 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
Evan Cheng4a460802006-01-11 00:33:36 +0000475
Evan Cheng0475ab52008-01-05 00:41:47 +0000476// PIC base
Dan Gohman2662d552008-10-01 04:14:30 +0000477let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
Chris Lattnerba7e7562008-01-10 07:59:24 +0000478 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
Dan Gohman4d47b9b2009-04-27 15:13:28 +0000479 "call\t$label\n\t"
480 "pop{l}\t$reg", []>;
Evan Cheng8f7f7122006-05-05 05:40:20 +0000481
Chris Lattner1cca5e32003-08-03 21:54:21 +0000482//===----------------------------------------------------------------------===//
483// Control Flow Instructions...
484//
485
Chris Lattner1be48112005-05-13 17:56:48 +0000486// Return instructions.
Evan Cheng2b4ea792005-12-26 09:11:45 +0000487let isTerminator = 1, isReturn = 1, isBarrier = 1,
Chris Lattner447ff682008-03-11 03:23:40 +0000488 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
Dan Gohmane4c67cd2008-05-31 02:11:25 +0000489 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
Chris Lattner447ff682008-03-11 03:23:40 +0000490 "ret",
Dan Gohmane4c67cd2008-05-31 02:11:25 +0000491 [(X86retflag 0)]>;
Chris Lattner447ff682008-03-11 03:23:40 +0000492 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
493 "ret\t$amt",
Evan Chenge3413162006-01-09 18:33:28 +0000494 [(X86retflag imm:$amt)]>;
Evan Cheng171049d2005-12-23 22:14:32 +0000495}
Chris Lattner1cca5e32003-08-03 21:54:21 +0000496
497// All branches are RawFrm, Void, Branch, and Terminators
Evan Chengffbacca2007-07-21 00:34:19 +0000498let isBranch = 1, isTerminator = 1 in
Evan Cheng64d80e32007-07-19 01:14:50 +0000499 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
500 I<opcode, RawFrm, (outs), ins, asm, pattern>;
Chris Lattner1cca5e32003-08-03 21:54:21 +0000501
Evan Chengec3bc392006-09-07 19:03:48 +0000502let isBranch = 1, isBarrier = 1 in
Dan Gohmanb1576f52007-07-31 20:11:57 +0000503 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
Evan Cheng898101c2005-12-19 23:12:38 +0000504
Owen Anderson20ab2902007-11-12 07:39:39 +0000505// Indirect branches
506let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
Dan Gohmanb1576f52007-07-31 20:11:57 +0000507 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
Evan Cheng069287d2006-05-16 07:21:53 +0000508 [(brind GR32:$dst)]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000509 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
Evan Cheng25ab6902006-09-08 06:48:29 +0000510 [(brind (loadi32 addr:$dst))]>;
Nate Begeman37efe672006-04-22 18:53:45 +0000511}
512
513// Conditional branches
Evan Cheng0488db92007-09-25 01:57:46 +0000514let Uses = [EFLAGS] in {
Dan Gohmanb1576f52007-07-31 20:11:57 +0000515def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000516 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000517def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000518 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000519def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000520 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000521def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000522 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000523def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000524 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000525def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000526 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
Evan Cheng898101c2005-12-19 23:12:38 +0000527
Dan Gohmanb1576f52007-07-31 20:11:57 +0000528def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000529 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000530def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000531 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000532def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000533 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000534def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000535 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
Evan Cheng898101c2005-12-19 23:12:38 +0000536
Dan Gohmanb1576f52007-07-31 20:11:57 +0000537def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000538 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000539def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000540 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000541def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000542 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000543def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000544 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000545def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000546 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
Dan Gohmanb1576f52007-07-31 20:11:57 +0000547def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +0000548 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
Evan Cheng0488db92007-09-25 01:57:46 +0000549} // Uses = [EFLAGS]
Chris Lattner1cca5e32003-08-03 21:54:21 +0000550
551//===----------------------------------------------------------------------===//
552// Call Instructions...
553//
Evan Chengffbacca2007-07-21 00:34:19 +0000554let isCall = 1 in
Dan Gohman6d4b0522008-10-01 18:28:06 +0000555 // All calls clobber the non-callee saved registers. ESP is marked as
556 // a use to prevent stack-pointer assignments that appear immediately
557 // before calls from potentially appearing dead. Uses for argument
558 // registers are added manually.
Nate Begemanf63be7d2005-07-06 18:59:04 +0000559 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
Bill Wendling3f3a17d2007-04-25 21:31:48 +0000560 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
Evan Cheng109a5622008-10-17 21:02:22 +0000561 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
562 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
Dan Gohman2662d552008-10-01 04:14:30 +0000563 Uses = [ESP] in {
Evan Chengf02ca692007-12-22 02:26:46 +0000564 def CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
Evan Chenga0652002009-03-12 18:15:39 +0000565 "call\t${dst:call}", [(X86call imm:$dst)]>,
566 Requires<[In32BitMode]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000567 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000568 "call\t{*}$dst", [(X86call GR32:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000569 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
Dan Gohmanb4106172008-05-29 21:50:34 +0000570 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
Chris Lattner1cca5e32003-08-03 21:54:21 +0000571 }
572
Chris Lattner1e9448b2005-05-15 03:10:37 +0000573// Tail call stuff.
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000574
Chris Lattner447ff682008-03-11 03:23:40 +0000575def TAILCALL : I<0, Pseudo, (outs), (ins),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000576 "#TAILCALL",
577 []>;
578
Evan Chengffbacca2007-07-21 00:34:19 +0000579let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer4fe30732008-03-19 16:39:45 +0000580def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000581 "#TC_RETURN $dst $offset",
582 []>;
583
584let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer4fe30732008-03-19 16:39:45 +0000585def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000586 "#TC_RETURN $dst $offset",
587 []>;
588
589let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighofer30e62c02008-04-30 09:16:33 +0000590
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000591 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
Evan Chengf10c17f2006-09-22 21:43:59 +0000592 []>;
Evan Chengffbacca2007-07-21 00:34:19 +0000593let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000594 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
595 []>;
Evan Chengffbacca2007-07-21 00:34:19 +0000596let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
Evan Cheng64d80e32007-07-19 01:14:50 +0000597 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +0000598 "jmp\t{*}$dst # TAILCALL", []>;
Chris Lattner1e9448b2005-05-15 03:10:37 +0000599
Chris Lattner1cca5e32003-08-03 21:54:21 +0000600//===----------------------------------------------------------------------===//
601// Miscellaneous Instructions...
602//
Chris Lattnerba7e7562008-01-10 07:59:24 +0000603let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
Chris Lattner30bf2d82004-08-10 20:17:41 +0000604def LEAVE : I<0xC9, RawFrm,
Evan Cheng071a2792007-09-11 19:55:27 +0000605 (outs), (ins), "leave", []>;
606
Chris Lattnerba7e7562008-01-10 07:59:24 +0000607let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
608let mayLoad = 1 in
Evan Cheng2f245ba2007-09-26 01:29:06 +0000609def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
Chris Lattner1cca5e32003-08-03 21:54:21 +0000610
Chris Lattnerba7e7562008-01-10 07:59:24 +0000611let mayStore = 1 in
Evan Cheng2f245ba2007-09-26 01:29:06 +0000612def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
Evan Cheng071a2792007-09-11 19:55:27 +0000613}
Anton Korobeynikov57fc00d2007-04-17 09:20:00 +0000614
Chris Lattnerba7e7562008-01-10 07:59:24 +0000615let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
Evan Chengbf4f89d2007-09-26 21:28:00 +0000616def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
Chris Lattnerba7e7562008-01-10 07:59:24 +0000617let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
Evan Chengbf4f89d2007-09-26 21:28:00 +0000618def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
Evan Cheng2f245ba2007-09-26 01:29:06 +0000619
Evan Cheng069287d2006-05-16 07:21:53 +0000620let isTwoAddress = 1 in // GR32 = bswap GR32
Chris Lattner30bf2d82004-08-10 20:17:41 +0000621 def BSWAP32r : I<0xC8, AddRegFrm,
Evan Cheng64d80e32007-07-19 01:14:50 +0000622 (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000623 "bswap{l}\t$dst",
Evan Cheng069287d2006-05-16 07:21:53 +0000624 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
Chris Lattner1cca5e32003-08-03 21:54:21 +0000625
Chris Lattner1cca5e32003-08-03 21:54:21 +0000626
Evan Cheng18efe262007-12-14 02:13:44 +0000627// Bit scan instructions.
628let Defs = [EFLAGS] in {
Evan Chengfd9e4732007-12-14 18:49:43 +0000629def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000630 "bsf{w}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000631 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng18efe262007-12-14 02:13:44 +0000632def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000633 "bsf{w}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000634 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
635 (implicit EFLAGS)]>, TB;
Evan Chengfd9e4732007-12-14 18:49:43 +0000636def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000637 "bsf{l}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000638 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng18efe262007-12-14 02:13:44 +0000639def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000640 "bsf{l}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000641 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
642 (implicit EFLAGS)]>, TB;
Evan Cheng18efe262007-12-14 02:13:44 +0000643
Evan Chengfd9e4732007-12-14 18:49:43 +0000644def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000645 "bsr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000646 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng18efe262007-12-14 02:13:44 +0000647def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000648 "bsr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000649 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
650 (implicit EFLAGS)]>, TB;
Evan Chengfd9e4732007-12-14 18:49:43 +0000651def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000652 "bsr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000653 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
Evan Cheng18efe262007-12-14 02:13:44 +0000654def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohman1a8001e2007-12-14 15:10:00 +0000655 "bsr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng152804e2007-12-14 08:30:15 +0000656 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
657 (implicit EFLAGS)]>, TB;
Evan Cheng18efe262007-12-14 02:13:44 +0000658} // Defs = [EFLAGS]
659
Chris Lattnerba7e7562008-01-10 07:59:24 +0000660let neverHasSideEffects = 1 in
Chris Lattner3a173df2004-10-03 20:35:00 +0000661def LEA16r : I<0x8D, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +0000662 (outs GR16:$dst), (ins i32mem:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000663 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
Evan Chenge771ebd2008-03-27 01:41:09 +0000664let isReMaterializable = 1 in
Chris Lattner3a173df2004-10-03 20:35:00 +0000665def LEA32r : I<0x8D, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +0000666 (outs GR32:$dst), (ins lea32mem:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000667 "lea{l}\t{$src|$dst}, {$dst|$src}",
Evan Cheng25ab6902006-09-08 06:48:29 +0000668 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
Chris Lattner1cca5e32003-08-03 21:54:21 +0000669
Evan Cheng071a2792007-09-11 19:55:27 +0000670let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000671def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
Evan Cheng071a2792007-09-11 19:55:27 +0000672 [(X86rep_movs i8)]>, REP;
Evan Cheng64d80e32007-07-19 01:14:50 +0000673def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
Evan Cheng071a2792007-09-11 19:55:27 +0000674 [(X86rep_movs i16)]>, REP, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +0000675def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
Evan Cheng071a2792007-09-11 19:55:27 +0000676 [(X86rep_movs i32)]>, REP;
677}
Chris Lattner915e5e52004-02-12 17:53:22 +0000678
Evan Cheng071a2792007-09-11 19:55:27 +0000679let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000680def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
Evan Cheng071a2792007-09-11 19:55:27 +0000681 [(X86rep_stos i8)]>, REP;
682let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000683def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
Evan Cheng071a2792007-09-11 19:55:27 +0000684 [(X86rep_stos i16)]>, REP, OpSize;
685let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000686def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
Evan Cheng071a2792007-09-11 19:55:27 +0000687 [(X86rep_stos i32)]>, REP;
Chris Lattner30bf2d82004-08-10 20:17:41 +0000688
Evan Cheng071a2792007-09-11 19:55:27 +0000689let Defs = [RAX, RDX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000690def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
Evan Cheng071a2792007-09-11 19:55:27 +0000691 TB;
Chris Lattnerb89abef2004-02-14 04:45:37 +0000692
Anton Korobeynikov66fac792008-01-15 07:02:33 +0000693let isBarrier = 1, hasCtrlDep = 1 in {
Chris Lattnerda68d302008-01-15 21:58:22 +0000694def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
Anton Korobeynikov66fac792008-01-15 07:02:33 +0000695}
696
Chris Lattner1cca5e32003-08-03 21:54:21 +0000697//===----------------------------------------------------------------------===//
John Criswell4ffff9e2004-04-08 20:31:47 +0000698// Input/Output Instructions...
699//
Evan Cheng071a2792007-09-11 19:55:27 +0000700let Defs = [AL], Uses = [DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000701def IN8rr : I<0xEC, RawFrm, (outs), (ins),
Evan Cheng071a2792007-09-11 19:55:27 +0000702 "in{b}\t{%dx, %al|%AL, %DX}", []>;
703let Defs = [AX], Uses = [DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000704def IN16rr : I<0xED, RawFrm, (outs), (ins),
Evan Cheng071a2792007-09-11 19:55:27 +0000705 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
706let Defs = [EAX], Uses = [DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000707def IN32rr : I<0xED, RawFrm, (outs), (ins),
Evan Cheng071a2792007-09-11 19:55:27 +0000708 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
John Criswell4ffff9e2004-04-08 20:31:47 +0000709
Evan Cheng071a2792007-09-11 19:55:27 +0000710let Defs = [AL] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000711def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng071a2792007-09-11 19:55:27 +0000712 "in{b}\t{$port, %al|%AL, $port}", []>;
713let Defs = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000714def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng071a2792007-09-11 19:55:27 +0000715 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
716let Defs = [EAX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000717def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng071a2792007-09-11 19:55:27 +0000718 "in{l}\t{$port, %eax|%EAX, $port}", []>;
Chris Lattner440bbc22004-04-13 17:19:31 +0000719
Evan Cheng071a2792007-09-11 19:55:27 +0000720let Uses = [DX, AL] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000721def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
Evan Cheng071a2792007-09-11 19:55:27 +0000722 "out{b}\t{%al, %dx|%DX, %AL}", []>;
723let Uses = [DX, AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000724def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
Evan Cheng071a2792007-09-11 19:55:27 +0000725 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
726let Uses = [DX, EAX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000727def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
Evan Cheng071a2792007-09-11 19:55:27 +0000728 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
Chris Lattnerffff7082004-08-01 07:44:35 +0000729
Evan Cheng071a2792007-09-11 19:55:27 +0000730let Uses = [AL] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000731def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng071a2792007-09-11 19:55:27 +0000732 "out{b}\t{%al, $port|$port, %AL}", []>;
733let Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000734def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng071a2792007-09-11 19:55:27 +0000735 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
736let Uses = [EAX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000737def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
Evan Cheng071a2792007-09-11 19:55:27 +0000738 "out{l}\t{%eax, $port|$port, %EAX}", []>;
John Criswell4ffff9e2004-04-08 20:31:47 +0000739
740//===----------------------------------------------------------------------===//
Chris Lattner1cca5e32003-08-03 21:54:21 +0000741// Move Instructions...
742//
Chris Lattnerba7e7562008-01-10 07:59:24 +0000743let neverHasSideEffects = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000744def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000745 "mov{b}\t{$src, $dst|$dst, $src}", []>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000746def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000747 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +0000748def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000749 "mov{l}\t{$src, $dst|$dst, $src}", []>;
Chris Lattnerba7e7562008-01-10 07:59:24 +0000750}
Evan Cheng359e9372008-06-18 08:13:07 +0000751let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000752def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000753 "mov{b}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +0000754 [(set GR8:$dst, imm:$src)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000755def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000756 "mov{w}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +0000757 [(set GR16:$dst, imm:$src)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +0000758def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000759 "mov{l}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +0000760 [(set GR32:$dst, imm:$src)]>;
Dan Gohmand45eddd2007-06-26 00:48:07 +0000761}
Evan Cheng64d80e32007-07-19 01:14:50 +0000762def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000763 "mov{b}\t{$src, $dst|$dst, $src}",
Evan Chengb51a0592005-12-10 00:48:20 +0000764 [(store (i8 imm:$src), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000765def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000766 "mov{w}\t{$src, $dst|$dst, $src}",
Evan Chengb51a0592005-12-10 00:48:20 +0000767 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +0000768def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000769 "mov{l}\t{$src, $dst|$dst, $src}",
Evan Chengb51a0592005-12-10 00:48:20 +0000770 [(store (i32 imm:$src), addr:$dst)]>;
Chris Lattner1cca5e32003-08-03 21:54:21 +0000771
Dan Gohman15511cf2008-12-03 18:15:48 +0000772let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000773def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000774 "mov{b}\t{$src, $dst|$dst, $src}",
Chris Lattnerc2406f22009-04-10 00:16:23 +0000775 [(set GR8:$dst, (loadi8 addr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000776def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000777 "mov{w}\t{$src, $dst|$dst, $src}",
Chris Lattnerc2406f22009-04-10 00:16:23 +0000778 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +0000779def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000780 "mov{l}\t{$src, $dst|$dst, $src}",
Chris Lattnerc2406f22009-04-10 00:16:23 +0000781 [(set GR32:$dst, (loadi32 addr:$src))]>;
Evan Cheng2f394262007-08-30 05:49:43 +0000782}
Chris Lattner1cca5e32003-08-03 21:54:21 +0000783
Evan Cheng64d80e32007-07-19 01:14:50 +0000784def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000785 "mov{b}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +0000786 [(store GR8:$src, addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000787def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000788 "mov{w}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +0000789 [(store GR16:$src, addr:$dst)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +0000790def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000791 "mov{l}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +0000792 [(store GR32:$src, addr:$dst)]>;
Dan Gohman21e3dfb2009-04-13 16:09:41 +0000793
Dan Gohman4af325d2009-04-27 16:41:36 +0000794// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
795// that they can be used for copying and storing h registers, which can't be
796// encoded when a REX prefix is present.
Dan Gohman6d9305c2009-04-15 00:04:23 +0000797let neverHasSideEffects = 1 in
Dan Gohmandf7dfc72009-04-15 19:48:57 +0000798def MOV8rr_NOREX : I<0x88, MRMDestReg,
799 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
Dan Gohman6d9305c2009-04-15 00:04:23 +0000800 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Evan Cheng8c147402009-04-30 00:58:57 +0000801let mayStore = 1 in
Dan Gohman6d9305c2009-04-15 00:04:23 +0000802def MOV8mr_NOREX : I<0x88, MRMDestMem,
803 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
804 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Evan Cheng8c147402009-04-30 00:58:57 +0000805let mayLoad = 1,
806 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
Dan Gohman4af325d2009-04-27 16:41:36 +0000807def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
808 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
809 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
Dan Gohman21e3dfb2009-04-13 16:09:41 +0000810
Chris Lattner1cca5e32003-08-03 21:54:21 +0000811//===----------------------------------------------------------------------===//
812// Fixed-Register Multiplication and Division Instructions...
813//
Chris Lattner1cca5e32003-08-03 21:54:21 +0000814
Chris Lattnerc8f45872003-08-04 04:59:56 +0000815// Extra precision multiplication
Evan Cheng24f2ea32007-09-14 21:48:26 +0000816let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Dan Gohmanb1576f52007-07-31 20:11:57 +0000817def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
Evan Chengcf74a7c2006-01-15 10:05:20 +0000818 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
819 // This probably ought to be moved to a def : Pat<> if the
820 // syntax can be accepted.
Bill Wendlingd350e022008-12-12 21:15:41 +0000821 [(set AL, (mul AL, GR8:$src)),
822 (implicit EFLAGS)]>; // AL,AH = AL*GR8
823
Chris Lattnera731c9f2008-01-11 07:18:17 +0000824let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
Bill Wendlingd350e022008-12-12 21:15:41 +0000825def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
826 "mul{w}\t$src",
827 []>, OpSize; // AX,DX = AX*GR16
828
Chris Lattnera731c9f2008-01-11 07:18:17 +0000829let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
Bill Wendlingd350e022008-12-12 21:15:41 +0000830def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
831 "mul{l}\t$src",
832 []>; // EAX,EDX = EAX*GR32
833
Evan Cheng24f2ea32007-09-14 21:48:26 +0000834let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000835def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000836 "mul{b}\t$src",
Evan Chengcf74a7c2006-01-15 10:05:20 +0000837 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
838 // This probably ought to be moved to a def : Pat<> if the
839 // syntax can be accepted.
Bill Wendlingd350e022008-12-12 21:15:41 +0000840 [(set AL, (mul AL, (loadi8 addr:$src))),
841 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
842
Chris Lattnerba7e7562008-01-10 07:59:24 +0000843let mayLoad = 1, neverHasSideEffects = 1 in {
Evan Cheng24f2ea32007-09-14 21:48:26 +0000844let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000845def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
Bill Wendlingd350e022008-12-12 21:15:41 +0000846 "mul{w}\t$src",
847 []>, OpSize; // AX,DX = AX*[mem16]
848
Evan Cheng24f2ea32007-09-14 21:48:26 +0000849let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000850def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
Bill Wendlingd350e022008-12-12 21:15:41 +0000851 "mul{l}\t$src",
852 []>; // EAX,EDX = EAX*[mem32]
Chris Lattnerba7e7562008-01-10 07:59:24 +0000853}
Chris Lattner1cca5e32003-08-03 21:54:21 +0000854
Chris Lattnerba7e7562008-01-10 07:59:24 +0000855let neverHasSideEffects = 1 in {
Evan Cheng24f2ea32007-09-14 21:48:26 +0000856let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Cheng071a2792007-09-11 19:55:27 +0000857def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
858 // AL,AH = AL*GR8
Evan Cheng24f2ea32007-09-14 21:48:26 +0000859let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Dan Gohmanb1576f52007-07-31 20:11:57 +0000860def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
Evan Cheng071a2792007-09-11 19:55:27 +0000861 OpSize; // AX,DX = AX*GR16
Evan Cheng24f2ea32007-09-14 21:48:26 +0000862let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
Evan Cheng071a2792007-09-11 19:55:27 +0000863def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
864 // EAX,EDX = EAX*GR32
Chris Lattnerba7e7562008-01-10 07:59:24 +0000865let mayLoad = 1 in {
Evan Cheng24f2ea32007-09-14 21:48:26 +0000866let Defs = [AL,AH,EFLAGS], Uses = [AL] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000867def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
Evan Cheng071a2792007-09-11 19:55:27 +0000868 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
Evan Cheng24f2ea32007-09-14 21:48:26 +0000869let Defs = [AX,DX,EFLAGS], Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000870def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
Evan Cheng071a2792007-09-11 19:55:27 +0000871 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
872let Defs = [EAX,EDX], Uses = [EAX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000873def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
Evan Cheng071a2792007-09-11 19:55:27 +0000874 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
Chris Lattnerba7e7562008-01-10 07:59:24 +0000875}
Dan Gohmanc99da132008-11-18 21:29:14 +0000876} // neverHasSideEffects
Chris Lattner1e6a7152005-04-06 04:19:22 +0000877
Chris Lattnerc8f45872003-08-04 04:59:56 +0000878// unsigned division/remainder
Dale Johannesen2cb48ea2008-10-07 18:54:28 +0000879let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000880def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Evan Cheng071a2792007-09-11 19:55:27 +0000881 "div{b}\t$src", []>;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000882let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000883def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Evan Cheng071a2792007-09-11 19:55:27 +0000884 "div{w}\t$src", []>, OpSize;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000885let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000886def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Evan Cheng071a2792007-09-11 19:55:27 +0000887 "div{l}\t$src", []>;
Chris Lattnerba7e7562008-01-10 07:59:24 +0000888let mayLoad = 1 in {
Dale Johannesen2cb48ea2008-10-07 18:54:28 +0000889let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000890def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Evan Cheng071a2792007-09-11 19:55:27 +0000891 "div{b}\t$src", []>;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000892let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000893def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Evan Cheng071a2792007-09-11 19:55:27 +0000894 "div{w}\t$src", []>, OpSize;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000895let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000896def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
Evan Cheng071a2792007-09-11 19:55:27 +0000897 "div{l}\t$src", []>;
Chris Lattnerba7e7562008-01-10 07:59:24 +0000898}
Chris Lattner1cca5e32003-08-03 21:54:21 +0000899
Chris Lattnerfc752712004-08-01 09:52:59 +0000900// Signed division/remainder.
Dale Johannesen2cb48ea2008-10-07 18:54:28 +0000901let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000902def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
Evan Cheng071a2792007-09-11 19:55:27 +0000903 "idiv{b}\t$src", []>;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000904let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000905def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
Evan Cheng071a2792007-09-11 19:55:27 +0000906 "idiv{w}\t$src", []>, OpSize;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000907let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000908def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
Evan Cheng071a2792007-09-11 19:55:27 +0000909 "idiv{l}\t$src", []>;
Chris Lattnerba7e7562008-01-10 07:59:24 +0000910let mayLoad = 1, mayLoad = 1 in {
Dale Johannesen2cb48ea2008-10-07 18:54:28 +0000911let Defs = [AL,AH,EFLAGS], Uses = [AX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000912def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
Evan Cheng071a2792007-09-11 19:55:27 +0000913 "idiv{b}\t$src", []>;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000914let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000915def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
Evan Cheng071a2792007-09-11 19:55:27 +0000916 "idiv{w}\t$src", []>, OpSize;
Evan Cheng24f2ea32007-09-14 21:48:26 +0000917let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000918def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
Evan Cheng071a2792007-09-11 19:55:27 +0000919 "idiv{l}\t$src", []>;
Chris Lattnerba7e7562008-01-10 07:59:24 +0000920}
Chris Lattner1cca5e32003-08-03 21:54:21 +0000921
Chris Lattner1cca5e32003-08-03 21:54:21 +0000922//===----------------------------------------------------------------------===//
Chris Lattnerba7e7562008-01-10 07:59:24 +0000923// Two address Instructions.
Chris Lattner1cca5e32003-08-03 21:54:21 +0000924//
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +0000925let isTwoAddress = 1 in {
Chris Lattner1cca5e32003-08-03 21:54:21 +0000926
Alkis Evlogimenosa3f66842004-03-12 17:59:56 +0000927// Conditional moves
Evan Cheng0488db92007-09-25 01:57:46 +0000928let Uses = [EFLAGS] in {
Evan Cheng7ad42d92007-10-05 23:13:21 +0000929let isCommutable = 1 in {
Evan Cheng069287d2006-05-16 07:21:53 +0000930def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +0000931 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000932 "cmovb\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000933 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000934 X86_COND_B, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000935 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +0000936def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +0000937 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000938 "cmovb\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000939 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000940 X86_COND_B, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000941 TB;
Evan Cheng069287d2006-05-16 07:21:53 +0000942def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +0000943 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000944 "cmovae\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000945 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000946 X86_COND_AE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000947 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +0000948def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +0000949 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000950 "cmovae\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000951 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000952 X86_COND_AE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000953 TB;
Evan Cheng069287d2006-05-16 07:21:53 +0000954def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +0000955 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000956 "cmove\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000957 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000958 X86_COND_E, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000959 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +0000960def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +0000961 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000962 "cmove\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000963 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000964 X86_COND_E, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000965 TB;
Evan Cheng069287d2006-05-16 07:21:53 +0000966def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +0000967 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000968 "cmovne\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000969 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000970 X86_COND_NE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000971 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +0000972def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +0000973 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000974 "cmovne\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000975 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000976 X86_COND_NE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000977 TB;
Evan Cheng069287d2006-05-16 07:21:53 +0000978def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +0000979 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000980 "cmovbe\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000981 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000982 X86_COND_BE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000983 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +0000984def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +0000985 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000986 "cmovbe\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000987 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000988 X86_COND_BE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000989 TB;
Evan Cheng069287d2006-05-16 07:21:53 +0000990def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +0000991 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000992 "cmova\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000993 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +0000994 X86_COND_A, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +0000995 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +0000996def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +0000997 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +0000998 "cmova\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +0000999 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001000 X86_COND_A, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001001 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001002def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001003 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001004 "cmovl\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001005 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001006 X86_COND_L, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001007 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001008def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001009 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001010 "cmovl\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001011 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001012 X86_COND_L, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001013 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001014def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001015 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001016 "cmovge\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001017 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001018 X86_COND_GE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001019 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001020def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001021 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001022 "cmovge\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001023 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001024 X86_COND_GE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001025 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001026def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001027 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001028 "cmovle\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001029 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001030 X86_COND_LE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001031 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001032def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001033 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001034 "cmovle\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001035 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001036 X86_COND_LE, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001037 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001038def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001039 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001040 "cmovg\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001041 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001042 X86_COND_G, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001043 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001044def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001045 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001046 "cmovg\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001047 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001048 X86_COND_G, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001049 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001050def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001051 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001052 "cmovs\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001053 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001054 X86_COND_S, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001055 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001056def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001057 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001058 "cmovs\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001059 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001060 X86_COND_S, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001061 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001062def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001063 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001064 "cmovns\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001065 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001066 X86_COND_NS, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001067 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001068def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001069 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001070 "cmovns\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001071 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001072 X86_COND_NS, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001073 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001074def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001075 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001076 "cmovp\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001077 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001078 X86_COND_P, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001079 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001080def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001081 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001082 "cmovp\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001083 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001084 X86_COND_P, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001085 TB;
Evan Cheng069287d2006-05-16 07:21:53 +00001086def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
Evan Cheng64d80e32007-07-19 01:14:50 +00001087 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001088 "cmovnp\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001089 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001090 X86_COND_NP, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001091 TB, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00001092def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
Evan Cheng64d80e32007-07-19 01:14:50 +00001093 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001094 "cmovnp\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001095 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
Evan Chenge5f62042007-09-29 00:00:36 +00001096 X86_COND_NP, EFLAGS))]>,
Evan Cheng71fb9ad2006-01-26 00:29:36 +00001097 TB;
Dan Gohman305fceb2009-01-07 00:35:10 +00001098def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1099 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1100 "cmovo\t{$src2, $dst|$dst, $src2}",
1101 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1102 X86_COND_O, EFLAGS))]>,
1103 TB, OpSize;
1104def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1105 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1106 "cmovo\t{$src2, $dst|$dst, $src2}",
1107 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1108 X86_COND_O, EFLAGS))]>,
Evan Cheng0488db92007-09-25 01:57:46 +00001109 TB;
Dan Gohman305fceb2009-01-07 00:35:10 +00001110def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1111 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1112 "cmovno\t{$src2, $dst|$dst, $src2}",
1113 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1114 X86_COND_NO, EFLAGS))]>,
1115 TB, OpSize;
1116def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1117 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1118 "cmovno\t{$src2, $dst|$dst, $src2}",
1119 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1120 X86_COND_NO, EFLAGS))]>,
1121 TB;
1122} // isCommutable = 1
Evan Cheng7ad42d92007-10-05 23:13:21 +00001123
1124def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1125 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1126 "cmovb\t{$src2, $dst|$dst, $src2}",
1127 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1128 X86_COND_B, EFLAGS))]>,
1129 TB, OpSize;
1130def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1131 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1132 "cmovb\t{$src2, $dst|$dst, $src2}",
1133 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1134 X86_COND_B, EFLAGS))]>,
1135 TB;
1136def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1137 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1138 "cmovae\t{$src2, $dst|$dst, $src2}",
1139 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1140 X86_COND_AE, EFLAGS))]>,
1141 TB, OpSize;
1142def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1143 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1144 "cmovae\t{$src2, $dst|$dst, $src2}",
1145 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1146 X86_COND_AE, EFLAGS))]>,
1147 TB;
1148def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1149 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1150 "cmove\t{$src2, $dst|$dst, $src2}",
1151 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1152 X86_COND_E, EFLAGS))]>,
1153 TB, OpSize;
1154def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1155 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1156 "cmove\t{$src2, $dst|$dst, $src2}",
1157 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1158 X86_COND_E, EFLAGS))]>,
1159 TB;
1160def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1161 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1162 "cmovne\t{$src2, $dst|$dst, $src2}",
1163 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1164 X86_COND_NE, EFLAGS))]>,
1165 TB, OpSize;
1166def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1167 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1168 "cmovne\t{$src2, $dst|$dst, $src2}",
1169 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1170 X86_COND_NE, EFLAGS))]>,
1171 TB;
1172def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1173 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1174 "cmovbe\t{$src2, $dst|$dst, $src2}",
1175 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1176 X86_COND_BE, EFLAGS))]>,
1177 TB, OpSize;
1178def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1179 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1180 "cmovbe\t{$src2, $dst|$dst, $src2}",
1181 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1182 X86_COND_BE, EFLAGS))]>,
1183 TB;
1184def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1185 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1186 "cmova\t{$src2, $dst|$dst, $src2}",
1187 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1188 X86_COND_A, EFLAGS))]>,
1189 TB, OpSize;
1190def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1191 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1192 "cmova\t{$src2, $dst|$dst, $src2}",
1193 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1194 X86_COND_A, EFLAGS))]>,
1195 TB;
1196def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1197 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1198 "cmovl\t{$src2, $dst|$dst, $src2}",
1199 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1200 X86_COND_L, EFLAGS))]>,
1201 TB, OpSize;
1202def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1203 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1204 "cmovl\t{$src2, $dst|$dst, $src2}",
1205 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1206 X86_COND_L, EFLAGS))]>,
1207 TB;
1208def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1209 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1210 "cmovge\t{$src2, $dst|$dst, $src2}",
1211 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1212 X86_COND_GE, EFLAGS))]>,
1213 TB, OpSize;
1214def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1215 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1216 "cmovge\t{$src2, $dst|$dst, $src2}",
1217 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1218 X86_COND_GE, EFLAGS))]>,
1219 TB;
1220def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1221 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1222 "cmovle\t{$src2, $dst|$dst, $src2}",
1223 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1224 X86_COND_LE, EFLAGS))]>,
1225 TB, OpSize;
1226def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1227 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1228 "cmovle\t{$src2, $dst|$dst, $src2}",
1229 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1230 X86_COND_LE, EFLAGS))]>,
1231 TB;
1232def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1233 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1234 "cmovg\t{$src2, $dst|$dst, $src2}",
1235 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1236 X86_COND_G, EFLAGS))]>,
1237 TB, OpSize;
1238def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1239 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1240 "cmovg\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1242 X86_COND_G, EFLAGS))]>,
1243 TB;
1244def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1245 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1246 "cmovs\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1248 X86_COND_S, EFLAGS))]>,
1249 TB, OpSize;
1250def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1251 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1252 "cmovs\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1254 X86_COND_S, EFLAGS))]>,
1255 TB;
1256def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1257 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1258 "cmovns\t{$src2, $dst|$dst, $src2}",
1259 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1260 X86_COND_NS, EFLAGS))]>,
1261 TB, OpSize;
1262def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1263 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1264 "cmovns\t{$src2, $dst|$dst, $src2}",
1265 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1266 X86_COND_NS, EFLAGS))]>,
1267 TB;
1268def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1269 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1270 "cmovp\t{$src2, $dst|$dst, $src2}",
1271 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1272 X86_COND_P, EFLAGS))]>,
1273 TB, OpSize;
1274def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1275 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1276 "cmovp\t{$src2, $dst|$dst, $src2}",
1277 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1278 X86_COND_P, EFLAGS))]>,
1279 TB;
1280def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1281 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1282 "cmovnp\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1284 X86_COND_NP, EFLAGS))]>,
1285 TB, OpSize;
Dan Gohman305fceb2009-01-07 00:35:10 +00001286def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1287 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1288 "cmovnp\t{$src2, $dst|$dst, $src2}",
1289 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1290 X86_COND_NP, EFLAGS))]>,
1291 TB;
1292def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1293 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1294 "cmovo\t{$src2, $dst|$dst, $src2}",
1295 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1296 X86_COND_O, EFLAGS))]>,
1297 TB, OpSize;
1298def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1299 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1300 "cmovo\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1302 X86_COND_O, EFLAGS))]>,
1303 TB;
1304def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1305 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1306 "cmovno\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1308 X86_COND_NO, EFLAGS))]>,
1309 TB, OpSize;
1310def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1311 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1312 "cmovno\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1314 X86_COND_NO, EFLAGS))]>,
1315 TB;
Evan Cheng0488db92007-09-25 01:57:46 +00001316} // Uses = [EFLAGS]
1317
1318
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001319// unary instructions
Evan Cheng1693e482006-07-19 00:27:29 +00001320let CodeSize = 2 in {
Evan Cheng24f2ea32007-09-14 21:48:26 +00001321let Defs = [EFLAGS] in {
Dan Gohmanb1576f52007-07-31 20:11:57 +00001322def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001323 [(set GR8:$dst, (ineg GR8:$src)),
1324 (implicit EFLAGS)]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001325def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001326 [(set GR16:$dst, (ineg GR16:$src)),
1327 (implicit EFLAGS)]>, OpSize;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001328def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001329 [(set GR32:$dst, (ineg GR32:$src)),
1330 (implicit EFLAGS)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001331let isTwoAddress = 0 in {
Dan Gohmanb1576f52007-07-31 20:11:57 +00001332 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001333 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1334 (implicit EFLAGS)]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001335 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001336 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1337 (implicit EFLAGS)]>, OpSize;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001338 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001339 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1340 (implicit EFLAGS)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001341}
Evan Cheng24f2ea32007-09-14 21:48:26 +00001342} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001343
Evan Chengaaf414c2009-01-21 02:09:05 +00001344// Match xor -1 to not. Favors these over a move imm + xor to save code size.
1345let AddedComplexity = 15 in {
Dan Gohmanb1576f52007-07-31 20:11:57 +00001346def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
Evan Cheng069287d2006-05-16 07:21:53 +00001347 [(set GR8:$dst, (not GR8:$src))]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001348def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
Evan Cheng069287d2006-05-16 07:21:53 +00001349 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001350def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
Evan Cheng069287d2006-05-16 07:21:53 +00001351 [(set GR32:$dst, (not GR32:$src))]>;
Evan Chengaaf414c2009-01-21 02:09:05 +00001352}
Chris Lattner57a02302004-08-11 04:31:00 +00001353let isTwoAddress = 0 in {
Dan Gohmanb1576f52007-07-31 20:11:57 +00001354 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
Evan Cheng605c4152005-12-13 01:57:51 +00001355 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001356 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
Evan Cheng605c4152005-12-13 01:57:51 +00001357 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001358 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
Evan Cheng605c4152005-12-13 01:57:51 +00001359 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001360}
Evan Cheng1693e482006-07-19 00:27:29 +00001361} // CodeSize
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001362
Evan Chengb51a0592005-12-10 00:48:20 +00001363// TODO: inc/dec is slow for P4, but fast for Pentium-M.
Evan Cheng24f2ea32007-09-14 21:48:26 +00001364let Defs = [EFLAGS] in {
Evan Cheng1693e482006-07-19 00:27:29 +00001365let CodeSize = 2 in
Dan Gohmanb1576f52007-07-31 20:11:57 +00001366def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001367 [(set GR8:$dst, (add GR8:$src, 1)),
1368 (implicit EFLAGS)]>;
Evan Cheng1693e482006-07-19 00:27:29 +00001369let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Dan Gohmanb1576f52007-07-31 20:11:57 +00001370def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001371 [(set GR16:$dst, (add GR16:$src, 1)),
1372 (implicit EFLAGS)]>,
Evan Cheng25ab6902006-09-08 06:48:29 +00001373 OpSize, Requires<[In32BitMode]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001374def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001375 [(set GR32:$dst, (add GR32:$src, 1)),
1376 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00001377}
Evan Cheng1693e482006-07-19 00:27:29 +00001378let isTwoAddress = 0, CodeSize = 2 in {
Dan Gohmanb1576f52007-07-31 20:11:57 +00001379 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001380 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1381 (implicit EFLAGS)]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001382 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001383 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1384 (implicit EFLAGS)]>,
Evan Cheng66f71632007-10-19 21:23:22 +00001385 OpSize, Requires<[In32BitMode]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001386 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001387 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1388 (implicit EFLAGS)]>,
Evan Cheng66f71632007-10-19 21:23:22 +00001389 Requires<[In32BitMode]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001390}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001391
Evan Cheng1693e482006-07-19 00:27:29 +00001392let CodeSize = 2 in
Dan Gohmanb1576f52007-07-31 20:11:57 +00001393def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001394 [(set GR8:$dst, (add GR8:$src, -1)),
1395 (implicit EFLAGS)]>;
Evan Cheng1693e482006-07-19 00:27:29 +00001396let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
Dan Gohmanb1576f52007-07-31 20:11:57 +00001397def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001398 [(set GR16:$dst, (add GR16:$src, -1)),
1399 (implicit EFLAGS)]>,
Evan Cheng25ab6902006-09-08 06:48:29 +00001400 OpSize, Requires<[In32BitMode]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001401def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001402 [(set GR32:$dst, (add GR32:$src, -1)),
1403 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00001404}
Chris Lattner57a02302004-08-11 04:31:00 +00001405
Evan Cheng1693e482006-07-19 00:27:29 +00001406let isTwoAddress = 0, CodeSize = 2 in {
Dan Gohmanb1576f52007-07-31 20:11:57 +00001407 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001408 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1409 (implicit EFLAGS)]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001410 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001411 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1412 (implicit EFLAGS)]>,
Evan Cheng66f71632007-10-19 21:23:22 +00001413 OpSize, Requires<[In32BitMode]>;
Dan Gohmanb1576f52007-07-31 20:11:57 +00001414 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001415 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1416 (implicit EFLAGS)]>,
Evan Cheng66f71632007-10-19 21:23:22 +00001417 Requires<[In32BitMode]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001418}
Evan Cheng24f2ea32007-09-14 21:48:26 +00001419} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001420
1421// Logical operators...
Evan Cheng24f2ea32007-09-14 21:48:26 +00001422let Defs = [EFLAGS] in {
Chris Lattnercc65bee2005-01-02 02:35:46 +00001423let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
Chris Lattner3a173df2004-10-03 20:35:00 +00001424def AND8rr : I<0x20, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00001425 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001426 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001427 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1428 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001429def AND16rr : I<0x21, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00001430 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001431 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001432 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1433 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001434def AND32rr : I<0x21, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00001435 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001436 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001437 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1438 (implicit EFLAGS)]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00001439}
Chris Lattner57a02302004-08-11 04:31:00 +00001440
Chris Lattner3a173df2004-10-03 20:35:00 +00001441def AND8rm : I<0x22, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001442 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001443 "and{b}\t{$src2, $dst|$dst, $src2}",
Chris Lattnerc2406f22009-04-10 00:16:23 +00001444 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
Dan Gohman09a2609e2009-03-03 19:53:46 +00001445 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001446def AND16rm : I<0x23, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001447 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001448 "and{w}\t{$src2, $dst|$dst, $src2}",
Chris Lattnerc2406f22009-04-10 00:16:23 +00001449 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
Dan Gohman09a2609e2009-03-03 19:53:46 +00001450 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001451def AND32rm : I<0x23, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001452 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001453 "and{l}\t{$src2, $dst|$dst, $src2}",
Chris Lattnerc2406f22009-04-10 00:16:23 +00001454 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
Dan Gohman09a2609e2009-03-03 19:53:46 +00001455 (implicit EFLAGS)]>;
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001456
Chris Lattner3a173df2004-10-03 20:35:00 +00001457def AND8ri : Ii8<0x80, MRM4r,
Evan Cheng64d80e32007-07-19 01:14:50 +00001458 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001459 "and{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001460 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1461 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001462def AND16ri : Ii16<0x81, MRM4r,
Evan Cheng64d80e32007-07-19 01:14:50 +00001463 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001464 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001465 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1466 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001467def AND32ri : Ii32<0x81, MRM4r,
Evan Cheng64d80e32007-07-19 01:14:50 +00001468 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001469 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001470 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1471 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001472def AND16ri8 : Ii8<0x83, MRM4r,
Evan Cheng64d80e32007-07-19 01:14:50 +00001473 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001474 "and{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001475 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1476 (implicit EFLAGS)]>,
Evan Cheng9b6b6422005-12-13 00:14:11 +00001477 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001478def AND32ri8 : Ii8<0x83, MRM4r,
Evan Cheng64d80e32007-07-19 01:14:50 +00001479 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001480 "and{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001481 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1482 (implicit EFLAGS)]>;
Chris Lattnerf29ed092004-08-11 05:07:25 +00001483
1484let isTwoAddress = 0 in {
Chris Lattner3a173df2004-10-03 20:35:00 +00001485 def AND8mr : I<0x20, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001486 (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001487 "and{b}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001488 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1489 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001490 def AND16mr : I<0x21, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001491 (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001492 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001493 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1494 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001495 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001496 def AND32mr : I<0x21, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001497 (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001498 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001499 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1500 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001501 def AND8mi : Ii8<0x80, MRM4m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001502 (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001503 "and{b}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001504 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1505 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001506 def AND16mi : Ii16<0x81, MRM4m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001507 (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001508 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001509 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1510 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001511 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001512 def AND32mi : Ii32<0x81, MRM4m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001513 (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001514 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001515 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1516 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001517 def AND16mi8 : Ii8<0x83, MRM4m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001518 (outs), (ins i16mem:$dst, i16i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001519 "and{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001520 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1521 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001522 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001523 def AND32mi8 : Ii8<0x83, MRM4m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001524 (outs), (ins i32mem:$dst, i32i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001525 "and{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001526 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1527 (implicit EFLAGS)]>;
Chris Lattnerf29ed092004-08-11 05:07:25 +00001528}
1529
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001530
Chris Lattnercc65bee2005-01-02 02:35:46 +00001531let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
Evan Cheng64d80e32007-07-19 01:14:50 +00001532def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001533 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001534 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1535 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001536def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001537 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001538 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1539 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001540def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001541 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001542 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1543 (implicit EFLAGS)]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00001544}
Evan Cheng64d80e32007-07-19 01:14:50 +00001545def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001546 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001547 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1548 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001549def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001550 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001551 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1552 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001553def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001554 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001555 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1556 (implicit EFLAGS)]>;
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001557
Evan Cheng64d80e32007-07-19 01:14:50 +00001558def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001559 "or{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001560 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1561 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001562def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001563 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001564 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1565 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001566def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001567 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001568 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1569 (implicit EFLAGS)]>;
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001570
Evan Cheng64d80e32007-07-19 01:14:50 +00001571def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001572 "or{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001573 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1574 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001575def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001576 "or{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001577 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1578 (implicit EFLAGS)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001579let isTwoAddress = 0 in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001580 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001581 "or{b}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001582 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1583 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001584 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001585 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001586 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1587 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001588 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001589 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001590 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1591 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001592 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001593 "or{b}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001594 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1595 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001596 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001597 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001598 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1599 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001600 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001601 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001602 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001603 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1604 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001605 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001606 "or{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001607 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1608 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001609 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001610 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001611 "or{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001612 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1613 (implicit EFLAGS)]>;
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001614} // isTwoAddress = 0
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001615
1616
Evan Cheng359e9372008-06-18 08:13:07 +00001617let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001618 def XOR8rr : I<0x30, MRMDestReg,
1619 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1620 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001621 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1622 (implicit EFLAGS)]>;
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001623 def XOR16rr : I<0x31, MRMDestReg,
1624 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1625 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001626 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1627 (implicit EFLAGS)]>, OpSize;
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001628 def XOR32rr : I<0x31, MRMDestReg,
1629 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1630 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001631 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1632 (implicit EFLAGS)]>;
Evan Cheng359e9372008-06-18 08:13:07 +00001633} // isCommutable = 1
Chris Lattnercc65bee2005-01-02 02:35:46 +00001634
Chris Lattner3a173df2004-10-03 20:35:00 +00001635def XOR8rm : I<0x32, MRMSrcMem ,
Evan Cheng64d80e32007-07-19 01:14:50 +00001636 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001637 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001638 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1639 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001640def XOR16rm : I<0x33, MRMSrcMem ,
Evan Cheng64d80e32007-07-19 01:14:50 +00001641 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001642 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001643 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1644 (implicit EFLAGS)]>,
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001645 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001646def XOR32rm : I<0x33, MRMSrcMem ,
Evan Cheng64d80e32007-07-19 01:14:50 +00001647 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001648 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001649 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1650 (implicit EFLAGS)]>;
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001651
Bill Wendling75cf88f2008-05-29 03:46:36 +00001652def XOR8ri : Ii8<0x80, MRM6r,
1653 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1654 "xor{b}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001655 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1656 (implicit EFLAGS)]>;
Bill Wendling75cf88f2008-05-29 03:46:36 +00001657def XOR16ri : Ii16<0x81, MRM6r,
1658 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1659 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001660 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1661 (implicit EFLAGS)]>, OpSize;
Bill Wendling75cf88f2008-05-29 03:46:36 +00001662def XOR32ri : Ii32<0x81, MRM6r,
1663 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1664 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001665 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1666 (implicit EFLAGS)]>;
Bill Wendling75cf88f2008-05-29 03:46:36 +00001667def XOR16ri8 : Ii8<0x83, MRM6r,
1668 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1669 "xor{w}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001670 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1671 (implicit EFLAGS)]>,
Bill Wendling75cf88f2008-05-29 03:46:36 +00001672 OpSize;
1673def XOR32ri8 : Ii8<0x83, MRM6r,
1674 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1675 "xor{l}\t{$src2, $dst|$dst, $src2}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001676 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1677 (implicit EFLAGS)]>;
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001678
Chris Lattner57a02302004-08-11 04:31:00 +00001679let isTwoAddress = 0 in {
Chris Lattner3a173df2004-10-03 20:35:00 +00001680 def XOR8mr : I<0x30, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001681 (outs), (ins i8mem :$dst, GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001682 "xor{b}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001683 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1684 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001685 def XOR16mr : I<0x31, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001686 (outs), (ins i16mem:$dst, GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001687 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001688 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1689 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001690 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001691 def XOR32mr : I<0x31, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00001692 (outs), (ins i32mem:$dst, GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001693 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001694 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1695 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001696 def XOR8mi : Ii8<0x80, MRM6m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001697 (outs), (ins i8mem :$dst, i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001698 "xor{b}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001699 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1700 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001701 def XOR16mi : Ii16<0x81, MRM6m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001702 (outs), (ins i16mem:$dst, i16imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001703 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001704 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1705 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001706 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001707 def XOR32mi : Ii32<0x81, MRM6m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001708 (outs), (ins i32mem:$dst, i32imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001709 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001710 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1711 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00001712 def XOR16mi8 : Ii8<0x83, MRM6m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001713 (outs), (ins i16mem:$dst, i16i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001714 "xor{w}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001715 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1716 (implicit EFLAGS)]>,
Evan Cheng0ef3a772005-12-13 01:41:36 +00001717 OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00001718 def XOR32mi8 : Ii8<0x83, MRM6m,
Evan Cheng64d80e32007-07-19 01:14:50 +00001719 (outs), (ins i32mem:$dst, i32i8imm :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001720 "xor{l}\t{$src, $dst|$dst, $src}",
Dan Gohman09a2609e2009-03-03 19:53:46 +00001721 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1722 (implicit EFLAGS)]>;
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001723} // isTwoAddress = 0
Evan Cheng24f2ea32007-09-14 21:48:26 +00001724} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001725
1726// Shift instructions
Evan Cheng24f2ea32007-09-14 21:48:26 +00001727let Defs = [EFLAGS] in {
Evan Cheng071a2792007-09-11 19:55:27 +00001728let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001729def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001730 "shl{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001731 [(set GR8:$dst, (shl GR8:$src, CL))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001732def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001733 "shl{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001734 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001735def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001736 "shl{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001737 [(set GR32:$dst, (shl GR32:$src, CL))]>;
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001738} // Uses = [CL]
Chris Lattnercc65bee2005-01-02 02:35:46 +00001739
Evan Cheng64d80e32007-07-19 01:14:50 +00001740def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001741 "shl{b}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001742 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00001743let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Evan Cheng64d80e32007-07-19 01:14:50 +00001744def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001745 "shl{w}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001746 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001747def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001748 "shl{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001749 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattnerf9b3f372008-01-11 18:00:50 +00001750// NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1751// cheaper.
Bill Wendlingbd0879d2008-05-29 01:02:09 +00001752} // isConvertibleToThreeAddress = 1
Evan Cheng09c54572006-06-29 00:36:51 +00001753
Chris Lattnerf29ed092004-08-11 05:07:25 +00001754let isTwoAddress = 0 in {
Evan Cheng071a2792007-09-11 19:55:27 +00001755 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001756 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001757 "shl{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001758 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001759 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001760 "shl{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001761 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001762 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001763 "shl{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001764 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1765 }
Evan Cheng64d80e32007-07-19 01:14:50 +00001766 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001767 "shl{b}\t{$src, $dst|$dst, $src}",
Evan Cheng763b0292005-12-13 02:34:51 +00001768 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001769 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001770 "shl{w}\t{$src, $dst|$dst, $src}",
Evan Cheng763b0292005-12-13 02:34:51 +00001771 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1772 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001773 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001774 "shl{l}\t{$src, $dst|$dst, $src}",
Evan Cheng763b0292005-12-13 02:34:51 +00001775 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng09c54572006-06-29 00:36:51 +00001776
1777 // Shift by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001778 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001779 "shl{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001780 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001781 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001782 "shl{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001783 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1784 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001785 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001786 "shl{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001787 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattnerf29ed092004-08-11 05:07:25 +00001788}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001789
Evan Cheng071a2792007-09-11 19:55:27 +00001790let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001791def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001792 "shr{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001793 [(set GR8:$dst, (srl GR8:$src, CL))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001794def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001795 "shr{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001796 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001797def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001798 "shr{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001799 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1800}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001801
Evan Cheng64d80e32007-07-19 01:14:50 +00001802def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001803 "shr{b}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001804 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001805def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001806 "shr{w}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001807 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001808def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001809 "shr{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001810 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattnerf29ed092004-08-11 05:07:25 +00001811
Evan Cheng09c54572006-06-29 00:36:51 +00001812// Shift by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001813def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001814 "shr{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001815 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001816def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001817 "shr{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001818 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001819def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001820 "shr{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001821 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1822
Chris Lattner57a02302004-08-11 04:31:00 +00001823let isTwoAddress = 0 in {
Evan Cheng071a2792007-09-11 19:55:27 +00001824 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001825 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001826 "shr{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001827 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001828 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001829 "shr{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001830 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
Evan Cheng071a2792007-09-11 19:55:27 +00001831 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001832 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001833 "shr{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001834 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1835 }
Evan Cheng64d80e32007-07-19 01:14:50 +00001836 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001837 "shr{b}\t{$src, $dst|$dst, $src}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001838 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001839 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001840 "shr{w}\t{$src, $dst|$dst, $src}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001841 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1842 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001843 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001844 "shr{l}\t{$src, $dst|$dst, $src}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001845 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng09c54572006-06-29 00:36:51 +00001846
1847 // Shift by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001848 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001849 "shr{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001850 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001851 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001852 "shr{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001853 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001854 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001855 "shr{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001856 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00001857}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001858
Evan Cheng071a2792007-09-11 19:55:27 +00001859let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001860def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001861 "sar{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001862 [(set GR8:$dst, (sra GR8:$src, CL))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001863def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001864 "sar{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001865 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001866def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001867 "sar{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001868 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1869}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001870
Evan Cheng64d80e32007-07-19 01:14:50 +00001871def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001872 "sar{b}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001873 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001874def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001875 "sar{w}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001876 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
Chris Lattner3d36a9f2005-12-05 02:40:25 +00001877 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001878def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001879 "sar{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001880 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
Evan Cheng09c54572006-06-29 00:36:51 +00001881
1882// Shift by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001883def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001884 "sar{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001885 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001886def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001887 "sar{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001888 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001889def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001890 "sar{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001891 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1892
Chris Lattnerf29ed092004-08-11 05:07:25 +00001893let isTwoAddress = 0 in {
Evan Cheng071a2792007-09-11 19:55:27 +00001894 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001895 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001896 "sar{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001897 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001898 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001899 "sar{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001900 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001901 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001902 "sar{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001903 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1904 }
Evan Cheng64d80e32007-07-19 01:14:50 +00001905 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001906 "sar{b}\t{$src, $dst|$dst, $src}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001907 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001908 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001909 "sar{w}\t{$src, $dst|$dst, $src}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001910 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1911 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001912 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001913 "sar{l}\t{$src, $dst|$dst, $src}",
Evan Cheng85dd8892005-12-13 07:24:22 +00001914 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng09c54572006-06-29 00:36:51 +00001915
1916 // Shift by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001917 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001918 "sar{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001919 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001920 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001921 "sar{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001922 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1923 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001924 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001925 "sar{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001926 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattnerf29ed092004-08-11 05:07:25 +00001927}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00001928
Chris Lattner40ff6332005-01-19 07:50:03 +00001929// Rotate instructions
1930// FIXME: provide shorter instructions when imm8 == 1
Evan Cheng071a2792007-09-11 19:55:27 +00001931let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001932def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001933 "rol{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001934 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001935def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001936 "rol{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001937 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001938def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001939 "rol{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001940 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1941}
Chris Lattner40ff6332005-01-19 07:50:03 +00001942
Evan Cheng64d80e32007-07-19 01:14:50 +00001943def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001944 "rol{b}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001945 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001946def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001947 "rol{w}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001948 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001949def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001950 "rol{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00001951 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattner40ff6332005-01-19 07:50:03 +00001952
Evan Cheng09c54572006-06-29 00:36:51 +00001953// Rotate by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001954def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001955 "rol{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001956 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001957def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001958 "rol{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001959 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001960def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001961 "rol{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001962 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1963
Chris Lattner40ff6332005-01-19 07:50:03 +00001964let isTwoAddress = 0 in {
Evan Cheng071a2792007-09-11 19:55:27 +00001965 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00001966 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001967 "rol{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001968 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001969 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001970 "rol{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001971 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001972 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001973 "rol{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00001974 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1975 }
Evan Cheng64d80e32007-07-19 01:14:50 +00001976 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001977 "rol{b}\t{$src, $dst|$dst, $src}",
Evan Chengeb422a72006-01-11 23:20:05 +00001978 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001979 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001980 "rol{w}\t{$src, $dst|$dst, $src}",
Evan Chengeb422a72006-01-11 23:20:05 +00001981 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1982 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001983 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001984 "rol{l}\t{$src, $dst|$dst, $src}",
Evan Chengeb422a72006-01-11 23:20:05 +00001985 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng09c54572006-06-29 00:36:51 +00001986
1987 // Rotate by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00001988 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001989 "rol{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001990 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001991 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001992 "rol{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001993 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1994 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00001995 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00001996 "rol{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00001997 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner40ff6332005-01-19 07:50:03 +00001998}
1999
Evan Cheng071a2792007-09-11 19:55:27 +00002000let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002001def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002002 "ror{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002003 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002004def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002005 "ror{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002006 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002007def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002008 "ror{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002009 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2010}
Chris Lattner40ff6332005-01-19 07:50:03 +00002011
Evan Cheng64d80e32007-07-19 01:14:50 +00002012def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002013 "ror{b}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002014 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002015def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002016 "ror{w}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002017 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002018def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002019 "ror{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002020 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
Evan Cheng09c54572006-06-29 00:36:51 +00002021
2022// Rotate by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00002023def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002024 "ror{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00002025 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002026def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002027 "ror{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00002028 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002029def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002030 "ror{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00002031 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2032
Chris Lattner40ff6332005-01-19 07:50:03 +00002033let isTwoAddress = 0 in {
Evan Cheng071a2792007-09-11 19:55:27 +00002034 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002035 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002036 "ror{b}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002037 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002038 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002039 "ror{w}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002040 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002041 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002042 "ror{l}\t{%cl, $dst|$dst, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002043 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2044 }
Evan Cheng64d80e32007-07-19 01:14:50 +00002045 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002046 "ror{b}\t{$src, $dst|$dst, $src}",
Evan Chengeb422a72006-01-11 23:20:05 +00002047 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002048 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002049 "ror{w}\t{$src, $dst|$dst, $src}",
Evan Chengeb422a72006-01-11 23:20:05 +00002050 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2051 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002052 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002053 "ror{l}\t{$src, $dst|$dst, $src}",
Evan Chengeb422a72006-01-11 23:20:05 +00002054 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Evan Cheng09c54572006-06-29 00:36:51 +00002055
2056 // Rotate by 1
Evan Cheng64d80e32007-07-19 01:14:50 +00002057 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002058 "ror{b}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00002059 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002060 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002061 "ror{w}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00002062 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2063 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002064 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002065 "ror{l}\t$dst",
Evan Cheng09c54572006-06-29 00:36:51 +00002066 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner40ff6332005-01-19 07:50:03 +00002067}
2068
2069
2070
2071// Double shift instructions (generalizations of rotate)
Evan Cheng071a2792007-09-11 19:55:27 +00002072let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002073def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002074 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002075 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002076def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002077 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng071a2792007-09-11 19:55:27 +00002078 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002079def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002080 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng069287d2006-05-16 07:21:53 +00002081 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
Evan Cheng071a2792007-09-11 19:55:27 +00002082 TB, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002083def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002084 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng069287d2006-05-16 07:21:53 +00002085 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
Evan Cheng071a2792007-09-11 19:55:27 +00002086 TB, OpSize;
2087}
Chris Lattner41e431b2005-01-19 07:11:01 +00002088
2089let isCommutable = 1 in { // These instructions commute to each other.
Chris Lattner3a173df2004-10-03 20:35:00 +00002090def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002091 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002092 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002093 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002094 (i8 imm:$src3)))]>,
2095 TB;
Chris Lattner3a173df2004-10-03 20:35:00 +00002096def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002097 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002098 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002099 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002100 (i8 imm:$src3)))]>,
2101 TB;
Chris Lattner0df53d22005-01-19 07:31:24 +00002102def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002103 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002104 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002105 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002106 (i8 imm:$src3)))]>,
Chris Lattner0df53d22005-01-19 07:31:24 +00002107 TB, OpSize;
2108def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002109 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002110 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002111 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002112 (i8 imm:$src3)))]>,
Chris Lattner0df53d22005-01-19 07:31:24 +00002113 TB, OpSize;
Chris Lattner41e431b2005-01-19 07:11:01 +00002114}
Chris Lattner0e967d42004-08-01 08:13:11 +00002115
Chris Lattner57a02302004-08-11 04:31:00 +00002116let isTwoAddress = 0 in {
Evan Cheng071a2792007-09-11 19:55:27 +00002117 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002118 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002119 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng069287d2006-05-16 07:21:53 +00002120 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
Evan Cheng071a2792007-09-11 19:55:27 +00002121 addr:$dst)]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002122 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002123 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng069287d2006-05-16 07:21:53 +00002124 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
Evan Cheng071a2792007-09-11 19:55:27 +00002125 addr:$dst)]>, TB;
2126 }
Chris Lattner3a173df2004-10-03 20:35:00 +00002127 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002128 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002129 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002130 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002131 (i8 imm:$src3)), addr:$dst)]>,
Chris Lattnerf124d5e2005-11-18 01:04:42 +00002132 TB;
Chris Lattner3a173df2004-10-03 20:35:00 +00002133 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002134 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002135 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002136 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002137 (i8 imm:$src3)), addr:$dst)]>,
Chris Lattnerf124d5e2005-11-18 01:04:42 +00002138 TB;
Chris Lattner0df53d22005-01-19 07:31:24 +00002139
Evan Cheng071a2792007-09-11 19:55:27 +00002140 let Uses = [CL] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002141 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002142 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng069287d2006-05-16 07:21:53 +00002143 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
Evan Cheng071a2792007-09-11 19:55:27 +00002144 addr:$dst)]>, TB, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002145 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002146 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
Evan Cheng069287d2006-05-16 07:21:53 +00002147 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
Evan Cheng071a2792007-09-11 19:55:27 +00002148 addr:$dst)]>, TB, OpSize;
2149 }
Chris Lattner0df53d22005-01-19 07:31:24 +00002150 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002151 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002152 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002153 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002154 (i8 imm:$src3)), addr:$dst)]>,
Chris Lattner0df53d22005-01-19 07:31:24 +00002155 TB, OpSize;
2156 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002157 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002158 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Evan Cheng069287d2006-05-16 07:21:53 +00002159 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
Evan Chenge3413162006-01-09 18:33:28 +00002160 (i8 imm:$src3)), addr:$dst)]>,
Chris Lattner0df53d22005-01-19 07:31:24 +00002161 TB, OpSize;
Chris Lattner57a02302004-08-11 04:31:00 +00002162}
Evan Cheng24f2ea32007-09-14 21:48:26 +00002163} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002164
2165
Chris Lattnercc65bee2005-01-02 02:35:46 +00002166// Arithmetic.
Evan Cheng24f2ea32007-09-14 21:48:26 +00002167let Defs = [EFLAGS] in {
Chris Lattnercc65bee2005-01-02 02:35:46 +00002168let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002169// Register-Register Addition
2170def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2171 (ins GR8 :$src1, GR8 :$src2),
2172 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002173 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002174 (implicit EFLAGS)]>;
2175
Chris Lattnercc65bee2005-01-02 02:35:46 +00002176let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002177// Register-Register Addition
Evan Cheng071a2792007-09-11 19:55:27 +00002178def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2179 (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002180 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002181 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2182 (implicit EFLAGS)]>, OpSize;
Evan Cheng071a2792007-09-11 19:55:27 +00002183def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2184 (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002185 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002186 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2187 (implicit EFLAGS)]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00002188} // end isConvertibleToThreeAddress
2189} // end isCommutable
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002190
2191// Register-Memory Addition
Evan Cheng071a2792007-09-11 19:55:27 +00002192def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2193 (ins GR8 :$src1, i8mem :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002194 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002195 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2196 (implicit EFLAGS)]>;
Evan Cheng071a2792007-09-11 19:55:27 +00002197def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2198 (ins GR16:$src1, i16mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002199 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002200 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2201 (implicit EFLAGS)]>, OpSize;
Evan Cheng071a2792007-09-11 19:55:27 +00002202def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2203 (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002204 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002205 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2206 (implicit EFLAGS)]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00002207
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002208// Register-Integer Addition
2209def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2210 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002211 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2212 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002213
Chris Lattnercc65bee2005-01-02 02:35:46 +00002214let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002215// Register-Integer Addition
Evan Cheng071a2792007-09-11 19:55:27 +00002216def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2217 (ins GR16:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002218 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002219 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2220 (implicit EFLAGS)]>, OpSize;
Evan Cheng071a2792007-09-11 19:55:27 +00002221def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2222 (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002223 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002224 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2225 (implicit EFLAGS)]>;
Evan Cheng071a2792007-09-11 19:55:27 +00002226def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2227 (ins GR16:$src1, i16i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002228 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002229 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2230 (implicit EFLAGS)]>, OpSize;
Evan Cheng071a2792007-09-11 19:55:27 +00002231def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2232 (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002233 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002234 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2235 (implicit EFLAGS)]>;
Evan Cheng09e3c802006-05-19 18:40:54 +00002236}
Chris Lattner57a02302004-08-11 04:31:00 +00002237
2238let isTwoAddress = 0 in {
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002239 // Memory-Register Addition
Bill Wendlingd350e022008-12-12 21:15:41 +00002240 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002241 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002242 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2243 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002244 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002245 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002246 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2247 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002248 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002249 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002250 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2251 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002252 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002253 "add{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002254 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2255 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002256 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002257 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002258 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2259 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002260 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002261 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002262 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2263 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002264 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002265 "add{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002266 [(store (add (load addr:$dst), i16immSExt8:$src2),
2267 addr:$dst),
2268 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002269 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002270 "add{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002271 [(store (add (load addr:$dst), i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00002272 addr:$dst),
2273 (implicit EFLAGS)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00002274}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002275
Evan Cheng3154cb62007-10-05 17:59:57 +00002276let Uses = [EFLAGS] in {
Chris Lattner10197ff2005-01-03 01:27:59 +00002277let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
Evan Cheng64d80e32007-07-19 01:14:50 +00002278def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002279 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlinge3b3c002008-12-01 23:44:08 +00002280 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
Chris Lattner10197ff2005-01-03 01:27:59 +00002281}
Evan Cheng64d80e32007-07-19 01:14:50 +00002282def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002283 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlinge3b3c002008-12-01 23:44:08 +00002284 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002285def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002286 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlinge3b3c002008-12-01 23:44:08 +00002287 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002288def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002289 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlinge3b3c002008-12-01 23:44:08 +00002290 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
Chris Lattner57a02302004-08-11 04:31:00 +00002291
2292let isTwoAddress = 0 in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002293 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002294 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlinge3b3c002008-12-01 23:44:08 +00002295 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002296 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002297 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlinge3b3c002008-12-01 23:44:08 +00002298 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002299 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002300 "adc{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendling9f248742008-12-02 00:07:05 +00002301 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00002302}
Evan Cheng3154cb62007-10-05 17:59:57 +00002303} // Uses = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002304
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002305// Register-Register Subtraction
2306def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2307 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002308 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2309 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002310def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2311 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002312 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2313 (implicit EFLAGS)]>, OpSize;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002314def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2315 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002316 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2317 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002318
2319// Register-Memory Subtraction
2320def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2321 (ins GR8 :$src1, i8mem :$src2),
2322 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002323 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2324 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002325def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2326 (ins GR16:$src1, i16mem:$src2),
2327 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002328 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2329 (implicit EFLAGS)]>, OpSize;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002330def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2331 (ins GR32:$src1, i32mem:$src2),
2332 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002333 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2334 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002335
2336// Register-Integer Subtraction
2337def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2338 (ins GR8:$src1, i8imm:$src2),
2339 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002340 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2341 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002342def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2343 (ins GR16:$src1, i16imm:$src2),
2344 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002345 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2346 (implicit EFLAGS)]>, OpSize;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002347def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2348 (ins GR32:$src1, i32imm:$src2),
2349 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002350 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2351 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002352def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2353 (ins GR16:$src1, i16i8imm:$src2),
2354 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002355 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2356 (implicit EFLAGS)]>, OpSize;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002357def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2358 (ins GR32:$src1, i32i8imm:$src2),
2359 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002360 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2361 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002362
Chris Lattner57a02302004-08-11 04:31:00 +00002363let isTwoAddress = 0 in {
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002364 // Memory-Register Subtraction
Evan Cheng64d80e32007-07-19 01:14:50 +00002365 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002366 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002367 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2368 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002369 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002370 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002371 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2372 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002373 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002374 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002375 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2376 (implicit EFLAGS)]>;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002377
2378 // Memory-Integer Subtraction
Evan Cheng64d80e32007-07-19 01:14:50 +00002379 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002380 "sub{b}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002381 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2382 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002383 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002384 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002385 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2386 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002387 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002388 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002389 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2390 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002391 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002392 "sub{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002393 [(store (sub (load addr:$dst), i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00002394 addr:$dst),
2395 (implicit EFLAGS)]>, OpSize;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002396 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002397 "sub{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002398 [(store (sub (load addr:$dst), i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00002399 addr:$dst),
2400 (implicit EFLAGS)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00002401}
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002402
Evan Cheng3154cb62007-10-05 17:59:57 +00002403let Uses = [EFLAGS] in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002404def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002405 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng24f2ea32007-09-14 21:48:26 +00002406 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
Chris Lattnerd93d3b02004-10-06 04:01:02 +00002407
Chris Lattner57a02302004-08-11 04:31:00 +00002408let isTwoAddress = 0 in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002409 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002410 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002411 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002412 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002413 "sbb{b}\t{$src2, $dst|$dst, $src2}",
Nate Begeman551bf3f2006-02-17 05:43:56 +00002414 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002415 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002416 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Nate Begeman551bf3f2006-02-17 05:43:56 +00002417 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002418 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002419 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng24f2ea32007-09-14 21:48:26 +00002420 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
Chris Lattner57a02302004-08-11 04:31:00 +00002421}
Evan Cheng64d80e32007-07-19 01:14:50 +00002422def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002423 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002424 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002425def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002426 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002427 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002428def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002429 "sbb{l}\t{$src2, $dst|$dst, $src2}",
Evan Cheng069287d2006-05-16 07:21:53 +00002430 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
Evan Cheng3154cb62007-10-05 17:59:57 +00002431} // Uses = [EFLAGS]
Evan Cheng24f2ea32007-09-14 21:48:26 +00002432} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002433
Evan Cheng24f2ea32007-09-14 21:48:26 +00002434let Defs = [EFLAGS] in {
Chris Lattner10197ff2005-01-03 01:27:59 +00002435let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
Bill Wendlingd350e022008-12-12 21:15:41 +00002436// Register-Register Signed Integer Multiply
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002437def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002438 "imul{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002439 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2440 (implicit EFLAGS)]>, TB, OpSize;
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002441def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002442 "imul{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002443 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2444 (implicit EFLAGS)]>, TB;
Chris Lattner10197ff2005-01-03 01:27:59 +00002445}
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002446
Bill Wendlingd350e022008-12-12 21:15:41 +00002447// Register-Memory Signed Integer Multiply
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002448def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2449 (ins GR16:$src1, i16mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002450 "imul{w}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002451 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2452 (implicit EFLAGS)]>, TB, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002453def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002454 "imul{l}\t{$src2, $dst|$dst, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002455 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2456 (implicit EFLAGS)]>, TB;
Evan Cheng24f2ea32007-09-14 21:48:26 +00002457} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002458} // end Two Address instructions
2459
Chris Lattnerf5d3a832004-08-11 05:31:07 +00002460// Suprisingly enough, these are not two address instructions!
Evan Cheng24f2ea32007-09-14 21:48:26 +00002461let Defs = [EFLAGS] in {
Bill Wendlingd350e022008-12-12 21:15:41 +00002462// Register-Integer Signed Integer Multiply
Evan Cheng069287d2006-05-16 07:21:53 +00002463def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
Evan Cheng64d80e32007-07-19 01:14:50 +00002464 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002465 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002466 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2467 (implicit EFLAGS)]>, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00002468def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
Evan Cheng64d80e32007-07-19 01:14:50 +00002469 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002470 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002471 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2472 (implicit EFLAGS)]>;
Evan Cheng069287d2006-05-16 07:21:53 +00002473def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
Evan Cheng64d80e32007-07-19 01:14:50 +00002474 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002475 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002476 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2477 (implicit EFLAGS)]>, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00002478def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
Evan Cheng64d80e32007-07-19 01:14:50 +00002479 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002480 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002481 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2482 (implicit EFLAGS)]>;
Chris Lattnerf5d3a832004-08-11 05:31:07 +00002483
Bill Wendlingd350e022008-12-12 21:15:41 +00002484// Memory-Integer Signed Integer Multiply
Evan Cheng069287d2006-05-16 07:21:53 +00002485def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
Evan Cheng64d80e32007-07-19 01:14:50 +00002486 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002487 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002488 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2489 (implicit EFLAGS)]>, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00002490def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
Evan Cheng64d80e32007-07-19 01:14:50 +00002491 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002492 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingd350e022008-12-12 21:15:41 +00002493 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2494 (implicit EFLAGS)]>;
Evan Cheng069287d2006-05-16 07:21:53 +00002495def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
Evan Cheng64d80e32007-07-19 01:14:50 +00002496 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002497 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002498 [(set GR16:$dst, (mul (load addr:$src1),
Bill Wendlingd350e022008-12-12 21:15:41 +00002499 i16immSExt8:$src2)),
2500 (implicit EFLAGS)]>, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00002501def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
Evan Cheng64d80e32007-07-19 01:14:50 +00002502 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002503 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Bill Wendlingab55ebd2008-12-12 00:56:36 +00002504 [(set GR32:$dst, (mul (load addr:$src1),
Bill Wendlingd350e022008-12-12 21:15:41 +00002505 i32immSExt8:$src2)),
2506 (implicit EFLAGS)]>;
Evan Cheng24f2ea32007-09-14 21:48:26 +00002507} // Defs = [EFLAGS]
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002508
2509//===----------------------------------------------------------------------===//
2510// Test instructions are just like AND, except they don't generate a result.
Chris Lattner3a173df2004-10-03 20:35:00 +00002511//
Evan Cheng0488db92007-09-25 01:57:46 +00002512let Defs = [EFLAGS] in {
Chris Lattnercc65bee2005-01-02 02:35:46 +00002513let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
Evan Cheng64d80e32007-07-19 01:14:50 +00002514def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
Evan Chenge5f62042007-09-29 00:00:36 +00002515 "test{b}\t{$src2, $src1|$src1, $src2}",
Chris Lattnerce2bcc82008-02-19 17:37:35 +00002516 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
Evan Chenge5f62042007-09-29 00:00:36 +00002517 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002518def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Evan Chenge5f62042007-09-29 00:00:36 +00002519 "test{w}\t{$src2, $src1|$src1, $src2}",
Chris Lattnerce2bcc82008-02-19 17:37:35 +00002520 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
Evan Chenge5f62042007-09-29 00:00:36 +00002521 (implicit EFLAGS)]>,
2522 OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002523def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Evan Chenge5f62042007-09-29 00:00:36 +00002524 "test{l}\t{$src2, $src1|$src1, $src2}",
Chris Lattnerce2bcc82008-02-19 17:37:35 +00002525 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
Evan Chenge5f62042007-09-29 00:00:36 +00002526 (implicit EFLAGS)]>;
Chris Lattnercc65bee2005-01-02 02:35:46 +00002527}
Evan Cheng734503b2006-09-11 02:19:56 +00002528
Evan Cheng64d80e32007-07-19 01:14:50 +00002529def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
Evan Chenge5f62042007-09-29 00:00:36 +00002530 "test{b}\t{$src2, $src1|$src1, $src2}",
2531 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2532 (implicit EFLAGS)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002533def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
Evan Chenge5f62042007-09-29 00:00:36 +00002534 "test{w}\t{$src2, $src1|$src1, $src2}",
2535 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2536 (implicit EFLAGS)]>, OpSize;
Evan Cheng64d80e32007-07-19 01:14:50 +00002537def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
Evan Chenge5f62042007-09-29 00:00:36 +00002538 "test{l}\t{$src2, $src1|$src1, $src2}",
2539 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2540 (implicit EFLAGS)]>;
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002541
Evan Cheng069287d2006-05-16 07:21:53 +00002542def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
Evan Cheng64d80e32007-07-19 01:14:50 +00002543 (outs), (ins GR8:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002544 "test{b}\t{$src2, $src1|$src1, $src2}",
Chris Lattnerce2bcc82008-02-19 17:37:35 +00002545 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
Evan Chenge5f62042007-09-29 00:00:36 +00002546 (implicit EFLAGS)]>;
Evan Cheng069287d2006-05-16 07:21:53 +00002547def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
Evan Cheng64d80e32007-07-19 01:14:50 +00002548 (outs), (ins GR16:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002549 "test{w}\t{$src2, $src1|$src1, $src2}",
Chris Lattnerce2bcc82008-02-19 17:37:35 +00002550 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
Evan Chenge5f62042007-09-29 00:00:36 +00002551 (implicit EFLAGS)]>, OpSize;
Evan Cheng069287d2006-05-16 07:21:53 +00002552def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
Evan Cheng64d80e32007-07-19 01:14:50 +00002553 (outs), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002554 "test{l}\t{$src2, $src1|$src1, $src2}",
Chris Lattnerce2bcc82008-02-19 17:37:35 +00002555 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
Evan Chenge5f62042007-09-29 00:00:36 +00002556 (implicit EFLAGS)]>;
Evan Cheng734503b2006-09-11 02:19:56 +00002557
Evan Chenge5f62042007-09-29 00:00:36 +00002558def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
Evan Cheng64d80e32007-07-19 01:14:50 +00002559 (outs), (ins i8mem:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002560 "test{b}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002561 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2562 (implicit EFLAGS)]>;
2563def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
Evan Cheng64d80e32007-07-19 01:14:50 +00002564 (outs), (ins i16mem:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002565 "test{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002566 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2567 (implicit EFLAGS)]>, OpSize;
2568def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
Evan Cheng64d80e32007-07-19 01:14:50 +00002569 (outs), (ins i32mem:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002570 "test{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002571 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
Evan Cheng0488db92007-09-25 01:57:46 +00002572 (implicit EFLAGS)]>;
2573} // Defs = [EFLAGS]
2574
2575
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002576// Condition code ops, incl. set if equal/not equal/...
Chris Lattnerba7e7562008-01-10 07:59:24 +00002577let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
Evan Cheng071a2792007-09-11 19:55:27 +00002578def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
Chris Lattnerba7e7562008-01-10 07:59:24 +00002579let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
Evan Cheng071a2792007-09-11 19:55:27 +00002580def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
Alkis Evlogimenos5ab29b52004-02-28 22:02:05 +00002581
Evan Cheng0488db92007-09-25 01:57:46 +00002582let Uses = [EFLAGS] in {
Chris Lattner3a173df2004-10-03 20:35:00 +00002583def SETEr : I<0x94, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002584 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002585 "sete\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002586 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002587 TB; // GR8 = ==
Chris Lattner3a173df2004-10-03 20:35:00 +00002588def SETEm : I<0x94, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002589 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002590 "sete\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002591 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002592 TB; // [mem8] = ==
Bill Wendling9f248742008-12-02 00:07:05 +00002593
Chris Lattner3a173df2004-10-03 20:35:00 +00002594def SETNEr : I<0x95, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002595 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002596 "setne\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002597 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002598 TB; // GR8 = !=
Chris Lattner3a173df2004-10-03 20:35:00 +00002599def SETNEm : I<0x95, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002600 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002601 "setne\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002602 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002603 TB; // [mem8] = !=
Bill Wendling9f248742008-12-02 00:07:05 +00002604
Evan Chengd5781fc2005-12-21 20:21:51 +00002605def SETLr : I<0x9C, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002606 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002607 "setl\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002608 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002609 TB; // GR8 = < signed
Evan Chengd5781fc2005-12-21 20:21:51 +00002610def SETLm : I<0x9C, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002611 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002612 "setl\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002613 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002614 TB; // [mem8] = < signed
Bill Wendling9f248742008-12-02 00:07:05 +00002615
Evan Chengd5781fc2005-12-21 20:21:51 +00002616def SETGEr : I<0x9D, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002617 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002618 "setge\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002619 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002620 TB; // GR8 = >= signed
Evan Chengd5781fc2005-12-21 20:21:51 +00002621def SETGEm : I<0x9D, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002622 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002623 "setge\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002624 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002625 TB; // [mem8] = >= signed
Bill Wendling9f248742008-12-02 00:07:05 +00002626
Evan Chengd5781fc2005-12-21 20:21:51 +00002627def SETLEr : I<0x9E, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002628 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002629 "setle\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002630 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002631 TB; // GR8 = <= signed
Evan Chengd5781fc2005-12-21 20:21:51 +00002632def SETLEm : I<0x9E, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002633 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002634 "setle\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002635 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002636 TB; // [mem8] = <= signed
Bill Wendling9f248742008-12-02 00:07:05 +00002637
Evan Chengd5781fc2005-12-21 20:21:51 +00002638def SETGr : I<0x9F, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002639 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002640 "setg\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002641 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002642 TB; // GR8 = > signed
Evan Chengd5781fc2005-12-21 20:21:51 +00002643def SETGm : I<0x9F, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002644 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002645 "setg\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002646 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002647 TB; // [mem8] = > signed
2648
2649def SETBr : I<0x92, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002650 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002651 "setb\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002652 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002653 TB; // GR8 = < unsign
Evan Chengd5781fc2005-12-21 20:21:51 +00002654def SETBm : I<0x92, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002655 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002656 "setb\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002657 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002658 TB; // [mem8] = < unsign
Bill Wendling9f248742008-12-02 00:07:05 +00002659
Evan Chengd5781fc2005-12-21 20:21:51 +00002660def SETAEr : I<0x93, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002661 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002662 "setae\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002663 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002664 TB; // GR8 = >= unsign
Evan Chengd5781fc2005-12-21 20:21:51 +00002665def SETAEm : I<0x93, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002666 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002667 "setae\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002668 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002669 TB; // [mem8] = >= unsign
Bill Wendling9f248742008-12-02 00:07:05 +00002670
Chris Lattner3a173df2004-10-03 20:35:00 +00002671def SETBEr : I<0x96, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002672 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002673 "setbe\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002674 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002675 TB; // GR8 = <= unsign
Chris Lattner3a173df2004-10-03 20:35:00 +00002676def SETBEm : I<0x96, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002677 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002678 "setbe\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002679 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002680 TB; // [mem8] = <= unsign
Bill Wendling9f248742008-12-02 00:07:05 +00002681
Chris Lattner3a173df2004-10-03 20:35:00 +00002682def SETAr : I<0x97, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002683 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002684 "seta\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002685 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002686 TB; // GR8 = > signed
Chris Lattner3a173df2004-10-03 20:35:00 +00002687def SETAm : I<0x97, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002688 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002689 "seta\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002690 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
Evan Chengd5781fc2005-12-21 20:21:51 +00002691 TB; // [mem8] = > signed
Evan Chengd9558e02006-01-06 00:43:03 +00002692
Chris Lattner3a173df2004-10-03 20:35:00 +00002693def SETSr : I<0x98, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002694 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002695 "sets\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002696 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002697 TB; // GR8 = <sign bit>
Chris Lattner3a173df2004-10-03 20:35:00 +00002698def SETSm : I<0x98, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002699 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002700 "sets\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002701 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
Evan Chengd9558e02006-01-06 00:43:03 +00002702 TB; // [mem8] = <sign bit>
Chris Lattner3a173df2004-10-03 20:35:00 +00002703def SETNSr : I<0x99, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002704 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002705 "setns\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002706 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002707 TB; // GR8 = !<sign bit>
Chris Lattner3a173df2004-10-03 20:35:00 +00002708def SETNSm : I<0x99, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002709 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002710 "setns\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002711 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
Evan Chengd9558e02006-01-06 00:43:03 +00002712 TB; // [mem8] = !<sign bit>
Bill Wendling9f248742008-12-02 00:07:05 +00002713
Chris Lattner3a173df2004-10-03 20:35:00 +00002714def SETPr : I<0x9A, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002715 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002716 "setp\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002717 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002718 TB; // GR8 = parity
Chris Lattner3a173df2004-10-03 20:35:00 +00002719def SETPm : I<0x9A, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002720 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002721 "setp\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002722 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
Evan Chengd9558e02006-01-06 00:43:03 +00002723 TB; // [mem8] = parity
Chris Lattnercc65bee2005-01-02 02:35:46 +00002724def SETNPr : I<0x9B, MRM0r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002725 (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002726 "setnp\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002727 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
Evan Cheng069287d2006-05-16 07:21:53 +00002728 TB; // GR8 = not parity
Chris Lattnercc65bee2005-01-02 02:35:46 +00002729def SETNPm : I<0x9B, MRM0m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002730 (outs), (ins i8mem:$dst),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002731 "setnp\t$dst",
Evan Chenge5f62042007-09-29 00:00:36 +00002732 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
Evan Chengd9558e02006-01-06 00:43:03 +00002733 TB; // [mem8] = not parity
Bill Wendling9f248742008-12-02 00:07:05 +00002734
2735def SETOr : I<0x90, MRM0r,
2736 (outs GR8 :$dst), (ins),
2737 "seto\t$dst",
2738 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2739 TB; // GR8 = overflow
2740def SETOm : I<0x90, MRM0m,
2741 (outs), (ins i8mem:$dst),
2742 "seto\t$dst",
2743 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2744 TB; // [mem8] = overflow
2745def SETNOr : I<0x91, MRM0r,
2746 (outs GR8 :$dst), (ins),
2747 "setno\t$dst",
2748 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2749 TB; // GR8 = not overflow
2750def SETNOm : I<0x91, MRM0m,
2751 (outs), (ins i8mem:$dst),
2752 "setno\t$dst",
2753 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2754 TB; // [mem8] = not overflow
Evan Cheng0488db92007-09-25 01:57:46 +00002755} // Uses = [EFLAGS]
2756
Chris Lattner1cca5e32003-08-03 21:54:21 +00002757
2758// Integer comparisons
Evan Cheng24f2ea32007-09-14 21:48:26 +00002759let Defs = [EFLAGS] in {
Chris Lattner3a173df2004-10-03 20:35:00 +00002760def CMP8rr : I<0x38, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002761 (outs), (ins GR8 :$src1, GR8 :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002762 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002763 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002764def CMP16rr : I<0x39, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002765 (outs), (ins GR16:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002766 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002767 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00002768def CMP32rr : I<0x39, MRMDestReg,
Evan Cheng64d80e32007-07-19 01:14:50 +00002769 (outs), (ins GR32:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002770 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002771 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002772def CMP8mr : I<0x38, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002773 (outs), (ins i8mem :$src1, GR8 :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002774 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002775 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2776 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002777def CMP16mr : I<0x39, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002778 (outs), (ins i16mem:$src1, GR16:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002779 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002780 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2781 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00002782def CMP32mr : I<0x39, MRMDestMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002783 (outs), (ins i32mem:$src1, GR32:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002784 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002785 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2786 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002787def CMP8rm : I<0x3A, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002788 (outs), (ins GR8 :$src1, i8mem :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002789 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002790 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2791 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002792def CMP16rm : I<0x3B, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002793 (outs), (ins GR16:$src1, i16mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002794 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002795 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2796 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00002797def CMP32rm : I<0x3B, MRMSrcMem,
Evan Cheng64d80e32007-07-19 01:14:50 +00002798 (outs), (ins GR32:$src1, i32mem:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002799 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002800 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2801 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002802def CMP8ri : Ii8<0x80, MRM7r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002803 (outs), (ins GR8:$src1, i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002804 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002805 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002806def CMP16ri : Ii16<0x81, MRM7r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002807 (outs), (ins GR16:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002808 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002809 [(X86cmp GR16:$src1, imm:$src2),
2810 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00002811def CMP32ri : Ii32<0x81, MRM7r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002812 (outs), (ins GR32:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002813 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002814 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002815def CMP8mi : Ii8 <0x80, MRM7m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002816 (outs), (ins i8mem :$src1, i8imm :$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002817 "cmp{b}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002818 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2819 (implicit EFLAGS)]>;
Chris Lattner3a173df2004-10-03 20:35:00 +00002820def CMP16mi : Ii16<0x81, MRM7m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002821 (outs), (ins i16mem:$src1, i16imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002822 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002823 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2824 (implicit EFLAGS)]>, OpSize;
Chris Lattner3a173df2004-10-03 20:35:00 +00002825def CMP32mi : Ii32<0x81, MRM7m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002826 (outs), (ins i32mem:$src1, i32imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002827 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002828 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2829 (implicit EFLAGS)]>;
Chris Lattner29b4dd02006-03-23 16:13:50 +00002830def CMP16ri8 : Ii8<0x83, MRM7r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002831 (outs), (ins GR16:$src1, i16i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002832 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002833 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2834 (implicit EFLAGS)]>, OpSize;
Chris Lattner29b4dd02006-03-23 16:13:50 +00002835def CMP16mi8 : Ii8<0x83, MRM7m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002836 (outs), (ins i16mem:$src1, i16i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002837 "cmp{w}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002838 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2839 (implicit EFLAGS)]>, OpSize;
Chris Lattner29b4dd02006-03-23 16:13:50 +00002840def CMP32mi8 : Ii8<0x83, MRM7m,
Evan Cheng64d80e32007-07-19 01:14:50 +00002841 (outs), (ins i32mem:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002842 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002843 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2844 (implicit EFLAGS)]>;
Chris Lattner29b4dd02006-03-23 16:13:50 +00002845def CMP32ri8 : Ii8<0x83, MRM7r,
Evan Cheng64d80e32007-07-19 01:14:50 +00002846 (outs), (ins GR32:$src1, i32i8imm:$src2),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002847 "cmp{l}\t{$src2, $src1|$src1, $src2}",
Evan Chenge5f62042007-09-29 00:00:36 +00002848 [(X86cmp GR32:$src1, i32immSExt8:$src2),
Evan Cheng0488db92007-09-25 01:57:46 +00002849 (implicit EFLAGS)]>;
2850} // Defs = [EFLAGS]
2851
Dan Gohmanc7a37d42008-12-23 22:45:23 +00002852// Bit tests.
Dan Gohmanc7a37d42008-12-23 22:45:23 +00002853// TODO: BTC, BTR, and BTS
2854let Defs = [EFLAGS] in {
Dan Gohman0c89b7e2009-01-13 20:32:45 +00002855def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
Dan Gohmanc7a37d42008-12-23 22:45:23 +00002856 "bt{w}\t{$src2, $src1|$src1, $src2}",
2857 [(X86bt GR16:$src1, GR16:$src2),
Chris Lattnerf1e9fd52008-12-25 01:32:49 +00002858 (implicit EFLAGS)]>, OpSize, TB;
Dan Gohman0c89b7e2009-01-13 20:32:45 +00002859def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
Dan Gohmanc7a37d42008-12-23 22:45:23 +00002860 "bt{l}\t{$src2, $src1|$src1, $src2}",
2861 [(X86bt GR32:$src1, GR32:$src2),
Chris Lattnerf1e9fd52008-12-25 01:32:49 +00002862 (implicit EFLAGS)]>, TB;
Dan Gohmanf31408d2009-01-13 23:23:30 +00002863
2864// Unlike with the register+register form, the memory+register form of the
2865// bt instruction does not ignore the high bits of the index. From ISel's
2866// perspective, this is pretty bizarre. Disable these instructions for now.
2867//def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2868// "bt{w}\t{$src2, $src1|$src1, $src2}",
2869// [(X86bt (loadi16 addr:$src1), GR16:$src2),
2870// (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2871//def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2872// "bt{l}\t{$src2, $src1|$src1, $src2}",
2873// [(X86bt (loadi32 addr:$src1), GR32:$src2),
2874// (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
Dan Gohman4afe15b2009-01-13 20:33:23 +00002875
2876def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2877 "bt{w}\t{$src2, $src1|$src1, $src2}",
2878 [(X86bt GR16:$src1, i16immSExt8:$src2),
2879 (implicit EFLAGS)]>, OpSize, TB;
2880def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2881 "bt{l}\t{$src2, $src1|$src1, $src2}",
2882 [(X86bt GR32:$src1, i32immSExt8:$src2),
2883 (implicit EFLAGS)]>, TB;
2884// Note that these instructions don't need FastBTMem because that
2885// only applies when the other operand is in a register. When it's
2886// an immediate, bt is still fast.
2887def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
2888 "bt{w}\t{$src2, $src1|$src1, $src2}",
2889 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
2890 (implicit EFLAGS)]>, OpSize, TB;
2891def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
2892 "bt{l}\t{$src2, $src1|$src1, $src2}",
2893 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
2894 (implicit EFLAGS)]>, TB;
Dan Gohmanc7a37d42008-12-23 22:45:23 +00002895} // Defs = [EFLAGS]
2896
Chris Lattner1cca5e32003-08-03 21:54:21 +00002897// Sign/Zero extenders
Dan Gohman11ba3b12008-07-30 18:09:17 +00002898// Use movsbl intead of movsbw; we don't care about the high 16 bits
2899// of the register here. This has a smaller encoding and avoids a
2900// partial-register update.
Evan Cheng64d80e32007-07-19 01:14:50 +00002901def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
Dan Gohman11ba3b12008-07-30 18:09:17 +00002902 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2903 [(set GR16:$dst, (sext GR8:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002904def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
Dan Gohman11ba3b12008-07-30 18:09:17 +00002905 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2906 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002907def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002908 "movs{bl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002909 [(set GR32:$dst, (sext GR8:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002910def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002911 "movs{bl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002912 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002913def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002914 "movs{wl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002915 [(set GR32:$dst, (sext GR16:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002916def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002917 "movs{wl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002918 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
Alkis Evlogimenosa7be9822004-02-17 09:14:23 +00002919
Dan Gohman11ba3b12008-07-30 18:09:17 +00002920// Use movzbl intead of movzbw; we don't care about the high 16 bits
2921// of the register here. This has a smaller encoding and avoids a
2922// partial-register update.
Evan Cheng64d80e32007-07-19 01:14:50 +00002923def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
Dan Gohman11ba3b12008-07-30 18:09:17 +00002924 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2925 [(set GR16:$dst, (zext GR8:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002926def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
Dan Gohman11ba3b12008-07-30 18:09:17 +00002927 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
2928 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002929def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002930 "movz{bl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002931 [(set GR32:$dst, (zext GR8:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002932def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002933 "movz{bl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002934 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002935def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002936 "movz{wl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002937 [(set GR32:$dst, (zext GR16:$src))]>, TB;
Evan Cheng64d80e32007-07-19 01:14:50 +00002938def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002939 "movz{wl|x}\t{$src, $dst|$dst, $src}",
Evan Cheng069287d2006-05-16 07:21:53 +00002940 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
Evan Cheng7a7e8372005-12-14 02:22:27 +00002941
Dan Gohman21e3dfb2009-04-13 16:09:41 +00002942// These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
2943// except that they use GR32_NOREX for the output operand register class
2944// instead of GR32. This allows them to operate on h registers on x86-64.
2945def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
2946 (outs GR32_NOREX:$dst), (ins GR8:$src),
2947 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
2948 []>, TB;
Dan Gohman78e04d42009-04-30 03:11:48 +00002949let mayLoad = 1 in
Dan Gohman21e3dfb2009-04-13 16:09:41 +00002950def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
2951 (outs GR32_NOREX:$dst), (ins i8mem:$src),
2952 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
2953 []>, TB;
2954
Chris Lattnerba7e7562008-01-10 07:59:24 +00002955let neverHasSideEffects = 1 in {
2956 let Defs = [AX], Uses = [AL] in
2957 def CBW : I<0x98, RawFrm, (outs), (ins),
2958 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
2959 let Defs = [EAX], Uses = [AX] in
2960 def CWDE : I<0x98, RawFrm, (outs), (ins),
2961 "{cwtl|cwde}", []>; // EAX = signext(AX)
Evan Chengf91c1012006-05-31 22:05:11 +00002962
Chris Lattnerba7e7562008-01-10 07:59:24 +00002963 let Defs = [AX,DX], Uses = [AX] in
2964 def CWD : I<0x99, RawFrm, (outs), (ins),
2965 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
2966 let Defs = [EAX,EDX], Uses = [EAX] in
2967 def CDQ : I<0x99, RawFrm, (outs), (ins),
2968 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
2969}
Evan Cheng747a90d2006-02-21 02:24:38 +00002970
Evan Cheng747a90d2006-02-21 02:24:38 +00002971//===----------------------------------------------------------------------===//
2972// Alias Instructions
2973//===----------------------------------------------------------------------===//
2974
2975// Alias instructions that map movr0 to xor.
2976// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
Bill Wendlingbd0879d2008-05-29 01:02:09 +00002977let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +00002978def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002979 "xor{b}\t$dst, $dst",
Evan Cheng069287d2006-05-16 07:21:53 +00002980 [(set GR8:$dst, 0)]>;
Dan Gohman11ba3b12008-07-30 18:09:17 +00002981// Use xorl instead of xorw since we don't care about the high 16 bits,
2982// it's smaller, and it avoids a partial-register update.
Evan Cheng64d80e32007-07-19 01:14:50 +00002983def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
Dan Gohman11ba3b12008-07-30 18:09:17 +00002984 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
2985 [(set GR16:$dst, 0)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00002986def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
Dan Gohmanb1576f52007-07-31 20:11:57 +00002987 "xor{l}\t$dst, $dst",
Evan Cheng069287d2006-05-16 07:21:53 +00002988 [(set GR32:$dst, 0)]>;
Dan Gohman1ab79892007-09-07 21:32:51 +00002989}
Evan Cheng747a90d2006-02-21 02:24:38 +00002990
Evan Cheng510e4782006-01-09 23:10:28 +00002991//===----------------------------------------------------------------------===//
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00002992// Thread Local Storage Instructions
2993//
2994
Rafael Espindola15f1b662009-04-24 12:59:40 +00002995// All calls clobber the non-callee saved registers. ESP is marked as
2996// a use to prevent stack-pointer assignments that appear immediately
2997// before calls from potentially appearing dead.
2998let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
2999 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3000 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3001 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3002 Uses = [ESP, EBX] in
Rafael Espindola2ee3db32009-04-17 14:35:58 +00003003def TLS_addr32 : I<0, Pseudo, (outs), (ins i32imm:$sym),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003004 "leal\t${sym:mem}(,%ebx,1), %eax; "
3005 "call\t___tls_get_addr@PLT",
Rafael Espindola2ee3db32009-04-17 14:35:58 +00003006 [(X86tlsaddr tglobaltlsaddr:$sym)]>,
3007 Requires<[In32BitMode]>;
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00003008
Nate Begeman51a04372009-01-26 01:24:32 +00003009let AddedComplexity = 5 in
3010def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3011 "movl\t%gs:$src, $dst",
3012 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3013
Chris Lattner1777d0c2009-05-05 18:52:19 +00003014let AddedComplexity = 5 in
3015def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3016 "movl\t%fs:$src, $dst",
3017 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3018
Lauro Ramos Venanciob3a04172007-04-20 21:38:10 +00003019//===----------------------------------------------------------------------===//
Evan Cheng3c992d22006-03-07 02:02:57 +00003020// DWARF Pseudo Instructions
3021//
3022
Evan Cheng64d80e32007-07-19 01:14:50 +00003023def DWARF_LOC : I<0, Pseudo, (outs),
3024 (ins i32imm:$line, i32imm:$col, i32imm:$file),
Dan Gohman6b5766e2007-09-24 19:25:06 +00003025 ".loc\t${file:debug} ${line:debug} ${col:debug}",
Evan Cheng3c992d22006-03-07 02:02:57 +00003026 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3027 (i32 imm:$file))]>;
3028
Evan Cheng3c992d22006-03-07 02:02:57 +00003029//===----------------------------------------------------------------------===//
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003030// EH Pseudo Instructions
3031//
3032let isTerminator = 1, isReturn = 1, isBarrier = 1,
Evan Chengffbacca2007-07-21 00:34:19 +00003033 hasCtrlDep = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +00003034def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
Dan Gohmanb1576f52007-07-31 20:11:57 +00003035 "ret\t#eh_return, addr: $addr",
Anton Korobeynikov2365f512007-07-14 14:06:15 +00003036 [(X86ehret GR32:$addr)]>;
3037
3038}
3039
3040//===----------------------------------------------------------------------===//
Andrew Lenharthab0b9492008-02-21 06:45:13 +00003041// Atomic support
3042//
Andrew Lenharthea7da502008-03-01 13:37:02 +00003043
Evan Chengbb6939d2008-04-19 01:20:30 +00003044// Atomic swap. These are just normal xchg instructions. But since a memory
3045// operand is referenced, the atomicity is ensured.
Dan Gohman165660e2008-08-06 15:52:50 +00003046let Constraints = "$val = $dst" in {
Evan Chengbb6939d2008-04-19 01:20:30 +00003047def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3048 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3049 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3050def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3051 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3052 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3053 OpSize;
3054def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3055 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3056 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3057}
3058
Evan Cheng7e032802008-04-18 20:55:36 +00003059// Atomic compare and swap.
Andrew Lenharth26ed8692008-03-01 21:52:34 +00003060let Defs = [EAX, EFLAGS], Uses = [EAX] in {
Evan Cheng7e032802008-04-18 20:55:36 +00003061def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003062 "lock\n\t"
3063 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng32967d22008-03-04 03:20:06 +00003064 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
Andrew Lenharthea7da502008-03-01 13:37:02 +00003065}
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003066let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
Anton Korobeynikovf88a6fa2008-07-22 16:22:48 +00003067def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003068 "lock\n\t"
3069 "cmpxchg8b\t$ptr",
Andrew Lenharthd19189e2008-03-05 01:15:49 +00003070 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3071}
Andrew Lenharth26ed8692008-03-01 21:52:34 +00003072
3073let Defs = [AX, EFLAGS], Uses = [AX] in {
Evan Cheng7e032802008-04-18 20:55:36 +00003074def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003075 "lock\n\t"
3076 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng32967d22008-03-04 03:20:06 +00003077 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
Andrew Lenharthea7da502008-03-01 13:37:02 +00003078}
Andrew Lenharth26ed8692008-03-01 21:52:34 +00003079let Defs = [AL, EFLAGS], Uses = [AL] in {
Evan Cheng7e032802008-04-18 20:55:36 +00003080def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003081 "lock\n\t"
3082 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
Evan Cheng32967d22008-03-04 03:20:06 +00003083 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
Andrew Lenharthea7da502008-03-01 13:37:02 +00003084}
3085
Evan Cheng7e032802008-04-18 20:55:36 +00003086// Atomic exchange and add
3087let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3088def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003089 "lock\n\t"
3090 "xadd{l}\t{$val, $ptr|$ptr, $val}",
Mon P Wang28873102008-06-25 08:15:39 +00003091 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
Evan Cheng7e032802008-04-18 20:55:36 +00003092 TB, LOCK;
3093def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003094 "lock\n\t"
3095 "xadd{w}\t{$val, $ptr|$ptr, $val}",
Mon P Wang28873102008-06-25 08:15:39 +00003096 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
Evan Cheng7e032802008-04-18 20:55:36 +00003097 TB, OpSize, LOCK;
3098def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
Dan Gohman4d47b9b2009-04-27 15:13:28 +00003099 "lock\n\t"
3100 "xadd{b}\t{$val, $ptr|$ptr, $val}",
Mon P Wang28873102008-06-25 08:15:39 +00003101 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
Evan Cheng7e032802008-04-18 20:55:36 +00003102 TB, LOCK;
Andrew Lenharthea7da502008-03-01 13:37:02 +00003103}
3104
Mon P Wang28873102008-06-25 08:15:39 +00003105// Atomic exchange, and, or, xor
Mon P Wang63307c32008-05-05 19:05:59 +00003106let Constraints = "$val = $dst", Defs = [EFLAGS],
3107 usesCustomDAGSchedInserter = 1 in {
Dan Gohman9499b712008-05-12 20:22:45 +00003108def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003109 "#ATOMAND32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003110 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
Dan Gohman9499b712008-05-12 20:22:45 +00003111def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003112 "#ATOMOR32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003113 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
Dan Gohman9499b712008-05-12 20:22:45 +00003114def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003115 "#ATOMXOR32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003116 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
Andrew Lenharth507a58a2008-06-14 05:48:15 +00003117def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003118 "#ATOMNAND32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003119 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
Dan Gohman9499b712008-05-12 20:22:45 +00003120def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003121 "#ATOMMIN32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003122 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
Dan Gohman9499b712008-05-12 20:22:45 +00003123def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003124 "#ATOMMAX32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003125 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
Dan Gohman9499b712008-05-12 20:22:45 +00003126def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003127 "#ATOMUMIN32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003128 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
Dan Gohman9499b712008-05-12 20:22:45 +00003129def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003130 "#ATOMUMAX32 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003131 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003132
3133def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003134 "#ATOMAND16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003135 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003136def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003137 "#ATOMOR16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003138 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003139def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003140 "#ATOMXOR16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003141 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003142def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003143 "#ATOMNAND16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003144 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003145def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003146 "#ATOMMIN16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003147 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003148def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003149 "#ATOMMAX16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003150 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003151def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003152 "#ATOMUMIN16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003153 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003154def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003155 "#ATOMUMAX16 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003156 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003157
3158def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003159 "#ATOMAND8 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003160 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003161def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003162 "#ATOMOR8 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003163 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003164def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003165 "#ATOMXOR8 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003166 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
Dale Johannesen140be2d2008-08-19 18:47:28 +00003167def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003168 "#ATOMNAND8 PSEUDO!",
Dale Johannesene00a8a22008-08-28 02:44:49 +00003169 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
Mon P Wang63307c32008-05-05 19:05:59 +00003170}
3171
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003172let Constraints = "$val1 = $dst1, $val2 = $dst2",
3173 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3174 Uses = [EAX, EBX, ECX, EDX],
Dale Johannesen1b54c7f2008-10-03 19:41:08 +00003175 mayLoad = 1, mayStore = 1,
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003176 usesCustomDAGSchedInserter = 1 in {
3177def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3178 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003179 "#ATOMAND6432 PSEUDO!", []>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003180def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3181 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003182 "#ATOMOR6432 PSEUDO!", []>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003183def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3184 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003185 "#ATOMXOR6432 PSEUDO!", []>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003186def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3187 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003188 "#ATOMNAND6432 PSEUDO!", []>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003189def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3190 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003191 "#ATOMADD6432 PSEUDO!", []>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003192def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3193 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003194 "#ATOMSUB6432 PSEUDO!", []>;
Dale Johannesen880ae362008-10-03 22:25:52 +00003195def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3196 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
Nick Lewycky6ecf5ce2008-12-07 03:49:52 +00003197 "#ATOMSWAP6432 PSEUDO!", []>;
Dale Johannesen48c1bc22008-10-02 18:53:47 +00003198}
3199
Andrew Lenharthab0b9492008-02-21 06:45:13 +00003200//===----------------------------------------------------------------------===//
Evan Cheng510e4782006-01-09 23:10:28 +00003201// Non-Instruction Patterns
3202//===----------------------------------------------------------------------===//
3203
Bill Wendling056292f2008-09-16 21:48:12 +00003204// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
Evan Cheng71fb8342006-02-25 10:02:21 +00003205def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
Nate Begeman37efe672006-04-22 18:53:45 +00003206def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
Nate Begeman6795ebb2008-04-12 00:47:57 +00003207def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
Evan Cheng71fb8342006-02-25 10:02:21 +00003208def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3209def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3210
Evan Cheng069287d2006-05-16 07:21:53 +00003211def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3212 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3213def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3214 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3215def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3216 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3217def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3218 (ADD32ri GR32:$src1, texternalsym:$src2)>;
Evan Cheng71fb8342006-02-25 10:02:21 +00003219
Evan Chengfc8feb12006-05-19 07:30:36 +00003220def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
Evan Cheng71fb8342006-02-25 10:02:21 +00003221 (MOV32mi addr:$dst, tglobaladdr:$src)>;
Evan Chengfc8feb12006-05-19 07:30:36 +00003222def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
Evan Cheng71fb8342006-02-25 10:02:21 +00003223 (MOV32mi addr:$dst, texternalsym:$src)>;
3224
Evan Cheng510e4782006-01-09 23:10:28 +00003225// Calls
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003226// tailcall stuff
Evan Cheng069287d2006-05-16 07:21:53 +00003227def : Pat<(X86tailcall GR32:$dst),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003228 (TAILCALL)>;
Evan Chengfea89c12006-04-27 08:40:39 +00003229
Evan Cheng25ab6902006-09-08 06:48:29 +00003230def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003231 (TAILCALL)>;
Evan Cheng25ab6902006-09-08 06:48:29 +00003232def : Pat<(X86tailcall (i32 texternalsym:$dst)),
Arnold Schwaighoferc85e1712007-10-11 19:40:01 +00003233 (TAILCALL)>;
3234
3235def : Pat<(X86tcret GR32:$dst, imm:$off),
3236 (TCRETURNri GR32:$dst, imm:$off)>;
3237
3238def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3239 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3240
3241def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3242 (TCRETURNdi texternalsym:$dst, imm:$off)>;
Evan Chengfea89c12006-04-27 08:40:39 +00003243
Evan Cheng25ab6902006-09-08 06:48:29 +00003244def : Pat<(X86call (i32 tglobaladdr:$dst)),
Evan Cheng510e4782006-01-09 23:10:28 +00003245 (CALLpcrel32 tglobaladdr:$dst)>;
Evan Cheng25ab6902006-09-08 06:48:29 +00003246def : Pat<(X86call (i32 texternalsym:$dst)),
Evan Cheng8700e142006-01-11 06:09:51 +00003247 (CALLpcrel32 texternalsym:$dst)>;
Evan Cheng510e4782006-01-09 23:10:28 +00003248
3249// X86 specific add which produces a flag.
Evan Cheng069287d2006-05-16 07:21:53 +00003250def : Pat<(addc GR32:$src1, GR32:$src2),
3251 (ADD32rr GR32:$src1, GR32:$src2)>;
3252def : Pat<(addc GR32:$src1, (load addr:$src2)),
3253 (ADD32rm GR32:$src1, addr:$src2)>;
3254def : Pat<(addc GR32:$src1, imm:$src2),
3255 (ADD32ri GR32:$src1, imm:$src2)>;
3256def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3257 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
Evan Cheng510e4782006-01-09 23:10:28 +00003258
Evan Cheng069287d2006-05-16 07:21:53 +00003259def : Pat<(subc GR32:$src1, GR32:$src2),
3260 (SUB32rr GR32:$src1, GR32:$src2)>;
3261def : Pat<(subc GR32:$src1, (load addr:$src2)),
3262 (SUB32rm GR32:$src1, addr:$src2)>;
3263def : Pat<(subc GR32:$src1, imm:$src2),
3264 (SUB32ri GR32:$src1, imm:$src2)>;
3265def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3266 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
Evan Cheng510e4782006-01-09 23:10:28 +00003267
Chris Lattnerffc0b262006-09-07 20:33:45 +00003268// Comparisons.
3269
3270// TEST R,R is smaller than CMP R,0
Evan Chenge5f62042007-09-29 00:00:36 +00003271def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
Chris Lattnerffc0b262006-09-07 20:33:45 +00003272 (TEST8rr GR8:$src1, GR8:$src1)>;
Evan Chenge5f62042007-09-29 00:00:36 +00003273def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
Chris Lattnerffc0b262006-09-07 20:33:45 +00003274 (TEST16rr GR16:$src1, GR16:$src1)>;
Evan Chenge5f62042007-09-29 00:00:36 +00003275def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
Chris Lattnerffc0b262006-09-07 20:33:45 +00003276 (TEST32rr GR32:$src1, GR32:$src1)>;
3277
Dan Gohmanfbb74862009-01-07 01:00:24 +00003278// Conditional moves with folded loads with operands swapped and conditions
3279// inverted.
3280def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3281 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3282def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3283 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3284def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3285 (CMOVB16rm GR16:$src2, addr:$src1)>;
3286def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3287 (CMOVB32rm GR32:$src2, addr:$src1)>;
3288def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3289 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3290def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3291 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3292def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3293 (CMOVE16rm GR16:$src2, addr:$src1)>;
3294def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3295 (CMOVE32rm GR32:$src2, addr:$src1)>;
3296def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3297 (CMOVA16rm GR16:$src2, addr:$src1)>;
3298def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3299 (CMOVA32rm GR32:$src2, addr:$src1)>;
3300def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3301 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3302def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3303 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3304def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3305 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3306def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3307 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3308def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3309 (CMOVL16rm GR16:$src2, addr:$src1)>;
3310def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3311 (CMOVL32rm GR32:$src2, addr:$src1)>;
3312def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3313 (CMOVG16rm GR16:$src2, addr:$src1)>;
3314def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3315 (CMOVG32rm GR32:$src2, addr:$src1)>;
3316def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3317 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3318def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3319 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3320def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3321 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3322def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3323 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3324def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3325 (CMOVP16rm GR16:$src2, addr:$src1)>;
3326def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3327 (CMOVP32rm GR32:$src2, addr:$src1)>;
3328def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3329 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3330def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3331 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3332def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3333 (CMOVS16rm GR16:$src2, addr:$src1)>;
3334def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3335 (CMOVS32rm GR32:$src2, addr:$src1)>;
3336def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3337 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3338def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3339 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3340def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3341 (CMOVO16rm GR16:$src2, addr:$src1)>;
3342def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3343 (CMOVO32rm GR32:$src2, addr:$src1)>;
3344
Duncan Sandsf9c98e62008-01-23 20:39:46 +00003345// zextload bool -> zextload byte
Evan Chenge5d93432006-01-17 07:02:46 +00003346def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
Evan Cheng510e4782006-01-09 23:10:28 +00003347def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3348def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3349
3350// extload bool -> extload byte
Evan Cheng47137242006-05-05 08:23:07 +00003351def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
Bill Wendling449416d2008-08-22 20:51:05 +00003352def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3353 Requires<[In32BitMode]>;
Evan Cheng47137242006-05-05 08:23:07 +00003354def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
Bill Wendling449416d2008-08-22 20:51:05 +00003355def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3356 Requires<[In32BitMode]>;
Evan Cheng47137242006-05-05 08:23:07 +00003357def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3358def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
Evan Cheng510e4782006-01-09 23:10:28 +00003359
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003360// anyext
Bill Wendling449416d2008-08-22 20:51:05 +00003361def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3362 Requires<[In32BitMode]>;
3363def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3364 Requires<[In32BitMode]>;
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003365def : Pat<(i32 (anyext GR16:$src)),
3366 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
Evan Cheng510e4782006-01-09 23:10:28 +00003367
Evan Cheng1314b002007-12-13 00:43:27 +00003368// (and (i32 load), 255) -> (zextload i8)
Evan Chengd47e0b62008-09-29 17:26:18 +00003369def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3370 (MOVZX32rm8 addr:$src)>;
3371def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3372 (MOVZX32rm16 addr:$src)>;
Evan Cheng1314b002007-12-13 00:43:27 +00003373
Evan Chengcfa260b2006-01-06 02:31:59 +00003374//===----------------------------------------------------------------------===//
3375// Some peepholes
3376//===----------------------------------------------------------------------===//
3377
Dan Gohman63f97202008-10-17 01:33:43 +00003378// Odd encoding trick: -128 fits into an 8-bit immediate field while
3379// +128 doesn't, so in this special case use a sub instead of an add.
3380def : Pat<(add GR16:$src1, 128),
3381 (SUB16ri8 GR16:$src1, -128)>;
3382def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3383 (SUB16mi8 addr:$dst, -128)>;
3384def : Pat<(add GR32:$src1, 128),
3385 (SUB32ri8 GR32:$src1, -128)>;
3386def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3387 (SUB32mi8 addr:$dst, -128)>;
3388
Dan Gohman11ba3b12008-07-30 18:09:17 +00003389// r & (2^16-1) ==> movz
3390def : Pat<(and GR32:$src1, 0xffff),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003391 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
Dan Gohman8a1510d2008-08-06 18:27:21 +00003392// r & (2^8-1) ==> movz
3393def : Pat<(and GR32:$src1, 0xff),
Dan Gohman62417622009-04-27 16:33:14 +00003394 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003395 x86_subreg_8bit))>,
Dan Gohman8a1510d2008-08-06 18:27:21 +00003396 Requires<[In32BitMode]>;
3397// r & (2^8-1) ==> movz
3398def : Pat<(and GR16:$src1, 0xff),
Dan Gohman62417622009-04-27 16:33:14 +00003399 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003400 x86_subreg_8bit))>,
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003401 Requires<[In32BitMode]>;
3402
3403// sext_inreg patterns
3404def : Pat<(sext_inreg GR32:$src, i16),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003405 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003406def : Pat<(sext_inreg GR32:$src, i8),
Dan Gohman62417622009-04-27 16:33:14 +00003407 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003408 x86_subreg_8bit))>,
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003409 Requires<[In32BitMode]>;
3410def : Pat<(sext_inreg GR16:$src, i8),
Dan Gohman62417622009-04-27 16:33:14 +00003411 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003412 x86_subreg_8bit))>,
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003413 Requires<[In32BitMode]>;
3414
3415// trunc patterns
3416def : Pat<(i16 (trunc GR32:$src)),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003417 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003418def : Pat<(i8 (trunc GR32:$src)),
Dan Gohman62417622009-04-27 16:33:14 +00003419 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003420 x86_subreg_8bit)>,
Dan Gohman0bfa1bf2008-08-20 21:27:32 +00003421 Requires<[In32BitMode]>;
3422def : Pat<(i8 (trunc GR16:$src)),
Dan Gohman62417622009-04-27 16:33:14 +00003423 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003424 x86_subreg_8bit)>,
3425 Requires<[In32BitMode]>;
3426
3427// h-register tricks
3428def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
Dan Gohman62417622009-04-27 16:33:14 +00003429 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003430 x86_subreg_8bit_hi)>,
3431 Requires<[In32BitMode]>;
3432def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
Dan Gohman62417622009-04-27 16:33:14 +00003433 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003434 x86_subreg_8bit_hi)>,
3435 Requires<[In32BitMode]>;
3436def : Pat<(srl_su GR16:$src, (i8 8)),
3437 (EXTRACT_SUBREG
3438 (MOVZX32rr8
Dan Gohman62417622009-04-27 16:33:14 +00003439 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003440 x86_subreg_8bit_hi)),
3441 x86_subreg_16bit)>,
3442 Requires<[In32BitMode]>;
3443def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
Dan Gohman62417622009-04-27 16:33:14 +00003444 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
Dan Gohman21e3dfb2009-04-13 16:09:41 +00003445 x86_subreg_8bit_hi))>,
Dan Gohman8a1510d2008-08-06 18:27:21 +00003446 Requires<[In32BitMode]>;
Dan Gohman11ba3b12008-07-30 18:09:17 +00003447
Evan Chengcfa260b2006-01-06 02:31:59 +00003448// (shl x, 1) ==> (add x, x)
Evan Cheng069287d2006-05-16 07:21:53 +00003449def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3450def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3451def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
Evan Cheng68b951a2006-01-19 01:56:29 +00003452
Evan Chengeb9f8922008-08-30 02:03:58 +00003453// (shl x (and y, 31)) ==> (shl x, y)
3454def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3455 (SHL8rCL GR8:$src1)>;
3456def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3457 (SHL16rCL GR16:$src1)>;
3458def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3459 (SHL32rCL GR32:$src1)>;
3460def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3461 (SHL8mCL addr:$dst)>;
3462def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3463 (SHL16mCL addr:$dst)>;
3464def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3465 (SHL32mCL addr:$dst)>;
3466
3467def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3468 (SHR8rCL GR8:$src1)>;
3469def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3470 (SHR16rCL GR16:$src1)>;
3471def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3472 (SHR32rCL GR32:$src1)>;
3473def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3474 (SHR8mCL addr:$dst)>;
3475def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3476 (SHR16mCL addr:$dst)>;
3477def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3478 (SHR32mCL addr:$dst)>;
3479
3480def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3481 (SAR8rCL GR8:$src1)>;
3482def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3483 (SAR16rCL GR16:$src1)>;
3484def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3485 (SAR32rCL GR32:$src1)>;
3486def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3487 (SAR8mCL addr:$dst)>;
3488def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3489 (SAR16mCL addr:$dst)>;
3490def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3491 (SAR32mCL addr:$dst)>;
3492
Evan Cheng956044c2006-01-19 23:26:24 +00003493// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
Evan Cheng069287d2006-05-16 07:21:53 +00003494def : Pat<(or (srl GR32:$src1, CL:$amt),
3495 (shl GR32:$src2, (sub 32, CL:$amt))),
3496 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
Evan Cheng68b951a2006-01-19 01:56:29 +00003497
Evan Cheng21d54432006-01-20 01:13:30 +00003498def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
Evan Cheng069287d2006-05-16 07:21:53 +00003499 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3500 (SHRD32mrCL addr:$dst, GR32:$src2)>;
Evan Cheng21d54432006-01-20 01:13:30 +00003501
Dan Gohman74feef22008-10-17 01:23:35 +00003502def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3503 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3504 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3505
3506def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3507 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3508 addr:$dst),
3509 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3510
3511def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3512 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3513
3514def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3515 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3516 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3517
Evan Cheng956044c2006-01-19 23:26:24 +00003518// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
Evan Cheng069287d2006-05-16 07:21:53 +00003519def : Pat<(or (shl GR32:$src1, CL:$amt),
3520 (srl GR32:$src2, (sub 32, CL:$amt))),
3521 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
Evan Cheng956044c2006-01-19 23:26:24 +00003522
Evan Cheng21d54432006-01-20 01:13:30 +00003523def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
Evan Cheng069287d2006-05-16 07:21:53 +00003524 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3525 (SHLD32mrCL addr:$dst, GR32:$src2)>;
Evan Cheng21d54432006-01-20 01:13:30 +00003526
Dan Gohman74feef22008-10-17 01:23:35 +00003527def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3528 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3529 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3530
3531def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3532 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3533 addr:$dst),
3534 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3535
3536def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3537 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3538
3539def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3540 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3541 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3542
Evan Cheng956044c2006-01-19 23:26:24 +00003543// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
Evan Cheng069287d2006-05-16 07:21:53 +00003544def : Pat<(or (srl GR16:$src1, CL:$amt),
3545 (shl GR16:$src2, (sub 16, CL:$amt))),
3546 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
Evan Cheng956044c2006-01-19 23:26:24 +00003547
Evan Cheng21d54432006-01-20 01:13:30 +00003548def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
Evan Cheng069287d2006-05-16 07:21:53 +00003549 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3550 (SHRD16mrCL addr:$dst, GR16:$src2)>;
Evan Cheng21d54432006-01-20 01:13:30 +00003551
Dan Gohman74feef22008-10-17 01:23:35 +00003552def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3553 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3554 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3555
3556def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3557 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3558 addr:$dst),
3559 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3560
3561def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3562 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3563
3564def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3565 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3566 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3567
Evan Cheng956044c2006-01-19 23:26:24 +00003568// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
Evan Cheng069287d2006-05-16 07:21:53 +00003569def : Pat<(or (shl GR16:$src1, CL:$amt),
3570 (srl GR16:$src2, (sub 16, CL:$amt))),
3571 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
Evan Cheng21d54432006-01-20 01:13:30 +00003572
3573def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
Evan Cheng069287d2006-05-16 07:21:53 +00003574 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3575 (SHLD16mrCL addr:$dst, GR16:$src2)>;
Evan Cheng4e4c71e2006-02-21 20:00:20 +00003576
Dan Gohman74feef22008-10-17 01:23:35 +00003577def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3578 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3579 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3580
3581def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3582 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3583 addr:$dst),
3584 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3585
3586def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3587 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3588
3589def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3590 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3591 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3592
Evan Cheng4e4c71e2006-02-21 20:00:20 +00003593//===----------------------------------------------------------------------===//
Dan Gohman076aee32009-03-04 19:44:21 +00003594// EFLAGS-defining Patterns
Bill Wendlingd350e022008-12-12 21:15:41 +00003595//===----------------------------------------------------------------------===//
3596
Dan Gohman076aee32009-03-04 19:44:21 +00003597// Register-Register Addition with EFLAGS result
3598def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003599 (implicit EFLAGS)),
3600 (ADD8rr GR8:$src1, GR8:$src2)>;
3601
Dan Gohman076aee32009-03-04 19:44:21 +00003602// Register-Register Addition with EFLAGS result
3603def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003604 (implicit EFLAGS)),
3605 (ADD16rr GR16:$src1, GR16:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003606def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003607 (implicit EFLAGS)),
3608 (ADD32rr GR32:$src1, GR32:$src2)>;
3609
Dan Gohman076aee32009-03-04 19:44:21 +00003610// Register-Memory Addition with EFLAGS result
3611def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003612 (implicit EFLAGS)),
3613 (ADD8rm GR8:$src1, addr:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003614def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003615 (implicit EFLAGS)),
3616 (ADD16rm GR16:$src1, addr:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003617def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003618 (implicit EFLAGS)),
3619 (ADD32rm GR32:$src1, addr:$src2)>;
3620
Dan Gohman076aee32009-03-04 19:44:21 +00003621// Register-Integer Addition with EFLAGS result
3622def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003623 (implicit EFLAGS)),
3624 (ADD8ri GR8:$src1, imm:$src2)>;
3625
Dan Gohman076aee32009-03-04 19:44:21 +00003626// Register-Integer Addition with EFLAGS result
3627def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003628 (implicit EFLAGS)),
3629 (ADD16ri GR16:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003630def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003631 (implicit EFLAGS)),
3632 (ADD32ri GR32:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003633def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003634 (implicit EFLAGS)),
3635 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003636def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003637 (implicit EFLAGS)),
3638 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3639
Dan Gohman076aee32009-03-04 19:44:21 +00003640// Memory-Register Addition with EFLAGS result
3641def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003642 addr:$dst),
3643 (implicit EFLAGS)),
3644 (ADD8mr addr:$dst, GR8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003645def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003646 addr:$dst),
3647 (implicit EFLAGS)),
3648 (ADD16mr addr:$dst, GR16:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003649def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003650 addr:$dst),
3651 (implicit EFLAGS)),
3652 (ADD32mr addr:$dst, GR32:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003653def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003654 addr:$dst),
3655 (implicit EFLAGS)),
3656 (ADD8mi addr:$dst, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003657def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003658 addr:$dst),
3659 (implicit EFLAGS)),
3660 (ADD16mi addr:$dst, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003661def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003662 addr:$dst),
3663 (implicit EFLAGS)),
3664 (ADD32mi addr:$dst, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003665def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003666 addr:$dst),
3667 (implicit EFLAGS)),
3668 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003669def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003670 addr:$dst),
3671 (implicit EFLAGS)),
3672 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3673
Dan Gohman076aee32009-03-04 19:44:21 +00003674// Register-Register Subtraction with EFLAGS result
3675def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003676 (implicit EFLAGS)),
3677 (SUB8rr GR8:$src1, GR8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003678def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003679 (implicit EFLAGS)),
3680 (SUB16rr GR16:$src1, GR16:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003681def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003682 (implicit EFLAGS)),
3683 (SUB32rr GR32:$src1, GR32:$src2)>;
3684
Dan Gohman076aee32009-03-04 19:44:21 +00003685// Register-Memory Subtraction with EFLAGS result
3686def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003687 (implicit EFLAGS)),
3688 (SUB8rm GR8:$src1, addr:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003689def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003690 (implicit EFLAGS)),
3691 (SUB16rm GR16:$src1, addr:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003692def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003693 (implicit EFLAGS)),
3694 (SUB32rm GR32:$src1, addr:$src2)>;
3695
Dan Gohman076aee32009-03-04 19:44:21 +00003696// Register-Integer Subtraction with EFLAGS result
3697def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003698 (implicit EFLAGS)),
3699 (SUB8ri GR8:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003700def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003701 (implicit EFLAGS)),
3702 (SUB16ri GR16:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003703def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003704 (implicit EFLAGS)),
3705 (SUB32ri GR32:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003706def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003707 (implicit EFLAGS)),
3708 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003709def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003710 (implicit EFLAGS)),
3711 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3712
Dan Gohman076aee32009-03-04 19:44:21 +00003713// Memory-Register Subtraction with EFLAGS result
3714def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003715 addr:$dst),
3716 (implicit EFLAGS)),
3717 (SUB8mr addr:$dst, GR8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003718def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003719 addr:$dst),
3720 (implicit EFLAGS)),
3721 (SUB16mr addr:$dst, GR16:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003722def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003723 addr:$dst),
3724 (implicit EFLAGS)),
3725 (SUB32mr addr:$dst, GR32:$src2)>;
3726
Dan Gohman076aee32009-03-04 19:44:21 +00003727// Memory-Integer Subtraction with EFLAGS result
3728def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003729 addr:$dst),
3730 (implicit EFLAGS)),
3731 (SUB8mi addr:$dst, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003732def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003733 addr:$dst),
3734 (implicit EFLAGS)),
3735 (SUB16mi addr:$dst, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003736def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003737 addr:$dst),
3738 (implicit EFLAGS)),
3739 (SUB32mi addr:$dst, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003740def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003741 addr:$dst),
3742 (implicit EFLAGS)),
3743 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003744def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003745 addr:$dst),
3746 (implicit EFLAGS)),
3747 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3748
3749
Dan Gohman076aee32009-03-04 19:44:21 +00003750// Register-Register Signed Integer Multiply with EFLAGS result
3751def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003752 (implicit EFLAGS)),
3753 (IMUL16rr GR16:$src1, GR16:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003754def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003755 (implicit EFLAGS)),
3756 (IMUL32rr GR32:$src1, GR32:$src2)>;
3757
Dan Gohman076aee32009-03-04 19:44:21 +00003758// Register-Memory Signed Integer Multiply with EFLAGS result
3759def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003760 (implicit EFLAGS)),
3761 (IMUL16rm GR16:$src1, addr:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003762def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
Bill Wendlingd350e022008-12-12 21:15:41 +00003763 (implicit EFLAGS)),
3764 (IMUL32rm GR32:$src1, addr:$src2)>;
3765
Dan Gohman076aee32009-03-04 19:44:21 +00003766// Register-Integer Signed Integer Multiply with EFLAGS result
3767def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003768 (implicit EFLAGS)),
3769 (IMUL16rri GR16:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003770def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003771 (implicit EFLAGS)),
3772 (IMUL32rri GR32:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003773def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003774 (implicit EFLAGS)),
3775 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003776def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003777 (implicit EFLAGS)),
3778 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3779
Dan Gohman076aee32009-03-04 19:44:21 +00003780// Memory-Integer Signed Integer Multiply with EFLAGS result
3781def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003782 (implicit EFLAGS)),
3783 (IMUL16rmi addr:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003784def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003785 (implicit EFLAGS)),
3786 (IMUL32rmi addr:$src1, imm:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003787def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003788 (implicit EFLAGS)),
3789 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
Dan Gohman076aee32009-03-04 19:44:21 +00003790def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
Bill Wendlingd350e022008-12-12 21:15:41 +00003791 (implicit EFLAGS)),
3792 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3793
Dan Gohman076aee32009-03-04 19:44:21 +00003794// Optimize multiply by 2 with EFLAGS result.
Evan Cheng6a86bd72009-01-27 03:30:42 +00003795let AddedComplexity = 2 in {
Dan Gohman076aee32009-03-04 19:44:21 +00003796def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
Evan Cheng6a86bd72009-01-27 03:30:42 +00003797 (implicit EFLAGS)),
3798 (ADD16rr GR16:$src1, GR16:$src1)>;
3799
Dan Gohman076aee32009-03-04 19:44:21 +00003800def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
Evan Cheng6a86bd72009-01-27 03:30:42 +00003801 (implicit EFLAGS)),
3802 (ADD32rr GR32:$src1, GR32:$src1)>;
3803}
3804
Dan Gohman076aee32009-03-04 19:44:21 +00003805// INC and DEC with EFLAGS result. Note that these do not set CF.
3806def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
3807 (INC8r GR8:$src)>;
3808def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
3809 (implicit EFLAGS)),
3810 (INC8m addr:$dst)>;
3811def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
3812 (DEC8r GR8:$src)>;
3813def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
3814 (implicit EFLAGS)),
3815 (DEC8m addr:$dst)>;
3816
3817def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003818 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003819def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
3820 (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003821 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003822def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003823 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003824def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
3825 (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003826 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003827
3828def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003829 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003830def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
3831 (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003832 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003833def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003834 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003835def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
3836 (implicit EFLAGS)),
Dan Gohman1f4af262009-03-05 21:32:23 +00003837 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
Dan Gohman076aee32009-03-04 19:44:21 +00003838
Nate Begeman9008ca62009-04-27 18:41:29 +00003839
Bill Wendlingd350e022008-12-12 21:15:41 +00003840//===----------------------------------------------------------------------===//
Evan Cheng4e4c71e2006-02-21 20:00:20 +00003841// Floating Point Stack Support
3842//===----------------------------------------------------------------------===//
3843
3844include "X86InstrFPStack.td"
3845
3846//===----------------------------------------------------------------------===//
Evan Chengc64a1a92007-07-31 08:04:03 +00003847// X86-64 Support
3848//===----------------------------------------------------------------------===//
3849
Chris Lattner36fe6d22008-01-10 05:50:42 +00003850include "X86Instr64bit.td"
Evan Chengc64a1a92007-07-31 08:04:03 +00003851
3852//===----------------------------------------------------------------------===//
Evan Cheng4e4c71e2006-02-21 20:00:20 +00003853// XMM Floating point support (requires SSE / SSE2)
3854//===----------------------------------------------------------------------===//
3855
3856include "X86InstrSSE.td"
Evan Cheng80f54042008-04-25 18:19:54 +00003857
3858//===----------------------------------------------------------------------===//
3859// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3860//===----------------------------------------------------------------------===//
3861
3862include "X86InstrMMX.td"