Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// |
Michael J. Spencer | 9a0bac4 | 2011-04-14 14:33:36 +0000 | [diff] [blame] | 2 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Michael J. Spencer | 9a0bac4 | 2011-04-14 14:33:36 +0000 | [diff] [blame] | 7 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 7a2bdde | 2011-04-15 05:18:47 +0000 | [diff] [blame] | 10 | // This is a target description file for the Intel i386 architecture, referred to |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 11 | // here as the "X86" architecture. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 15 | // Get the target-independent interfaces which we are implementing... |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 16 | // |
Evan Cheng | 027fdbe | 2008-11-24 07:34:46 +0000 | [diff] [blame] | 17 | include "llvm/Target/Target.td" |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 18 | |
| 19 | //===----------------------------------------------------------------------===// |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 20 | // X86 Subtarget features. |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 21 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7008416 | 2009-09-02 05:53:04 +0000 | [diff] [blame] | 22 | |
| 23 | def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", |
| 24 | "Enable conditional move instructions">; |
| 25 | |
Benjamin Kramer | 1292c22 | 2010-12-04 20:32:23 +0000 | [diff] [blame] | 26 | def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", |
| 27 | "Support POPCNT instruction">; |
| 28 | |
David Greene | 95eb2ee | 2010-01-11 16:29:42 +0000 | [diff] [blame] | 29 | |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 30 | def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", |
| 31 | "Enable MMX instructions">; |
| 32 | def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", |
| 33 | "Enable SSE instructions", |
Chris Lattner | 7008416 | 2009-09-02 05:53:04 +0000 | [diff] [blame] | 34 | // SSE codegen depends on cmovs, and all |
Michael J. Spencer | 9a0bac4 | 2011-04-14 14:33:36 +0000 | [diff] [blame] | 35 | // SSE1+ processors support them. |
Chris Lattner | 7008416 | 2009-09-02 05:53:04 +0000 | [diff] [blame] | 36 | [FeatureMMX, FeatureCMOV]>; |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 37 | def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", |
| 38 | "Enable SSE2 instructions", |
| 39 | [FeatureSSE1]>; |
| 40 | def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", |
| 41 | "Enable SSE3 instructions", |
| 42 | [FeatureSSE2]>; |
| 43 | def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", |
| 44 | "Enable SSSE3 instructions", |
| 45 | [FeatureSSE3]>; |
Nate Begeman | 63ec90a | 2008-02-03 07:18:54 +0000 | [diff] [blame] | 46 | def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", |
| 47 | "Enable SSE 4.1 instructions", |
| 48 | [FeatureSSSE3]>; |
| 49 | def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", |
| 50 | "Enable SSE 4.2 instructions", |
Benjamin Kramer | 1292c22 | 2010-12-04 20:32:23 +0000 | [diff] [blame] | 51 | [FeatureSSE41, FeaturePOPCNT]>; |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 52 | def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", |
Michael J. Spencer | 4babeee | 2011-04-15 00:32:41 +0000 | [diff] [blame] | 53 | "Enable 3DNow! instructions", |
| 54 | [FeatureMMX]>; |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 55 | def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", |
Bill Wendling | 11d8fda | 2007-05-06 07:56:19 +0000 | [diff] [blame] | 56 | "Enable 3DNow! Athlon instructions", |
| 57 | [Feature3DNow]>; |
Dan Gohman | f75e5b4 | 2009-02-03 00:04:43 +0000 | [diff] [blame] | 58 | // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied |
| 59 | // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) |
| 60 | // without disabling 64-bit mode. |
Bill Wendling | 11d8fda | 2007-05-06 07:56:19 +0000 | [diff] [blame] | 61 | def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", |
Chris Lattner | 1f84e32 | 2010-03-14 22:24:34 +0000 | [diff] [blame] | 62 | "Support 64-bit instructions", |
| 63 | [FeatureCMOV]>; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 64 | def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", |
| 65 | "Bit testing of memory is slow">; |
Evan Cheng | 48c58bb | 2010-04-01 05:58:17 +0000 | [diff] [blame] | 66 | def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem", |
| 67 | "IsUAMemFast", "true", |
| 68 | "Fast unaligned memory access">; |
Stefanus Du Toit | 8cf5ab1 | 2009-05-26 21:04:35 +0000 | [diff] [blame] | 69 | def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", |
Benjamin Kramer | 1292c22 | 2010-12-04 20:32:23 +0000 | [diff] [blame] | 70 | "Support SSE 4a instructions", |
| 71 | [FeaturePOPCNT]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 72 | |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 73 | def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true", |
| 74 | "Enable AVX instructions">; |
Bruno Cardoso Lopes | 26a9142 | 2010-07-23 01:22:45 +0000 | [diff] [blame] | 75 | def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true", |
| 76 | "Enable carry-less multiplication instructions">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 77 | def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 78 | "Enable three-operand fused multiple-add">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 79 | def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", |
| 80 | "Enable four-operand fused multiple-add">; |
David Greene | 95eb2ee | 2010-01-11 16:29:42 +0000 | [diff] [blame] | 81 | def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", |
| 82 | "HasVectorUAMem", "true", |
| 83 | "Allow unaligned memory operands on vector/SIMD instructions">; |
Eric Christopher | 6d1cd1c | 2010-04-02 21:54:27 +0000 | [diff] [blame] | 84 | def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", |
| 85 | "Enable AES instructions">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 86 | |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 87 | //===----------------------------------------------------------------------===// |
| 88 | // X86 processors supported. |
| 89 | //===----------------------------------------------------------------------===// |
| 90 | |
| 91 | class Proc<string Name, list<SubtargetFeature> Features> |
| 92 | : Processor<Name, NoItineraries, Features>; |
| 93 | |
| 94 | def : Proc<"generic", []>; |
| 95 | def : Proc<"i386", []>; |
| 96 | def : Proc<"i486", []>; |
Dale Johannesen | 2194d46 | 2008-10-14 22:06:33 +0000 | [diff] [blame] | 97 | def : Proc<"i586", []>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 98 | def : Proc<"pentium", []>; |
| 99 | def : Proc<"pentium-mmx", [FeatureMMX]>; |
| 100 | def : Proc<"i686", []>; |
Chris Lattner | 7008416 | 2009-09-02 05:53:04 +0000 | [diff] [blame] | 101 | def : Proc<"pentiumpro", [FeatureCMOV]>; |
| 102 | def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 103 | def : Proc<"pentium3", [FeatureSSE1]>; |
Michael J. Spencer | 34868ee | 2011-05-03 03:42:50 +0000 | [diff] [blame] | 104 | def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 105 | def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 106 | def : Proc<"pentium4", [FeatureSSE2]>; |
Michael J. Spencer | 34868ee | 2011-05-03 03:42:50 +0000 | [diff] [blame] | 107 | def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>; |
Evan Cheng | b1f4981 | 2009-12-22 17:47:23 +0000 | [diff] [blame] | 108 | def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; |
| 109 | def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; |
| 110 | def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; |
| 111 | def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; |
| 112 | def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>; |
| 113 | def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>; |
| 114 | def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; |
Eric Christopher | 6d1cd1c | 2010-04-02 21:54:27 +0000 | [diff] [blame] | 115 | // "Arrandale" along with corei3 and corei5 |
Evan Cheng | 48c58bb | 2010-04-01 05:58:17 +0000 | [diff] [blame] | 116 | def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem, |
Eric Christopher | 6d1cd1c | 2010-04-02 21:54:27 +0000 | [diff] [blame] | 117 | FeatureFastUAMem, FeatureAES]>; |
Evan Cheng | 48c58bb | 2010-04-01 05:58:17 +0000 | [diff] [blame] | 118 | def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem, |
| 119 | FeatureFastUAMem]>; |
Eric Christopher | 6d1cd1c | 2010-04-02 21:54:27 +0000 | [diff] [blame] | 120 | // Westmere is a similar machine to nehalem with some additional features. |
| 121 | // Westmere is the corei3/i5/i7 path from nehalem to sandybridge |
Nate Begeman | 2ea8ee7 | 2010-12-10 00:26:57 +0000 | [diff] [blame] | 122 | def : Proc<"westmere", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem, |
| 123 | FeatureFastUAMem, FeatureAES, FeatureCLMUL]>; |
| 124 | // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, |
| 125 | // rather than a superset. |
Evan Cheng | de7f920 | 2010-12-13 04:23:53 +0000 | [diff] [blame] | 126 | // FIXME: Disabling AVX for now since it's not ready. |
Benjamin Kramer | eb274e6 | 2011-05-20 15:11:26 +0000 | [diff] [blame] | 127 | def : Proc<"corei7-avx", [FeatureSSE42, Feature64Bit, |
Evan Cheng | de7f920 | 2010-12-13 04:23:53 +0000 | [diff] [blame] | 128 | FeatureAES, FeatureCLMUL]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 129 | |
| 130 | def : Proc<"k6", [FeatureMMX]>; |
Michael J. Spencer | 4babeee | 2011-04-15 00:32:41 +0000 | [diff] [blame] | 131 | def : Proc<"k6-2", [Feature3DNow]>; |
| 132 | def : Proc<"k6-3", [Feature3DNow]>; |
| 133 | def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>; |
| 134 | def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 135 | def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; |
| 136 | def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; |
| 137 | def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; |
Dan Gohman | f75e5b4 | 2009-02-03 00:04:43 +0000 | [diff] [blame] | 138 | def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, |
| 139 | FeatureSlowBTMem]>; |
| 140 | def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, |
| 141 | FeatureSlowBTMem]>; |
| 142 | def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, |
| 143 | FeatureSlowBTMem]>; |
| 144 | def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, |
| 145 | FeatureSlowBTMem]>; |
Stefanus Du Toit | 8cf5ab1 | 2009-05-26 21:04:35 +0000 | [diff] [blame] | 146 | def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, |
| 147 | FeatureSlowBTMem]>; |
| 148 | def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, |
| 149 | FeatureSlowBTMem]>; |
| 150 | def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, |
| 151 | FeatureSlowBTMem]>; |
| 152 | def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A, |
| 153 | Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; |
| 154 | def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A, |
| 155 | Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; |
David Greene | 3016af5 | 2009-06-29 16:54:06 +0000 | [diff] [blame] | 156 | def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A, |
| 157 | Feature3DNowA]>; |
| 158 | def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A, |
| 159 | Feature3DNowA]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 160 | |
| 161 | def : Proc<"winchip-c6", [FeatureMMX]>; |
Michael J. Spencer | 4babeee | 2011-04-15 00:32:41 +0000 | [diff] [blame] | 162 | def : Proc<"winchip2", [Feature3DNow]>; |
| 163 | def : Proc<"c3", [Feature3DNow]>; |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 164 | def : Proc<"c3-2", [FeatureSSE1]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 165 | |
| 166 | //===----------------------------------------------------------------------===// |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 167 | // Register File Description |
| 168 | //===----------------------------------------------------------------------===// |
| 169 | |
| 170 | include "X86RegisterInfo.td" |
| 171 | |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 172 | //===----------------------------------------------------------------------===// |
| 173 | // Instruction Descriptions |
| 174 | //===----------------------------------------------------------------------===// |
| 175 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 176 | include "X86InstrInfo.td" |
| 177 | |
Jakob Stoklund Olesen | fddb766 | 2010-04-05 03:10:20 +0000 | [diff] [blame] | 178 | def X86InstrInfo : InstrInfo; |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 179 | |
Chris Lattner | 31c8a6d | 2007-02-26 18:17:14 +0000 | [diff] [blame] | 180 | //===----------------------------------------------------------------------===// |
| 181 | // Calling Conventions |
| 182 | //===----------------------------------------------------------------------===// |
| 183 | |
| 184 | include "X86CallingConv.td" |
| 185 | |
| 186 | |
| 187 | //===----------------------------------------------------------------------===// |
Jim Grosbach | 604cdf6 | 2010-10-30 13:48:28 +0000 | [diff] [blame] | 188 | // Assembly Parser |
Chris Lattner | 31c8a6d | 2007-02-26 18:17:14 +0000 | [diff] [blame] | 189 | //===----------------------------------------------------------------------===// |
| 190 | |
Daniel Dunbar | 0e2771f | 2009-07-29 00:02:19 +0000 | [diff] [blame] | 191 | // Currently the X86 assembly parser only supports ATT syntax. |
| 192 | def ATTAsmParser : AsmParser { |
Daniel Dunbar | c918d60 | 2010-05-04 16:12:42 +0000 | [diff] [blame] | 193 | string AsmParserClassName = "ATTAsmParser"; |
Daniel Dunbar | 0e2771f | 2009-07-29 00:02:19 +0000 | [diff] [blame] | 194 | int Variant = 0; |
Daniel Dunbar | 59fc42d | 2009-08-11 20:59:47 +0000 | [diff] [blame] | 195 | |
| 196 | // Discard comments in assembly strings. |
| 197 | string CommentDelimiter = "#"; |
| 198 | |
| 199 | // Recognize hard coded registers. |
| 200 | string RegisterPrefix = "%"; |
Daniel Dunbar | 0e2771f | 2009-07-29 00:02:19 +0000 | [diff] [blame] | 201 | } |
| 202 | |
Jim Grosbach | 604cdf6 | 2010-10-30 13:48:28 +0000 | [diff] [blame] | 203 | //===----------------------------------------------------------------------===// |
| 204 | // Assembly Printers |
| 205 | //===----------------------------------------------------------------------===// |
| 206 | |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 207 | // The X86 target supports two different syntaxes for emitting machine code. |
| 208 | // This is controlled by the -x86-asm-syntax={att|intel} |
| 209 | def ATTAsmWriter : AsmWriter { |
Chris Lattner | cae05cb | 2009-09-13 19:30:11 +0000 | [diff] [blame] | 210 | string AsmWriterClassName = "ATTInstPrinter"; |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 211 | int Variant = 0; |
Jim Grosbach | ddcf859 | 2010-09-30 23:40:25 +0000 | [diff] [blame] | 212 | bit isMCAsmWriter = 1; |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 213 | } |
| 214 | def IntelAsmWriter : AsmWriter { |
Chris Lattner | 7057641 | 2009-09-20 07:47:59 +0000 | [diff] [blame] | 215 | string AsmWriterClassName = "IntelInstPrinter"; |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 216 | int Variant = 1; |
Jim Grosbach | ddcf859 | 2010-09-30 23:40:25 +0000 | [diff] [blame] | 217 | bit isMCAsmWriter = 1; |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 218 | } |
| 219 | |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 220 | def X86 : Target { |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 221 | // Information about the instructions... |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 222 | let InstructionSet = X86InstrInfo; |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 223 | |
Daniel Dunbar | 0e2771f | 2009-07-29 00:02:19 +0000 | [diff] [blame] | 224 | let AssemblyParsers = [ATTAsmParser]; |
| 225 | |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 226 | let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 227 | } |