blob: e93bac4987cc3d919b47beddcbae12f0078affbf [file] [log] [blame]
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00007//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Evan Chengb6ca4b32007-08-14 23:25:37 +000039STATISTIC(NumDRM , "Number of re-materializable defs elided");
Chris Lattnercd3245a2006-12-19 22:41:21 +000040STATISTIC(NumStores, "Number of stores added");
41STATISTIC(NumLoads , "Number of loads added");
42STATISTIC(NumReused, "Number of values reused");
43STATISTIC(NumDSE , "Number of dead stores elided");
44STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000045
Chris Lattnercd3245a2006-12-19 22:41:21 +000046namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000048
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000049 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000051 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 cl::Prefix,
53 cl::values(clEnumVal(simple, " simple spiller"),
54 clEnumVal(local, " local spiller"),
55 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000056 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000057}
58
Chris Lattner8c4d88d2004-09-30 01:54:45 +000059//===----------------------------------------------------------------------===//
60// VirtRegMap implementation
61//===----------------------------------------------------------------------===//
62
Chris Lattner29268692006-09-05 02:12:02 +000063VirtRegMap::VirtRegMap(MachineFunction &mf)
64 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000065 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng81a03822007-11-17 00:40:40 +000066 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
Evan Chengd120ffd2007-12-05 10:24:35 +000067 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000068 grow();
69}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071void VirtRegMap::grow() {
Chris Lattner84bc5422007-12-31 04:13:23 +000072 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
Evan Cheng549f27d32007-08-13 23:45:17 +000073 Virt2PhysMap.grow(LastVirtReg);
74 Virt2StackSlotMap.grow(LastVirtReg);
75 Virt2ReMatIdMap.grow(LastVirtReg);
Evan Cheng81a03822007-11-17 00:40:40 +000076 Virt2SplitMap.grow(LastVirtReg);
Evan Chengadf85902007-12-05 09:51:10 +000077 Virt2SplitKillMap.grow(LastVirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +000078 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000079}
80
Chris Lattner8c4d88d2004-09-30 01:54:45 +000081int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +000082 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000083 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000084 "attempt to assign stack slot to already spilled register");
Chris Lattner84bc5422007-12-31 04:13:23 +000085 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
Chris Lattner7f690e62004-09-30 02:15:18 +000086 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
87 RC->getAlignment());
88 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000089 ++NumSpills;
90 return frameIndex;
91}
92
93void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
Dan Gohman6f0d0242008-02-10 18:45:23 +000094 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000095 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000096 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000097 assert((frameIndex >= 0 ||
98 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
99 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +0000100 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +0000101}
102
Evan Cheng2638e1a2007-03-20 08:13:50 +0000103int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000104 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000105 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000106 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000107 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000108 return ReMatId++;
109}
110
Evan Cheng549f27d32007-08-13 23:45:17 +0000111void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000112 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000113 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
114 "attempt to assign re-mat id to already spilled register");
115 Virt2ReMatIdMap[virtReg] = id;
116}
117
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000118void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Evan Chengaee4af62007-12-02 08:30:39 +0000119 MachineInstr *NewMI, ModRef MRInfo) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000120 // Move previous memory references folded to new instruction.
121 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000122 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000123 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
124 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000125 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000126 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000127
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000128 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000129 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000130}
131
Evan Cheng7f566252007-10-13 02:50:24 +0000132void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
133 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
134 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
135}
136
Chris Lattner7f690e62004-09-30 02:15:18 +0000137void VirtRegMap::print(std::ostream &OS) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000138 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000139
Chris Lattner7f690e62004-09-30 02:15:18 +0000140 OS << "********** REGISTER MAP **********\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +0000141 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
Chris Lattner84bc5422007-12-31 04:13:23 +0000142 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
Chris Lattner7f690e62004-09-30 02:15:18 +0000143 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
Dan Gohman6f0d0242008-02-10 18:45:23 +0000144 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000145
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 }
147
Dan Gohman6f0d0242008-02-10 18:45:23 +0000148 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
Chris Lattner84bc5422007-12-31 04:13:23 +0000149 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
Chris Lattner7f690e62004-09-30 02:15:18 +0000150 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
151 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
152 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000153}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000154
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000155void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000156 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000157}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000158
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000159
160//===----------------------------------------------------------------------===//
161// Simple Spiller Implementation
162//===----------------------------------------------------------------------===//
163
164Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000165
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000166namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000167 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000168 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000170}
171
Chris Lattner35f27052006-05-01 21:16:03 +0000172bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000173 DOUT << "********** REWRITE MACHINE CODE **********\n";
174 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000175 const TargetMachine &TM = MF.getTarget();
Owen Andersonf6372aa2008-01-01 21:11:32 +0000176 const TargetInstrInfo &TII = *TM.getInstrInfo();
177
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000178
Chris Lattner4ea1b822004-09-30 02:33:48 +0000179 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
180 // each vreg once (in the case where a spilled vreg is used by multiple
181 // operands). This is always smaller than the number of operands to the
182 // current machine instr, so it should be small.
183 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000184
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000185 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
186 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000187 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000188 MachineBasicBlock &MBB = *MBBI;
189 for (MachineBasicBlock::iterator MII = MBB.begin(),
190 E = MBB.end(); MII != E; ++MII) {
191 MachineInstr &MI = *MII;
192 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000193 MachineOperand &MO = MI.getOperand(i);
Anton Korobeynikov4c71dfe2008-02-20 11:10:28 +0000194 if (MO.isRegister() && MO.getReg()) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000195 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
Chris Lattner886dd912005-04-04 21:35:34 +0000196 unsigned VirtReg = MO.getReg();
197 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000198 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000199 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000200 const TargetRegisterClass* RC =
Chris Lattner84bc5422007-12-31 04:13:23 +0000201 MF.getRegInfo().getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000202
Chris Lattner886dd912005-04-04 21:35:34 +0000203 if (MO.isUse() &&
204 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
205 == LoadedRegs.end()) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000206 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000207 LoadedRegs.push_back(VirtReg);
208 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000209 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000210 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000211
Chris Lattner886dd912005-04-04 21:35:34 +0000212 if (MO.isDef()) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000213 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
Evan Chengd64b5c82007-12-05 03:14:33 +0000214 StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000215 ++NumStores;
216 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000217 }
Chris Lattner84bc5422007-12-31 04:13:23 +0000218 MF.getRegInfo().setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000219 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000220 } else {
Chris Lattner84bc5422007-12-31 04:13:23 +0000221 MF.getRegInfo().setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000222 }
Anton Korobeynikov4c71dfe2008-02-20 11:10:28 +0000223 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000224 }
Chris Lattner886dd912005-04-04 21:35:34 +0000225
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000226 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000227 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000228 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000229 }
230 return true;
231}
232
233//===----------------------------------------------------------------------===//
234// Local Spiller Implementation
235//===----------------------------------------------------------------------===//
236
237namespace {
Evan Cheng66f71632007-10-19 21:23:22 +0000238 class AvailableSpills;
239
Chris Lattner7fb64342004-10-01 19:04:51 +0000240 /// LocalSpiller - This spiller does a simple pass over the machine basic
241 /// block to attempt to keep spills in registers as much as possible for
242 /// blocks that have low register pressure (the vreg may be spilled due to
243 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000244 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner84bc5422007-12-31 04:13:23 +0000245 MachineRegisterInfo *RegInfo;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000246 const TargetRegisterInfo *TRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000247 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000248 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000249 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner84bc5422007-12-31 04:13:23 +0000250 RegInfo = &MF.getRegInfo();
Dan Gohman6f0d0242008-02-10 18:45:23 +0000251 TRI = MF.getTarget().getRegisterInfo();
Chris Lattner7fb64342004-10-01 19:04:51 +0000252 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000253 DOUT << "\n**** Local spiller rewriting function '"
254 << MF.getFunction()->getName() << "':\n";
Chris Lattner84bc5422007-12-31 04:13:23 +0000255 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
256 " ****\n";
David Greene04fa32f2007-09-06 16:36:39 +0000257 DEBUG(MF.dump());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000258
Chris Lattner7fb64342004-10-01 19:04:51 +0000259 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
260 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000261 RewriteMBB(*MBB, VRM);
David Greene04fa32f2007-09-06 16:36:39 +0000262
263 DOUT << "**** Post Machine Instrs ****\n";
264 DEBUG(MF.dump());
265
Chris Lattner7fb64342004-10-01 19:04:51 +0000266 return true;
267 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000268 private:
Evan Cheng66f71632007-10-19 21:23:22 +0000269 bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator &MII,
271 std::vector<MachineInstr*> &MaybeDeadStores,
272 AvailableSpills &Spills, BitVector &RegKills,
273 std::vector<MachineOperand*> &KillOps,
274 VirtRegMap &VRM);
Evan Cheng81a03822007-11-17 00:40:40 +0000275 void SpillRegToStackSlot(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator &MII,
277 int Idx, unsigned PhysReg, int StackSlot,
278 const TargetRegisterClass *RC,
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000279 bool isAvailable, MachineInstr *&LastStore,
Evan Cheng81a03822007-11-17 00:40:40 +0000280 AvailableSpills &Spills,
281 SmallSet<MachineInstr*, 4> &ReMatDefs,
282 BitVector &RegKills,
283 std::vector<MachineOperand*> &KillOps,
Evan Chenge4b39002007-12-03 21:31:55 +0000284 VirtRegMap &VRM);
Evan Cheng549f27d32007-08-13 23:45:17 +0000285 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000286 };
287}
288
Chris Lattner66cf80f2006-02-03 23:13:58 +0000289/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000290/// top down, keep track of which spills slots or remat are available in each
291/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000292///
293/// Note that not all physregs are created equal here. In particular, some
294/// physregs are reloads that we are allowed to clobber or ignore at any time.
295/// Other physregs are values that the register allocated program is using that
296/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000297/// per-stack-slot / remat id basis as the low bit in the value of the
298/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
299/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000300namespace {
301class VISIBILITY_HIDDEN AvailableSpills {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000302 const TargetRegisterInfo *TRI;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000303 const TargetInstrInfo *TII;
304
Evan Cheng549f27d32007-08-13 23:45:17 +0000305 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
306 // or remat'ed virtual register values that are still available, due to being
307 // loaded or stored to, but not invalidated yet.
308 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000309
Evan Cheng549f27d32007-08-13 23:45:17 +0000310 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
311 // indicating which stack slot values are currently held by a physreg. This
312 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
313 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000314 std::multimap<unsigned, int> PhysRegsAvailable;
315
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000316 void disallowClobberPhysRegOnly(unsigned PhysReg);
317
Chris Lattner66cf80f2006-02-03 23:13:58 +0000318 void ClobberPhysRegOnly(unsigned PhysReg);
319public:
Dan Gohman6f0d0242008-02-10 18:45:23 +0000320 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
321 : TRI(tri), TII(tii) {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000322 }
323
Dan Gohman6f0d0242008-02-10 18:45:23 +0000324 const TargetRegisterInfo *getRegInfo() const { return TRI; }
Evan Cheng91e23902007-02-23 01:13:26 +0000325
Evan Cheng549f27d32007-08-13 23:45:17 +0000326 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
327 /// available in a physical register, return that PhysReg, otherwise
328 /// return 0.
329 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
330 std::map<int, unsigned>::const_iterator I =
331 SpillSlotsOrReMatsAvailable.find(Slot);
332 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000333 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000334 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000335 return 0;
336 }
Evan Chengde4e9422007-02-25 09:51:27 +0000337
Evan Cheng549f27d32007-08-13 23:45:17 +0000338 /// addAvailable - Mark that the specified stack slot / remat is available in
339 /// the specified physreg. If CanClobber is true, the physreg can be modified
340 /// at any time without changing the semantics of the program.
341 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000342 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000343 // If this stack slot is thought to be available in some other physreg,
344 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000345 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000346
Evan Cheng549f27d32007-08-13 23:45:17 +0000347 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
Evan Cheng90a43c32007-08-15 20:20:34 +0000348 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000349
Evan Cheng549f27d32007-08-13 23:45:17 +0000350 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
351 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000352 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000353 DOUT << "Remembering SS#" << SlotOrReMat;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000354 DOUT << " in physreg " << TRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000355 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000356
Chris Lattner593c9582006-02-03 23:28:46 +0000357 /// canClobberPhysReg - Return true if the spiller is allowed to change the
358 /// value of the specified stackslot register if it desires. The specified
359 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000360 bool canClobberPhysReg(int SlotOrReMat) const {
Evan Cheng90a43c32007-08-15 20:20:34 +0000361 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
362 "Value not available!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000363 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000364 }
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000365
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000366 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
367 /// stackslot register. The register is still available but is no longer
368 /// allowed to be modifed.
369 void disallowClobberPhysReg(unsigned PhysReg);
370
Chris Lattner66cf80f2006-02-03 23:13:58 +0000371 /// ClobberPhysReg - This is called when the specified physreg changes
Evan Cheng66f71632007-10-19 21:23:22 +0000372 /// value. We use this to invalidate any info about stuff that lives in
Chris Lattner66cf80f2006-02-03 23:13:58 +0000373 /// it and any of its aliases.
374 void ClobberPhysReg(unsigned PhysReg);
375
Evan Cheng90a43c32007-08-15 20:20:34 +0000376 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
377 /// slot changes. This removes information about which register the previous
378 /// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000379 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000380};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000381}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000382
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000383/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
384/// stackslot register. The register is still available but is no longer
385/// allowed to be modifed.
386void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
387 std::multimap<unsigned, int>::iterator I =
388 PhysRegsAvailable.lower_bound(PhysReg);
389 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000390 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000391 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000392 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000393 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000394 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000395 DOUT << "PhysReg " << TRI->getName(PhysReg)
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000396 << " copied, it is available for use but can no longer be modified\n";
397 }
398}
399
400/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
401/// stackslot register and its aliases. The register and its aliases may
402/// still available but is no longer allowed to be modifed.
403void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000404 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000405 disallowClobberPhysRegOnly(*AS);
406 disallowClobberPhysRegOnly(PhysReg);
407}
408
Chris Lattner66cf80f2006-02-03 23:13:58 +0000409/// ClobberPhysRegOnly - This is called when the specified physreg changes
410/// value. We use this to invalidate any info about stuff we thing lives in it.
411void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
412 std::multimap<unsigned, int>::iterator I =
413 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000414 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000415 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000416 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000417 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000418 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000419 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Dan Gohman6f0d0242008-02-10 18:45:23 +0000420 DOUT << "PhysReg " << TRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000421 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000422 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
423 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000424 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000425 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000426 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000427}
428
Chris Lattner66cf80f2006-02-03 23:13:58 +0000429/// ClobberPhysReg - This is called when the specified physreg changes
430/// value. We use this to invalidate any info about stuff we thing lives in
431/// it and any of its aliases.
432void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000433 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000434 ClobberPhysRegOnly(*AS);
435 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000436}
437
Evan Cheng90a43c32007-08-15 20:20:34 +0000438/// ModifyStackSlotOrReMat - This method is called when the value in a stack
439/// slot changes. This removes information about which register the previous
440/// value for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000441void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
Evan Cheng90a43c32007-08-15 20:20:34 +0000442 std::map<int, unsigned>::iterator It =
443 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
Evan Cheng549f27d32007-08-13 23:45:17 +0000444 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000445 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000446 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000447
448 // This register may hold the value of multiple stack slots, only remove this
449 // stack slot from the set of values the register contains.
450 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
451 for (; ; ++I) {
452 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
453 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000454 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000455 }
456 PhysRegsAvailable.erase(I);
457}
458
459
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000460
Evan Cheng28bb4622007-07-11 19:17:18 +0000461/// InvalidateKills - MI is going to be deleted. If any of its operands are
462/// marked kill, then invalidate the information.
463static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
Evan Chengc91f0b82007-08-14 20:23:13 +0000464 std::vector<MachineOperand*> &KillOps,
Evan Cheng66f71632007-10-19 21:23:22 +0000465 SmallVector<unsigned, 2> *KillRegs = NULL) {
Evan Cheng28bb4622007-07-11 19:17:18 +0000466 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
467 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000468 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
Evan Cheng28bb4622007-07-11 19:17:18 +0000469 continue;
470 unsigned Reg = MO.getReg();
Evan Chengb6ca4b32007-08-14 23:25:37 +0000471 if (KillRegs)
472 KillRegs->push_back(Reg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000473 if (KillOps[Reg] == &MO) {
474 RegKills.reset(Reg);
475 KillOps[Reg] = NULL;
476 }
477 }
478}
479
Evan Cheng39c883c2007-12-11 23:36:57 +0000480/// InvalidateKill - A MI that defines the specified register is being deleted,
481/// invalidate the register kill information.
482static void InvalidateKill(unsigned Reg, BitVector &RegKills,
483 std::vector<MachineOperand*> &KillOps) {
484 if (RegKills[Reg]) {
Chris Lattnerf7382302007-12-30 21:56:09 +0000485 KillOps[Reg]->setIsKill(false);
Evan Cheng39c883c2007-12-11 23:36:57 +0000486 KillOps[Reg] = NULL;
487 RegKills.reset(Reg);
488 }
489}
490
Evan Chengb6ca4b32007-08-14 23:25:37 +0000491/// InvalidateRegDef - If the def operand of the specified def MI is now dead
492/// (since it's spill instruction is removed), mark it isDead. Also checks if
493/// the def MI has other definition operands that are not dead. Returns it by
494/// reference.
495static bool InvalidateRegDef(MachineBasicBlock::iterator I,
496 MachineInstr &NewDef, unsigned Reg,
497 bool &HasLiveDef) {
498 // Due to remat, it's possible this reg isn't being reused. That is,
499 // the def of this reg (by prev MI) is now dead.
500 MachineInstr *DefMI = I;
501 MachineOperand *DefOp = NULL;
502 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
503 MachineOperand &MO = DefMI->getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000504 if (MO.isRegister() && MO.isDef()) {
Evan Chengb6ca4b32007-08-14 23:25:37 +0000505 if (MO.getReg() == Reg)
506 DefOp = &MO;
507 else if (!MO.isDead())
508 HasLiveDef = true;
509 }
510 }
511 if (!DefOp)
512 return false;
513
514 bool FoundUse = false, Done = false;
515 MachineBasicBlock::iterator E = NewDef;
516 ++I; ++E;
517 for (; !Done && I != E; ++I) {
518 MachineInstr *NMI = I;
519 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
520 MachineOperand &MO = NMI->getOperand(j);
Dan Gohman92dfe202007-09-14 20:33:02 +0000521 if (!MO.isRegister() || MO.getReg() != Reg)
Evan Chengb6ca4b32007-08-14 23:25:37 +0000522 continue;
523 if (MO.isUse())
524 FoundUse = true;
525 Done = true; // Stop after scanning all the operands of this MI.
526 }
527 }
528 if (!FoundUse) {
529 // Def is dead!
530 DefOp->setIsDead();
531 return true;
532 }
533 return false;
534}
535
Evan Cheng28bb4622007-07-11 19:17:18 +0000536/// UpdateKills - Track and update kill info. If a MI reads a register that is
537/// marked kill, then it must be due to register reuse. Transfer the kill info
538/// over.
539static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
540 std::vector<MachineOperand*> &KillOps) {
Chris Lattner749c6f62008-01-07 07:27:27 +0000541 const TargetInstrDesc &TID = MI.getDesc();
Evan Cheng28bb4622007-07-11 19:17:18 +0000542 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
543 MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000544 if (!MO.isRegister() || !MO.isUse())
Evan Cheng28bb4622007-07-11 19:17:18 +0000545 continue;
546 unsigned Reg = MO.getReg();
547 if (Reg == 0)
548 continue;
549
550 if (RegKills[Reg]) {
551 // That can't be right. Register is killed but not re-defined and it's
552 // being reused. Let's fix that.
Chris Lattnerf7382302007-12-30 21:56:09 +0000553 KillOps[Reg]->setIsKill(false);
Evan Cheng39c883c2007-12-11 23:36:57 +0000554 KillOps[Reg] = NULL;
555 RegKills.reset(Reg);
Chris Lattner749c6f62008-01-07 07:27:27 +0000556 if (i < TID.getNumOperands() &&
557 TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
Evan Cheng28bb4622007-07-11 19:17:18 +0000558 // Unless it's a two-address operand, this is the new kill.
559 MO.setIsKill();
560 }
Evan Cheng28bb4622007-07-11 19:17:18 +0000561 if (MO.isKill()) {
562 RegKills.set(Reg);
563 KillOps[Reg] = &MO;
564 }
565 }
566
567 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
568 const MachineOperand &MO = MI.getOperand(i);
Dan Gohman92dfe202007-09-14 20:33:02 +0000569 if (!MO.isRegister() || !MO.isDef())
Evan Cheng28bb4622007-07-11 19:17:18 +0000570 continue;
571 unsigned Reg = MO.getReg();
572 RegKills.reset(Reg);
573 KillOps[Reg] = NULL;
574 }
575}
576
577
Chris Lattner7fb64342004-10-01 19:04:51 +0000578// ReusedOp - For each reused operand, we keep track of a bit of information, in
579// case we need to rollback upon processing a new operand. See comments below.
580namespace {
581 struct ReusedOp {
582 // The MachineInstr operand that reused an available value.
583 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000584
Evan Cheng549f27d32007-08-13 23:45:17 +0000585 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
586 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000587
Chris Lattner7fb64342004-10-01 19:04:51 +0000588 // PhysRegReused - The physical register the value was available in.
589 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000590
Chris Lattner7fb64342004-10-01 19:04:51 +0000591 // AssignedPhysReg - The physreg that was assigned for use by the reload.
592 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000593
594 // VirtReg - The virtual register itself.
595 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000596
Chris Lattner8a61a752005-10-06 17:19:06 +0000597 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
598 unsigned vreg)
Evan Cheng90a43c32007-08-15 20:20:34 +0000599 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
600 AssignedPhysReg(apr), VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000601 };
Chris Lattner540fec62006-02-25 01:51:33 +0000602
603 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
604 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000605 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000606 MachineInstr &MI;
607 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000608 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000609 public:
Dan Gohman6f0d0242008-02-10 18:45:23 +0000610 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
611 PhysRegsClobbered.resize(tri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000612 }
Chris Lattner540fec62006-02-25 01:51:33 +0000613
614 bool hasReuses() const {
615 return !Reuses.empty();
616 }
617
618 /// addReuse - If we choose to reuse a virtual register that is already
619 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000620 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000621 unsigned PhysRegReused, unsigned AssignedPhysReg,
622 unsigned VirtReg) {
623 // If the reload is to the assigned register anyway, no undo will be
624 // required.
625 if (PhysRegReused == AssignedPhysReg) return;
626
627 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000628 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000629 AssignedPhysReg, VirtReg));
630 }
Evan Chenge077ef62006-11-04 00:21:55 +0000631
632 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000633 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000634 }
635
636 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000637 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000638 }
Chris Lattner540fec62006-02-25 01:51:33 +0000639
640 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
641 /// is some other operand that is using the specified register, either pick
642 /// a new register to use, or evict the previous reload and use this reg.
643 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
644 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000645 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000646 SmallSet<unsigned, 8> &Rejected,
647 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000648 std::vector<MachineOperand*> &KillOps,
649 VirtRegMap &VRM) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000650 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
651 .getInstrInfo();
652
Chris Lattner540fec62006-02-25 01:51:33 +0000653 if (Reuses.empty()) return PhysReg; // This is most often empty.
654
655 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
656 ReusedOp &Op = Reuses[ro];
657 // If we find some other reuse that was supposed to use this register
658 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000659 // register. That is, unless its reload register has already been
660 // considered and subsequently rejected because it has also been reused
661 // by another operand.
662 if (Op.PhysRegReused == PhysReg &&
663 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000664 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000665 unsigned NewReg = Op.AssignedPhysReg;
666 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000667 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000668 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000669 } else {
670 // Otherwise, we might also have a problem if a previously reused
671 // value aliases the new register. If so, codegen the previous reload
672 // and use this one.
673 unsigned PRRU = Op.PhysRegReused;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000674 const TargetRegisterInfo *TRI = Spills.getRegInfo();
675 if (TRI->areAliases(PRRU, PhysReg)) {
Chris Lattner540fec62006-02-25 01:51:33 +0000676 // Okay, we found out that an alias of a reused register
677 // was used. This isn't good because it means we have
678 // to undo a previous reuse.
679 MachineBasicBlock *MBB = MI->getParent();
680 const TargetRegisterClass *AliasRC =
Chris Lattner84bc5422007-12-31 04:13:23 +0000681 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
Chris Lattner28bad082006-02-25 02:17:31 +0000682
683 // Copy Op out of the vector and remove it, we're going to insert an
684 // explicit load for it.
685 ReusedOp NewOp = Op;
686 Reuses.erase(Reuses.begin()+ro);
687
688 // Ok, we're going to try to reload the assigned physreg into the
689 // slot that we were supposed to in the first place. However, that
690 // register could hold a reuse. Check to see if it conflicts or
691 // would prefer us to use a different register.
692 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000693 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000694 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000695
Evan Cheng549f27d32007-08-13 23:45:17 +0000696 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000697 TRI->reMaterialize(*MBB, MI, NewPhysReg,
Evan Cheng549f27d32007-08-13 23:45:17 +0000698 VRM.getReMaterializedMI(NewOp.VirtReg));
699 ++NumReMats;
700 } else {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000701 TII->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
Evan Cheng549f27d32007-08-13 23:45:17 +0000702 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000703 // Any stores to this stack slot are not dead anymore.
704 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000705 ++NumLoads;
706 }
Chris Lattner28bad082006-02-25 02:17:31 +0000707 Spills.ClobberPhysReg(NewPhysReg);
708 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000709
Chris Lattnere53f4a02006-05-04 17:52:23 +0000710 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000711
Evan Cheng549f27d32007-08-13 23:45:17 +0000712 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000713 MachineBasicBlock::iterator MII = MI;
714 --MII;
715 UpdateKills(*MII, RegKills, KillOps);
716 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000717
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000718 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000719 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000720
721 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000722 return PhysReg;
723 }
724 }
725 }
726 return PhysReg;
727 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000728
729 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
730 /// 'Rejected' set to remember which registers have been considered and
731 /// rejected for the reload. This avoids infinite looping in case like
732 /// this:
733 /// t1 := op t2, t3
734 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
735 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
736 /// t1 <- desires r1
737 /// sees r1 is taken by t2, tries t2's reload register r0
738 /// sees r0 is taken by t3, tries t3's reload register r1
739 /// sees r1 is taken by t2, tries t2's reload register r0 ...
740 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
741 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000742 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000743 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000744 std::vector<MachineOperand*> &KillOps,
745 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000746 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000747 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000748 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000749 }
Chris Lattner540fec62006-02-25 01:51:33 +0000750 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000751}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000752
Evan Cheng66f71632007-10-19 21:23:22 +0000753/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
754/// instruction. e.g.
755/// xorl %edi, %eax
756/// movl %eax, -32(%ebp)
757/// movl -36(%ebp), %eax
758/// orl %eax, -32(%ebp)
759/// ==>
760/// xorl %edi, %eax
761/// orl -36(%ebp), %eax
762/// mov %eax, -32(%ebp)
763/// This enables unfolding optimization for a subsequent instruction which will
764/// also eliminate the newly introduced store instruction.
765bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
766 MachineBasicBlock::iterator &MII,
767 std::vector<MachineInstr*> &MaybeDeadStores,
768 AvailableSpills &Spills,
769 BitVector &RegKills,
770 std::vector<MachineOperand*> &KillOps,
771 VirtRegMap &VRM) {
772 MachineFunction &MF = *MBB.getParent();
773 MachineInstr &MI = *MII;
774 unsigned UnfoldedOpc = 0;
775 unsigned UnfoldPR = 0;
776 unsigned UnfoldVR = 0;
777 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
778 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
779 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
780 // Only transform a MI that folds a single register.
781 if (UnfoldedOpc)
782 return false;
783 UnfoldVR = I->second.first;
784 VirtRegMap::ModRef MR = I->second.second;
785 if (VRM.isAssignedReg(UnfoldVR))
786 continue;
787 // If this reference is not a use, any previous store is now dead.
788 // Otherwise, the store to this stack slot is not dead anymore.
789 FoldedSS = VRM.getStackSlot(UnfoldVR);
790 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
791 if (DeadStore && (MR & VirtRegMap::isModRef)) {
792 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
793 if (!PhysReg ||
794 DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1)
795 continue;
796 UnfoldPR = PhysReg;
Owen Anderson6425f8b2008-01-07 01:35:56 +0000797 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
Evan Cheng66f71632007-10-19 21:23:22 +0000798 false, true);
799 }
800 }
801
802 if (!UnfoldedOpc)
803 return false;
804
805 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
806 MachineOperand &MO = MI.getOperand(i);
807 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse())
808 continue;
809 unsigned VirtReg = MO.getReg();
Dan Gohman6f0d0242008-02-10 18:45:23 +0000810 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
Evan Cheng66f71632007-10-19 21:23:22 +0000811 continue;
812 if (VRM.isAssignedReg(VirtReg)) {
813 unsigned PhysReg = VRM.getPhys(VirtReg);
Dan Gohman6f0d0242008-02-10 18:45:23 +0000814 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
Evan Cheng66f71632007-10-19 21:23:22 +0000815 return false;
816 } else if (VRM.isReMaterialized(VirtReg))
817 continue;
818 int SS = VRM.getStackSlot(VirtReg);
819 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
820 if (PhysReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000821 if (TRI->regsOverlap(PhysReg, UnfoldPR))
Evan Cheng66f71632007-10-19 21:23:22 +0000822 return false;
823 continue;
824 }
825 PhysReg = VRM.getPhys(VirtReg);
Dan Gohman6f0d0242008-02-10 18:45:23 +0000826 if (!TRI->regsOverlap(PhysReg, UnfoldPR))
Evan Cheng66f71632007-10-19 21:23:22 +0000827 continue;
828
829 // Ok, we'll need to reload the value into a register which makes
830 // it impossible to perform the store unfolding optimization later.
831 // Let's see if it is possible to fold the load if the store is
832 // unfolded. This allows us to perform the store unfolding
833 // optimization.
834 SmallVector<MachineInstr*, 4> NewMIs;
Owen Anderson6425f8b2008-01-07 01:35:56 +0000835 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
Evan Cheng66f71632007-10-19 21:23:22 +0000836 assert(NewMIs.size() == 1);
837 MachineInstr *NewMI = NewMIs.back();
838 NewMIs.clear();
Evan Cheng81a03822007-11-17 00:40:40 +0000839 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg);
840 assert(Idx != -1);
Evan Chengaee4af62007-12-02 08:30:39 +0000841 SmallVector<unsigned, 2> Ops;
842 Ops.push_back(Idx);
Evan Chengf2f8c2a2008-02-08 22:05:27 +0000843 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
Evan Cheng66f71632007-10-19 21:23:22 +0000844 if (FoldedMI) {
Evan Chengcbfb9b22007-10-22 03:01:44 +0000845 if (!VRM.hasPhys(UnfoldVR))
Evan Cheng66f71632007-10-19 21:23:22 +0000846 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
Evan Cheng66f71632007-10-19 21:23:22 +0000847 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
848 MII = MBB.insert(MII, FoldedMI);
Evan Chengcada2452007-11-28 01:28:46 +0000849 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng66f71632007-10-19 21:23:22 +0000850 MBB.erase(&MI);
851 return true;
852 }
853 delete NewMI;
854 }
855 }
856 return false;
857}
Chris Lattner7fb64342004-10-01 19:04:51 +0000858
Evan Cheng7277a7d2007-11-02 17:35:08 +0000859/// findSuperReg - Find the SubReg's super-register of given register class
860/// where its SubIdx sub-register is SubReg.
861static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
Dan Gohman6f0d0242008-02-10 18:45:23 +0000862 unsigned SubIdx, const TargetRegisterInfo *TRI) {
Evan Cheng7277a7d2007-11-02 17:35:08 +0000863 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
864 I != E; ++I) {
865 unsigned Reg = *I;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000866 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
Evan Cheng7277a7d2007-11-02 17:35:08 +0000867 return Reg;
868 }
869 return 0;
870}
871
Evan Cheng81a03822007-11-17 00:40:40 +0000872/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
873/// the last store to the same slot is now dead. If so, remove the last store.
874void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
875 MachineBasicBlock::iterator &MII,
876 int Idx, unsigned PhysReg, int StackSlot,
877 const TargetRegisterClass *RC,
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000878 bool isAvailable, MachineInstr *&LastStore,
Evan Cheng81a03822007-11-17 00:40:40 +0000879 AvailableSpills &Spills,
880 SmallSet<MachineInstr*, 4> &ReMatDefs,
881 BitVector &RegKills,
882 std::vector<MachineOperand*> &KillOps,
Evan Chenge4b39002007-12-03 21:31:55 +0000883 VirtRegMap &VRM) {
Owen Andersonf6372aa2008-01-01 21:11:32 +0000884 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
Evan Cheng81a03822007-11-17 00:40:40 +0000885 DOUT << "Store:\t" << *next(MII);
886
887 // If there is a dead store to this stack slot, nuke it now.
888 if (LastStore) {
889 DOUT << "Removed dead store:\t" << *LastStore;
890 ++NumDSE;
891 SmallVector<unsigned, 2> KillRegs;
892 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
893 MachineBasicBlock::iterator PrevMII = LastStore;
894 bool CheckDef = PrevMII != MBB.begin();
895 if (CheckDef)
896 --PrevMII;
897 MBB.erase(LastStore);
Evan Chengcada2452007-11-28 01:28:46 +0000898 VRM.RemoveMachineInstrFromMaps(LastStore);
Evan Cheng81a03822007-11-17 00:40:40 +0000899 if (CheckDef) {
900 // Look at defs of killed registers on the store. Mark the defs
901 // as dead since the store has been deleted and they aren't
902 // being reused.
903 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
904 bool HasOtherDef = false;
905 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
906 MachineInstr *DeadDef = PrevMII;
907 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
908 // FIXME: This assumes a remat def does not have side
909 // effects.
910 MBB.erase(DeadDef);
Evan Chengcada2452007-11-28 01:28:46 +0000911 VRM.RemoveMachineInstrFromMaps(DeadDef);
Evan Cheng81a03822007-11-17 00:40:40 +0000912 ++NumDRM;
913 }
914 }
915 }
916 }
917 }
918
Evan Chenge4b39002007-12-03 21:31:55 +0000919 LastStore = next(MII);
Evan Cheng81a03822007-11-17 00:40:40 +0000920
921 // If the stack slot value was previously available in some other
922 // register, change it now. Otherwise, make the register available,
923 // in PhysReg.
924 Spills.ModifyStackSlotOrReMat(StackSlot);
925 Spills.ClobberPhysReg(PhysReg);
Evan Cheng35a3e4a2007-12-04 19:19:45 +0000926 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable);
Evan Cheng81a03822007-11-17 00:40:40 +0000927 ++NumStores;
928}
929
Chris Lattner7fb64342004-10-01 19:04:51 +0000930/// rewriteMBB - Keep track of which spills are available even after the
Evan Cheng81a03822007-11-17 00:40:40 +0000931/// register allocator is done with them. If possible, avid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000932void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000933 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000934
Evan Chengfff3e192007-08-14 09:11:18 +0000935 MachineFunction &MF = *MBB.getParent();
Owen Andersond10fd972007-12-31 06:32:00 +0000936
Chris Lattner66cf80f2006-02-03 23:13:58 +0000937 // Spills - Keep track of which spilled values are available in physregs so
938 // that we can choose to reuse the physregs instead of emitting reloads.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000939 AvailableSpills Spills(TRI, TII);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000940
Chris Lattner52b25db2004-10-01 19:47:12 +0000941 // MaybeDeadStores - When we need to write a value back into a stack slot,
942 // keep track of the inserted store. If the stack slot value is never read
943 // (because the value was used from some available register, for example), and
944 // subsequently stored to, the original store is dead. This map keeps track
945 // of inserted stores that are not used. If we see a subsequent store to the
946 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000947 std::vector<MachineInstr*> MaybeDeadStores;
948 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000949
Evan Chengb6ca4b32007-08-14 23:25:37 +0000950 // ReMatDefs - These are rematerializable def MIs which are not deleted.
951 SmallSet<MachineInstr*, 4> ReMatDefs;
952
Evan Cheng0c40d722007-07-11 05:28:39 +0000953 // Keep track of kill information.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000954 BitVector RegKills(TRI->getNumRegs());
Evan Cheng0c40d722007-07-11 05:28:39 +0000955 std::vector<MachineOperand*> KillOps;
Dan Gohman6f0d0242008-02-10 18:45:23 +0000956 KillOps.resize(TRI->getNumRegs(), NULL);
Evan Cheng0c40d722007-07-11 05:28:39 +0000957
Chris Lattner7fb64342004-10-01 19:04:51 +0000958 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
959 MII != E; ) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000960 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000961
Evan Cheng66f71632007-10-19 21:23:22 +0000962 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
Evan Cheng0c40d722007-07-11 05:28:39 +0000963 bool Erased = false;
964 bool BackTracked = false;
Evan Cheng66f71632007-10-19 21:23:22 +0000965 if (PrepForUnfoldOpti(MBB, MII,
966 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
967 NextMII = next(MII);
Chris Lattner7fb64342004-10-01 19:04:51 +0000968
Evan Cheng66f71632007-10-19 21:23:22 +0000969 MachineInstr &MI = *MII;
Chris Lattner749c6f62008-01-07 07:27:27 +0000970 const TargetInstrDesc &TID = MI.getDesc();
Evan Chenge077ef62006-11-04 00:21:55 +0000971
Evan Cheng0cbb1162007-11-29 01:06:25 +0000972 // Insert restores here if asked to.
973 if (VRM.isRestorePt(&MI)) {
974 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
975 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
976 unsigned VirtReg = RestoreRegs[i];
977 if (!VRM.getPreSplitReg(VirtReg))
978 continue; // Split interval spilled again.
979 unsigned Phys = VRM.getPhys(VirtReg);
Chris Lattner84bc5422007-12-31 04:13:23 +0000980 RegInfo->setPhysRegUsed(Phys);
Evan Cheng0cbb1162007-11-29 01:06:25 +0000981 if (VRM.isReMaterialized(VirtReg)) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000982 TRI->reMaterialize(MBB, &MI, Phys,
Evan Cheng0cbb1162007-11-29 01:06:25 +0000983 VRM.getReMaterializedMI(VirtReg));
984 ++NumReMats;
985 } else {
Chris Lattner84bc5422007-12-31 04:13:23 +0000986 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
Owen Andersonf6372aa2008-01-01 21:11:32 +0000987 TII->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
Chris Lattner84bc5422007-12-31 04:13:23 +0000988 RC);
Evan Cheng0cbb1162007-11-29 01:06:25 +0000989 ++NumLoads;
990 }
991 // This invalidates Phys.
992 Spills.ClobberPhysReg(Phys);
993 UpdateKills(*prior(MII), RegKills, KillOps);
994 DOUT << '\t' << *prior(MII);
995 }
996 }
997
Evan Cheng81a03822007-11-17 00:40:40 +0000998 // Insert spills here if asked to.
Evan Chengcada2452007-11-28 01:28:46 +0000999 if (VRM.isSpillPt(&MI)) {
Evan Chengb50bb8c2007-12-05 08:16:32 +00001000 std::vector<std::pair<unsigned,bool> > &SpillRegs =
1001 VRM.getSpillPtSpills(&MI);
Evan Chengcada2452007-11-28 01:28:46 +00001002 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
Evan Chengb50bb8c2007-12-05 08:16:32 +00001003 unsigned VirtReg = SpillRegs[i].first;
1004 bool isKill = SpillRegs[i].second;
Evan Chengcada2452007-11-28 01:28:46 +00001005 if (!VRM.getPreSplitReg(VirtReg))
1006 continue; // Split interval spilled again.
Chris Lattner84bc5422007-12-31 04:13:23 +00001007 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
Evan Chengcada2452007-11-28 01:28:46 +00001008 unsigned Phys = VRM.getPhys(VirtReg);
1009 int StackSlot = VRM.getStackSlot(VirtReg);
Owen Andersonf6372aa2008-01-01 21:11:32 +00001010 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
Evan Chengd64b5c82007-12-05 03:14:33 +00001011 MachineInstr *StoreMI = next(MII);
1012 DOUT << "Store:\t" << StoreMI;
1013 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
Evan Chengcada2452007-11-28 01:28:46 +00001014 }
Evan Chenge4b39002007-12-03 21:31:55 +00001015 NextMII = next(MII);
Evan Cheng81a03822007-11-17 00:40:40 +00001016 }
1017
1018 /// ReusedOperands - Keep track of operand reuse in case we need to undo
1019 /// reuse.
Dan Gohman6f0d0242008-02-10 18:45:23 +00001020 ReuseInfo ReusedOperands(MI, TRI);
Chris Lattner7fb64342004-10-01 19:04:51 +00001021 // Process all of the spilled uses and all non spilled reg references.
1022 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1023 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001024 if (!MO.isRegister() || MO.getReg() == 0)
1025 continue; // Ignore non-register operands.
1026
Evan Cheng32dfbea2007-10-12 08:50:34 +00001027 unsigned VirtReg = MO.getReg();
Dan Gohman6f0d0242008-02-10 18:45:23 +00001028 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +00001029 // Ignore physregs for spilling, but remember that it is used by this
1030 // function.
Chris Lattner84bc5422007-12-31 04:13:23 +00001031 RegInfo->setPhysRegUsed(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001032 continue;
1033 }
1034
Dan Gohman6f0d0242008-02-10 18:45:23 +00001035 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
Chris Lattner50ea01e2005-09-09 20:29:51 +00001036 "Not a virtual or a physical register?");
Evan Cheng70306f82007-12-03 09:58:48 +00001037
Evan Chengc498b022007-11-14 07:59:08 +00001038 unsigned SubIdx = MO.getSubReg();
Evan Cheng549f27d32007-08-13 23:45:17 +00001039 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +00001040 // This virtual register was assigned a physreg!
1041 unsigned Phys = VRM.getPhys(VirtReg);
Chris Lattner84bc5422007-12-31 04:13:23 +00001042 RegInfo->setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +00001043 if (MO.isDef())
1044 ReusedOperands.markClobbered(Phys);
Dan Gohman6f0d0242008-02-10 18:45:23 +00001045 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001046 MI.getOperand(i).setReg(RReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001047 continue;
1048 }
1049
1050 // This virtual register is now known to be a spilled value.
1051 if (!MO.isUse())
1052 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +00001053
Evan Cheng549f27d32007-08-13 23:45:17 +00001054 bool DoReMat = VRM.isReMaterialized(VirtReg);
1055 int SSorRMId = DoReMat
1056 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +00001057 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +00001058
Chris Lattner50ea01e2005-09-09 20:29:51 +00001059 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +00001060 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001061
1062 // If this is a sub-register use, make sure the reuse register is in the
1063 // right register class. For example, for x86 not all of the 32-bit
1064 // registers have accessible sub-registers.
1065 // Similarly so for EXTRACT_SUBREG. Consider this:
1066 // EDI = op
1067 // MOV32_mr fi#1, EDI
1068 // ...
1069 // = EXTRACT_SUBREG fi#1
1070 // fi#1 is available in EDI, but it cannot be reused because it's not in
1071 // the right register file.
1072 if (PhysReg &&
Evan Chengc498b022007-11-14 07:59:08 +00001073 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
Chris Lattner84bc5422007-12-31 04:13:23 +00001074 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001075 if (!RC->contains(PhysReg))
1076 PhysReg = 0;
1077 }
1078
Evan Chengdc6be192007-08-14 05:42:54 +00001079 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +00001080 // This spilled operand might be part of a two-address operand. If this
1081 // is the case, then changing it will necessarily require changing the
1082 // def part of the instruction as well. However, in some cases, we
1083 // aren't allowed to modify the reused register. If none of these cases
1084 // apply, reuse it.
1085 bool CanReuse = true;
Chris Lattner749c6f62008-01-07 07:27:27 +00001086 int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001087 if (ti != -1 &&
Dan Gohman92dfe202007-09-14 20:33:02 +00001088 MI.getOperand(ti).isRegister() &&
Evan Cheng360c2dd2006-11-01 23:06:55 +00001089 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +00001090 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +00001091 // long as we are allowed to clobber the value and there isn't an
1092 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +00001093 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +00001094 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +00001095 }
1096
1097 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +00001098 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +00001099 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1100 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001101 else
Evan Chengdc6be192007-08-14 05:42:54 +00001102 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001103 DOUT << " from physreg "
Dan Gohman6f0d0242008-02-10 18:45:23 +00001104 << TRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001105 << VirtReg <<" instead of reloading into physreg "
Dan Gohman6f0d0242008-02-10 18:45:23 +00001106 << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
1107 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001108 MI.getOperand(i).setReg(RReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +00001109
1110 // The only technical detail we have is that we don't know that
1111 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1112 // later in the instruction. In particular, consider 'op V1, V2'.
1113 // If V1 is available in physreg R0, we would choose to reuse it
1114 // here, instead of reloading it into the register the allocator
1115 // indicated (say R1). However, V2 might have to be reloaded
1116 // later, and it might indicate that it needs to live in R0. When
1117 // this occurs, we need to have information available that
1118 // indicates it is safe to use R1 for the reload instead of R0.
1119 //
1120 // To further complicate matters, we might conflict with an alias,
1121 // or R0 and R1 might not be compatible with each other. In this
1122 // case, we actually insert a reload for V1 in R1, ensuring that
1123 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +00001124 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +00001125 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001126 if (ti != -1)
1127 // Only mark it clobbered if this is a use&def operand.
1128 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +00001129 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +00001130
1131 if (MI.getOperand(i).isKill() &&
1132 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1133 // This was the last use and the spilled value is still available
1134 // for reuse. That means the spill was unnecessary!
1135 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
1136 if (DeadStore) {
1137 DOUT << "Removed dead store:\t" << *DeadStore;
1138 InvalidateKills(*DeadStore, RegKills, KillOps);
Evan Chengcada2452007-11-28 01:28:46 +00001139 VRM.RemoveMachineInstrFromMaps(DeadStore);
Evan Cheng66f71632007-10-19 21:23:22 +00001140 MBB.erase(DeadStore);
Evan Chengfff3e192007-08-14 09:11:18 +00001141 MaybeDeadStores[ReuseSlot] = NULL;
1142 ++NumDSE;
1143 }
1144 }
Chris Lattneraddc55a2006-04-28 01:46:50 +00001145 continue;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001146 } // CanReuse
Chris Lattneraddc55a2006-04-28 01:46:50 +00001147
1148 // Otherwise we have a situation where we have a two-address instruction
1149 // whose mod/ref operand needs to be reloaded. This reload is already
1150 // available in some register "PhysReg", but if we used PhysReg as the
1151 // operand to our 2-addr instruction, the instruction would modify
1152 // PhysReg. This isn't cool if something later uses PhysReg and expects
1153 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +00001154 //
Chris Lattneraddc55a2006-04-28 01:46:50 +00001155 // To avoid this problem, and to avoid doing a load right after a store,
1156 // we emit a copy from PhysReg into the designated register for this
1157 // operand.
1158 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1159 assert(DesignatedReg && "Must map virtreg to physreg!");
1160
1161 // Note that, if we reused a register for a previous operand, the
1162 // register we want to reload into might not actually be
1163 // available. If this occurs, use the register indicated by the
1164 // reuser.
1165 if (ReusedOperands.hasReuses())
1166 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001167 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +00001168
Chris Lattnerba1fc3d2006-04-28 04:43:18 +00001169 // If the mapped designated register is actually the physreg we have
1170 // incoming, we don't need to inserted a dead copy.
1171 if (DesignatedReg == PhysReg) {
1172 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +00001173 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1174 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +00001175 else
Evan Chengdc6be192007-08-14 05:42:54 +00001176 DOUT << "Reusing SS#" << ReuseSlot;
Dan Gohman6f0d0242008-02-10 18:45:23 +00001177 DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001178 << VirtReg
1179 << " instead of reloading into same physreg.\n";
Dan Gohman6f0d0242008-02-10 18:45:23 +00001180 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001181 MI.getOperand(i).setReg(RReg);
Evan Cheng7277a7d2007-11-02 17:35:08 +00001182 ReusedOperands.markClobbered(RReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +00001183 ++NumReused;
1184 continue;
1185 }
1186
Chris Lattner84bc5422007-12-31 04:13:23 +00001187 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1188 RegInfo->setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001189 ReusedOperands.markClobbered(DesignatedReg);
Owen Andersond10fd972007-12-31 06:32:00 +00001190 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
Evan Chengde4e9422007-02-25 09:51:27 +00001191
Evan Cheng6b448092007-03-02 08:52:00 +00001192 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +00001193 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +00001194
Chris Lattneraddc55a2006-04-28 01:46:50 +00001195 // This invalidates DesignatedReg.
1196 Spills.ClobberPhysReg(DesignatedReg);
1197
Evan Chengdc6be192007-08-14 05:42:54 +00001198 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001199 unsigned RReg =
Dan Gohman6f0d0242008-02-10 18:45:23 +00001200 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001201 MI.getOperand(i).setReg(RReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001202 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001203 ++NumReused;
1204 continue;
Evan Cheng66f71632007-10-19 21:23:22 +00001205 } // if (PhysReg)
Chris Lattner50ea01e2005-09-09 20:29:51 +00001206
1207 // Otherwise, reload it and remember that we have it.
1208 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +00001209 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattner7fb64342004-10-01 19:04:51 +00001210
Chris Lattner50ea01e2005-09-09 20:29:51 +00001211 // Note that, if we reused a register for a previous operand, the
1212 // register we want to reload into might not actually be
1213 // available. If this occurs, use the register indicated by the
1214 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +00001215 if (ReusedOperands.hasReuses())
1216 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001217 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +00001218
Chris Lattner84bc5422007-12-31 04:13:23 +00001219 RegInfo->setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001220 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +00001221 if (DoReMat) {
Dan Gohman6f0d0242008-02-10 18:45:23 +00001222 TRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +00001223 ++NumReMats;
1224 } else {
Chris Lattner84bc5422007-12-31 04:13:23 +00001225 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
Owen Andersonf6372aa2008-01-01 21:11:32 +00001226 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +00001227 ++NumLoads;
1228 }
Chris Lattner50ea01e2005-09-09 20:29:51 +00001229 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001230 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +00001231
1232 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +00001233 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +00001234 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +00001235 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +00001236 // Assumes this is the last use. IsKill will be unset if reg is reused
1237 // unless it's a two-address operand.
Chris Lattner749c6f62008-01-07 07:27:27 +00001238 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
Evan Chengde4e9422007-02-25 09:51:27 +00001239 MI.getOperand(i).setIsKill();
Dan Gohman6f0d0242008-02-10 18:45:23 +00001240 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001241 MI.getOperand(i).setReg(RReg);
Evan Cheng0c40d722007-07-11 05:28:39 +00001242 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001243 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001244 }
1245
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001246 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001247
Evan Cheng81a03822007-11-17 00:40:40 +00001248
Chris Lattner7fb64342004-10-01 19:04:51 +00001249 // If we have folded references to memory operands, make sure we clear all
1250 // physical registers that may contain the value of the spilled virtual
1251 // register
Evan Cheng66f71632007-10-19 21:23:22 +00001252 SmallSet<int, 2> FoldedSS;
Chris Lattner8f1d6402005-01-14 15:54:24 +00001253 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +00001254 unsigned VirtReg = I->second.first;
1255 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng66f71632007-10-19 21:23:22 +00001256 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR;
Evan Cheng81a03822007-11-17 00:40:40 +00001257
Chris Lattnercea86882005-09-19 06:56:21 +00001258 int SS = VRM.getStackSlot(VirtReg);
Evan Cheng81a03822007-11-17 00:40:40 +00001259 if (SS == VirtRegMap::NO_STACK_SLOT)
1260 continue;
Evan Cheng90a43c32007-08-15 20:20:34 +00001261 FoldedSS.insert(SS);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001262 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +00001263
1264 // If this folded instruction is just a use, check to see if it's a
1265 // straight load from the virt reg slot.
1266 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1267 int FrameIdx;
Evan Cheng32dfbea2007-10-12 08:50:34 +00001268 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1269 if (DestReg && FrameIdx == SS) {
1270 // If this spill slot is available, turn it into a copy (or nothing)
1271 // instead of leaving it as a load!
1272 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1273 DOUT << "Promoted Load To Copy: " << MI;
1274 if (DestReg != InReg) {
Chris Lattner84bc5422007-12-31 04:13:23 +00001275 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
Owen Andersond10fd972007-12-31 06:32:00 +00001276 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001277 // Revisit the copy so we make sure to notice the effects of the
1278 // operation on the destreg (either needing to RA it if it's
1279 // virtual or needing to clobber any values if it's physical).
1280 NextMII = &MI;
1281 --NextMII; // backtrack to the copy.
1282 BackTracked = true;
Evan Cheng39c883c2007-12-11 23:36:57 +00001283 } else {
Evan Cheng32dfbea2007-10-12 08:50:34 +00001284 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng39c883c2007-12-11 23:36:57 +00001285 // Unset last kill since it's being reused.
1286 InvalidateKill(InReg, RegKills, KillOps);
1287 }
Evan Chengde4e9422007-02-25 09:51:27 +00001288
Evan Chengcada2452007-11-28 01:28:46 +00001289 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng32dfbea2007-10-12 08:50:34 +00001290 MBB.erase(&MI);
1291 Erased = true;
1292 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +00001293 }
Evan Cheng7f566252007-10-13 02:50:24 +00001294 } else {
1295 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1296 SmallVector<MachineInstr*, 4> NewMIs;
1297 if (PhysReg &&
Owen Anderson6425f8b2008-01-07 01:35:56 +00001298 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
Evan Cheng7f566252007-10-13 02:50:24 +00001299 MBB.insert(MII, NewMIs[0]);
Evan Chengcada2452007-11-28 01:28:46 +00001300 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng7f566252007-10-13 02:50:24 +00001301 MBB.erase(&MI);
1302 Erased = true;
1303 --NextMII; // backtrack to the unfolded instruction.
1304 BackTracked = true;
1305 goto ProcessNextInst;
1306 }
Chris Lattnercea86882005-09-19 06:56:21 +00001307 }
1308 }
1309
1310 // If this reference is not a use, any previous store is now dead.
1311 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +00001312 MachineInstr* DeadStore = MaybeDeadStores[SS];
1313 if (DeadStore) {
Evan Cheng66f71632007-10-19 21:23:22 +00001314 bool isDead = !(MR & VirtRegMap::isRef);
Evan Cheng7f566252007-10-13 02:50:24 +00001315 MachineInstr *NewStore = NULL;
Evan Chengcbfb9b22007-10-22 03:01:44 +00001316 if (MR & VirtRegMap::isModRef) {
Evan Cheng7f566252007-10-13 02:50:24 +00001317 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1318 SmallVector<MachineInstr*, 4> NewMIs;
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001319 // We can reuse this physreg as long as we are allowed to clobber
Chris Lattner84bc5422007-12-31 04:13:23 +00001320 // the value and there isn't an earlier def that has already clobbered
1321 // the physreg.
Evan Cheng7f566252007-10-13 02:50:24 +00001322 if (PhysReg &&
Evan Cheng39c883c2007-12-11 23:36:57 +00001323 !TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
Evan Cheng7f566252007-10-13 02:50:24 +00001324 DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
Owen Anderson6425f8b2008-01-07 01:35:56 +00001325 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) {
Evan Cheng7f566252007-10-13 02:50:24 +00001326 MBB.insert(MII, NewMIs[0]);
1327 NewStore = NewMIs[1];
1328 MBB.insert(MII, NewStore);
Evan Chengcada2452007-11-28 01:28:46 +00001329 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng7f566252007-10-13 02:50:24 +00001330 MBB.erase(&MI);
1331 Erased = true;
1332 --NextMII;
1333 --NextMII; // backtrack to the unfolded instruction.
1334 BackTracked = true;
Evan Cheng66f71632007-10-19 21:23:22 +00001335 isDead = true;
1336 }
Evan Cheng7f566252007-10-13 02:50:24 +00001337 }
1338
1339 if (isDead) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +00001340 // If we get here, the store is dead, nuke it now.
Evan Chengfff3e192007-08-14 09:11:18 +00001341 DOUT << "Removed dead store:\t" << *DeadStore;
1342 InvalidateKills(*DeadStore, RegKills, KillOps);
Evan Chengcada2452007-11-28 01:28:46 +00001343 VRM.RemoveMachineInstrFromMaps(DeadStore);
Evan Cheng7f566252007-10-13 02:50:24 +00001344 MBB.erase(DeadStore);
1345 if (!NewStore)
1346 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001347 }
Evan Cheng7f566252007-10-13 02:50:24 +00001348
Evan Chengfff3e192007-08-14 09:11:18 +00001349 MaybeDeadStores[SS] = NULL;
Evan Cheng7f566252007-10-13 02:50:24 +00001350 if (NewStore) {
1351 // Treat this store as a spill merged into a copy. That makes the
1352 // stack slot value available.
1353 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
1354 goto ProcessNextInst;
1355 }
Chris Lattnercea86882005-09-19 06:56:21 +00001356 }
1357
1358 // If the spill slot value is available, and this is a new definition of
1359 // the value, the value is not available anymore.
1360 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001361 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +00001362 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001363
1364 // If this is *just* a mod of the value, check to see if this is just a
1365 // store to the spill slot (i.e. the spill got merged into the copy). If
1366 // so, realize that the vreg is available now, and add the store to the
1367 // MaybeDeadStore info.
1368 int StackSlot;
1369 if (!(MR & VirtRegMap::isRef)) {
1370 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
Dan Gohman6f0d0242008-02-10 18:45:23 +00001371 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
Chris Lattnercd816392006-02-02 23:29:36 +00001372 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001373 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001374 // this as a potentially dead store in case there is a subsequent
1375 // store into the stack slot without a read from it.
1376 MaybeDeadStores[StackSlot] = &MI;
1377
Chris Lattnercd816392006-02-02 23:29:36 +00001378 // If the stack slot value was previously available in some other
1379 // register, change it now. Otherwise, make the register available,
1380 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001381 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001382 }
1383 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001384 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001385 }
1386
Chris Lattner7fb64342004-10-01 19:04:51 +00001387 // Process all of the spilled defs.
1388 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1389 MachineOperand &MO = MI.getOperand(i);
Evan Cheng66f71632007-10-19 21:23:22 +00001390 if (!(MO.isRegister() && MO.getReg() && MO.isDef()))
1391 continue;
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001392
Evan Cheng66f71632007-10-19 21:23:22 +00001393 unsigned VirtReg = MO.getReg();
Dan Gohman6f0d0242008-02-10 18:45:23 +00001394 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
Evan Cheng66f71632007-10-19 21:23:22 +00001395 // Check to see if this is a noop copy. If so, eliminate the
1396 // instruction before considering the dest reg to be changed.
1397 unsigned Src, Dst;
1398 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1399 ++NumDCE;
1400 DOUT << "Removing now-noop copy: " << MI;
1401 MBB.erase(&MI);
1402 Erased = true;
Evan Chengcada2452007-11-28 01:28:46 +00001403 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng66f71632007-10-19 21:23:22 +00001404 Spills.disallowClobberPhysReg(VirtReg);
1405 goto ProcessNextInst;
1406 }
1407
1408 // If it's not a no-op copy, it clobbers the value in the destreg.
1409 Spills.ClobberPhysReg(VirtReg);
1410 ReusedOperands.markClobbered(VirtReg);
1411
1412 // Check to see if this instruction is a load from a stack slot into
1413 // a register. If so, this provides the stack slot value in the reg.
1414 int FrameIdx;
1415 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1416 assert(DestReg == VirtReg && "Unknown load situation!");
1417
1418 // If it is a folded reference, then it's not safe to clobber.
1419 bool Folded = FoldedSS.count(FrameIdx);
1420 // Otherwise, if it wasn't available, remember that it is now!
1421 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded);
1422 goto ProcessNextInst;
1423 }
1424
1425 continue;
1426 }
1427
Evan Chengc498b022007-11-14 07:59:08 +00001428 unsigned SubIdx = MO.getSubReg();
Evan Cheng66f71632007-10-19 21:23:22 +00001429 bool DoReMat = VRM.isReMaterialized(VirtReg);
1430 if (DoReMat)
1431 ReMatDefs.insert(&MI);
1432
1433 // The only vregs left are stack slot definitions.
1434 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattner84bc5422007-12-31 04:13:23 +00001435 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
Evan Cheng66f71632007-10-19 21:23:22 +00001436
1437 // If this def is part of a two-address operand, make sure to execute
1438 // the store from the correct physical register.
1439 unsigned PhysReg;
Chris Lattner749c6f62008-01-07 07:27:27 +00001440 int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
Evan Cheng7277a7d2007-11-02 17:35:08 +00001441 if (TiedOp != -1) {
Evan Cheng66f71632007-10-19 21:23:22 +00001442 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chengc498b022007-11-14 07:59:08 +00001443 if (SubIdx) {
Dan Gohman6f0d0242008-02-10 18:45:23 +00001444 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
1445 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
Evan Cheng7277a7d2007-11-02 17:35:08 +00001446 "Can't find corresponding super-register!");
1447 PhysReg = SuperReg;
1448 }
1449 } else {
Evan Cheng66f71632007-10-19 21:23:22 +00001450 PhysReg = VRM.getPhys(VirtReg);
1451 if (ReusedOperands.isClobbered(PhysReg)) {
1452 // Another def has taken the assigned physreg. It must have been a
1453 // use&def which got it due to reuse. Undo the reuse!
1454 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1455 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1456 }
1457 }
1458
Chris Lattner84bc5422007-12-31 04:13:23 +00001459 RegInfo->setPhysRegUsed(PhysReg);
Dan Gohman6f0d0242008-02-10 18:45:23 +00001460 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
Evan Cheng7277a7d2007-11-02 17:35:08 +00001461 ReusedOperands.markClobbered(RReg);
1462 MI.getOperand(i).setReg(RReg);
1463
Evan Cheng66f71632007-10-19 21:23:22 +00001464 if (!MO.isDead()) {
Evan Cheng66f71632007-10-19 21:23:22 +00001465 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001466 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
1467 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
Evan Chenge4b39002007-12-03 21:31:55 +00001468 NextMII = next(MII);
Evan Cheng66f71632007-10-19 21:23:22 +00001469
1470 // Check to see if this is a noop copy. If so, eliminate the
1471 // instruction before considering the dest reg to be changed.
1472 {
Chris Lattner29268692006-09-05 02:12:02 +00001473 unsigned Src, Dst;
1474 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1475 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001476 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001477 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001478 Erased = true;
Evan Chengcada2452007-11-28 01:28:46 +00001479 VRM.RemoveMachineInstrFromMaps(&MI);
Evan Cheng66f71632007-10-19 21:23:22 +00001480 UpdateKills(*LastStore, RegKills, KillOps);
Chris Lattner29268692006-09-05 02:12:02 +00001481 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001482 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00001483 }
Evan Cheng66f71632007-10-19 21:23:22 +00001484 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001485 }
Chris Lattnercea86882005-09-19 06:56:21 +00001486 ProcessNextInst:
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001487 if (!Erased && !BackTracked) {
Evan Cheng0c40d722007-07-11 05:28:39 +00001488 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1489 UpdateKills(*II, RegKills, KillOps);
Evan Cheng35a3e4a2007-12-04 19:19:45 +00001490 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001491 MII = NextMII;
1492 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001493}
1494
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001495llvm::Spiller* llvm::createSpiller() {
1496 switch (SpillerOpt) {
1497 default: assert(0 && "Unreachable!");
1498 case local:
1499 return new LocalSpiller();
1500 case simple:
1501 return new SimpleSpiller();
1502 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001503}