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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 24d315dc053e8130593a8053bd6dc0245632f5f3 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 34f3bc90550a49cffc3bb9cae57ccea320dde209 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]15#include "llvm/ADT/BitVector.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]16#include "llvm/ADT/STLExtras.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]17#include "llvm/CodeGen/Analysis.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineJumpTableInfo.h"
21#include "llvm/CodeGen/SelectionDAG.h"
Chandler Carruth0b8c9a82013-01-02 11:36:10 +0000[diff] [blame]22#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/DerivedTypes.h"
24#include "llvm/IR/GlobalVariable.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]25#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCExpr.h"
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]27#include "llvm/Support/CommandLine.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]28#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]29#include "llvm/Support/MathExtras.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]30#include "llvm/Target/TargetLoweringObjectFile.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Target/TargetRegisterInfo.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]33#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]34using namespace llvm;
35
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]36/// InitLibcallNames - Set default libcall names.
37///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]38static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]39 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]40 Names[RTLIB::SHL_I32] = "__ashlsi3";
41 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]42 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]43 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]44 Names[RTLIB::SRL_I32] = "__lshrsi3";
45 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]46 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]47 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]48 Names[RTLIB::SRA_I32] = "__ashrsi3";
49 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]50 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]51 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]52 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]53 Names[RTLIB::MUL_I32] = "__mulsi3";
54 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]55 Names[RTLIB::MUL_I128] = "__multi3";
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]56 Names[RTLIB::MULO_I32] = "__mulosi4";
57 Names[RTLIB::MULO_I64] = "__mulodi4";
58 Names[RTLIB::MULO_I128] = "__muloti4";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]59 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]60 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]61 Names[RTLIB::SDIV_I32] = "__divsi3";
62 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]63 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]64 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]65 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]66 Names[RTLIB::UDIV_I32] = "__udivsi3";
67 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]68 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]69 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]70 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]71 Names[RTLIB::SREM_I32] = "__modsi3";
72 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]73 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]74 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]75 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]76 Names[RTLIB::UREM_I32] = "__umodsi3";
77 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]78 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame]79
80 // These are generally not available.
81 Names[RTLIB::SDIVREM_I8] = 0;
82 Names[RTLIB::SDIVREM_I16] = 0;
83 Names[RTLIB::SDIVREM_I32] = 0;
84 Names[RTLIB::SDIVREM_I64] = 0;
85 Names[RTLIB::SDIVREM_I128] = 0;
86 Names[RTLIB::UDIVREM_I8] = 0;
87 Names[RTLIB::UDIVREM_I16] = 0;
88 Names[RTLIB::UDIVREM_I32] = 0;
89 Names[RTLIB::UDIVREM_I64] = 0;
90 Names[RTLIB::UDIVREM_I128] = 0;
91
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]92 Names[RTLIB::NEG_I32] = "__negsi2";
93 Names[RTLIB::NEG_I64] = "__negdi2";
94 Names[RTLIB::ADD_F32] = "__addsf3";
95 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]96 Names[RTLIB::ADD_F80] = "__addxf3";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]97 Names[RTLIB::ADD_F128] = "__addtf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]98 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]99 Names[RTLIB::SUB_F32] = "__subsf3";
100 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]101 Names[RTLIB::SUB_F80] = "__subxf3";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]102 Names[RTLIB::SUB_F128] = "__subtf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]104 Names[RTLIB::MUL_F32] = "__mulsf3";
105 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]106 Names[RTLIB::MUL_F80] = "__mulxf3";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]107 Names[RTLIB::MUL_F128] = "__multf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]111 Names[RTLIB::DIV_F80] = "__divxf3";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]112 Names[RTLIB::DIV_F128] = "__divtf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]114 Names[RTLIB::REM_F32] = "fmodf";
115 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]116 Names[RTLIB::REM_F80] = "fmodl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]117 Names[RTLIB::REM_F128] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]118 Names[RTLIB::REM_PPCF128] = "fmodl";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]119 Names[RTLIB::FMA_F32] = "fmaf";
120 Names[RTLIB::FMA_F64] = "fma";
121 Names[RTLIB::FMA_F80] = "fmal";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]122 Names[RTLIB::FMA_F128] = "fmal";
Cameron Zwarich33390842011-07-08 21:39:21 +0000[diff] [blame]123 Names[RTLIB::FMA_PPCF128] = "fmal";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]124 Names[RTLIB::POWI_F32] = "__powisf2";
125 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]126 Names[RTLIB::POWI_F80] = "__powixf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]127 Names[RTLIB::POWI_F128] = "__powitf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]128 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]129 Names[RTLIB::SQRT_F32] = "sqrtf";
130 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]131 Names[RTLIB::SQRT_F80] = "sqrtl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]132 Names[RTLIB::SQRT_F128] = "sqrtl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]133 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]134 Names[RTLIB::LOG_F32] = "logf";
135 Names[RTLIB::LOG_F64] = "log";
136 Names[RTLIB::LOG_F80] = "logl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]137 Names[RTLIB::LOG_F128] = "logl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]138 Names[RTLIB::LOG_PPCF128] = "logl";
139 Names[RTLIB::LOG2_F32] = "log2f";
140 Names[RTLIB::LOG2_F64] = "log2";
141 Names[RTLIB::LOG2_F80] = "log2l";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]142 Names[RTLIB::LOG2_F128] = "log2l";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]143 Names[RTLIB::LOG2_PPCF128] = "log2l";
144 Names[RTLIB::LOG10_F32] = "log10f";
145 Names[RTLIB::LOG10_F64] = "log10";
146 Names[RTLIB::LOG10_F80] = "log10l";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]147 Names[RTLIB::LOG10_F128] = "log10l";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]148 Names[RTLIB::LOG10_PPCF128] = "log10l";
149 Names[RTLIB::EXP_F32] = "expf";
150 Names[RTLIB::EXP_F64] = "exp";
151 Names[RTLIB::EXP_F80] = "expl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]152 Names[RTLIB::EXP_F128] = "expl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]153 Names[RTLIB::EXP_PPCF128] = "expl";
154 Names[RTLIB::EXP2_F32] = "exp2f";
155 Names[RTLIB::EXP2_F64] = "exp2";
156 Names[RTLIB::EXP2_F80] = "exp2l";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]157 Names[RTLIB::EXP2_F128] = "exp2l";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]158 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]159 Names[RTLIB::SIN_F32] = "sinf";
160 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]161 Names[RTLIB::SIN_F80] = "sinl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]162 Names[RTLIB::SIN_F128] = "sinl";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]163 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]164 Names[RTLIB::COS_F32] = "cosf";
165 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]166 Names[RTLIB::COS_F80] = "cosl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]167 Names[RTLIB::COS_F128] = "cosl";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]168 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]169 Names[RTLIB::POW_F32] = "powf";
170 Names[RTLIB::POW_F64] = "pow";
171 Names[RTLIB::POW_F80] = "powl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]172 Names[RTLIB::POW_F128] = "powl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]173 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]174 Names[RTLIB::CEIL_F32] = "ceilf";
175 Names[RTLIB::CEIL_F64] = "ceil";
176 Names[RTLIB::CEIL_F80] = "ceill";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]177 Names[RTLIB::CEIL_F128] = "ceill";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]178 Names[RTLIB::CEIL_PPCF128] = "ceill";
179 Names[RTLIB::TRUNC_F32] = "truncf";
180 Names[RTLIB::TRUNC_F64] = "trunc";
181 Names[RTLIB::TRUNC_F80] = "truncl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]182 Names[RTLIB::TRUNC_F128] = "truncl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]183 Names[RTLIB::TRUNC_PPCF128] = "truncl";
184 Names[RTLIB::RINT_F32] = "rintf";
185 Names[RTLIB::RINT_F64] = "rint";
186 Names[RTLIB::RINT_F80] = "rintl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]187 Names[RTLIB::RINT_F128] = "rintl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]188 Names[RTLIB::RINT_PPCF128] = "rintl";
189 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
190 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
191 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]192 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]193 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
194 Names[RTLIB::FLOOR_F32] = "floorf";
195 Names[RTLIB::FLOOR_F64] = "floor";
196 Names[RTLIB::FLOOR_F80] = "floorl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]197 Names[RTLIB::FLOOR_F128] = "floorl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]198 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]199 Names[RTLIB::COPYSIGN_F32] = "copysignf";
200 Names[RTLIB::COPYSIGN_F64] = "copysign";
201 Names[RTLIB::COPYSIGN_F80] = "copysignl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]202 Names[RTLIB::COPYSIGN_F128] = "copysignl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]203 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]204 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
205 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]206 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]207 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
208 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]209 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]210 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]211 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]212 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
213 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]214 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]215 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]216 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
217 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]218 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
219 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]220 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]221 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
222 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]223 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
224 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]225 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]226 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]227 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]228 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]229 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
230 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
231 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]232 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]233 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]234 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]235 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
236 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]237 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
238 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]239 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]240 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
241 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]242 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
243 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]244 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]245 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
246 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]247 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]248 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
249 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
250 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]251 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]252 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]253 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]254 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
255 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]256 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]257 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]258 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]259 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
260 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]261 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]262 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]263 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]264 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
265 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
266 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]267 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]268 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]269 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
270 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]271 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]272 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]273 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]274 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
275 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]276 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]277 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]278 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
279 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
280 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
281 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]282 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]283 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]284 Names[RTLIB::OEQ_F32] = "__eqsf2";
285 Names[RTLIB::OEQ_F64] = "__eqdf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]286 Names[RTLIB::OEQ_F128] = "__eqtf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]287 Names[RTLIB::UNE_F32] = "__nesf2";
288 Names[RTLIB::UNE_F64] = "__nedf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]289 Names[RTLIB::UNE_F128] = "__netf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]290 Names[RTLIB::OGE_F32] = "__gesf2";
291 Names[RTLIB::OGE_F64] = "__gedf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]292 Names[RTLIB::OGE_F128] = "__getf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]293 Names[RTLIB::OLT_F32] = "__ltsf2";
294 Names[RTLIB::OLT_F64] = "__ltdf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]295 Names[RTLIB::OLT_F128] = "__lttf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]296 Names[RTLIB::OLE_F32] = "__lesf2";
297 Names[RTLIB::OLE_F64] = "__ledf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]298 Names[RTLIB::OLE_F128] = "__letf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]299 Names[RTLIB::OGT_F32] = "__gtsf2";
300 Names[RTLIB::OGT_F64] = "__gtdf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]301 Names[RTLIB::OGT_F128] = "__gttf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]302 Names[RTLIB::UO_F32] = "__unordsf2";
303 Names[RTLIB::UO_F64] = "__unorddf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]304 Names[RTLIB::UO_F128] = "__unordtf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]305 Names[RTLIB::O_F32] = "__unordsf2";
306 Names[RTLIB::O_F64] = "__unorddf2";
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]307 Names[RTLIB::O_F128] = "__unordtf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]308 Names[RTLIB::MEMCPY] = "memcpy";
309 Names[RTLIB::MEMMOVE] = "memmove";
310 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]311 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]312 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
313 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
314 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
315 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]316 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
317 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
318 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
319 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]320 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
321 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
322 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
323 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
324 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
325 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
326 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
327 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
328 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
329 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
330 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
331 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
332 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
333 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
334 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
335 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
336 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
337 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Jim Grosbach312b7c92011-10-14 15:53:48 +0000[diff] [blame]338 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]339 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
340 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
341 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
342 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
343 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]344}
345
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]346/// InitLibcallCallingConvs - Set default libcall CallingConvs.
347///
348static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
349 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
350 CCs[i] = CallingConv::C;
351 }
352}
353
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]354/// getFPEXT - Return the FPEXT_*_* value for the given types, or
355/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]356RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 if (OpVT == MVT::f32) {
358 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]359 return FPEXT_F32_F64;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]360 if (RetVT == MVT::f128)
361 return FPEXT_F32_F128;
362 } else if (OpVT == MVT::f64) {
363 if (RetVT == MVT::f128)
364 return FPEXT_F64_F128;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]365 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]366
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]367 return UNKNOWN_LIBCALL;
368}
369
370/// getFPROUND - Return the FPROUND_*_* value for the given types, or
371/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]372RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::f32) {
374 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]375 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]376 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]377 return FPROUND_F80_F32;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]378 if (OpVT == MVT::f128)
379 return FPROUND_F128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]380 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]381 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]382 } else if (RetVT == MVT::f64) {
383 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]384 return FPROUND_F80_F64;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]385 if (OpVT == MVT::f128)
386 return FPROUND_F128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]387 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]388 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]389 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]390
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]391 return UNKNOWN_LIBCALL;
392}
393
394/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
395/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]396RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]397 if (OpVT == MVT::f32) {
398 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]399 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]400 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]401 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]406 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]407 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]408 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]409 if (RetVT == MVT::i8)
410 return FPTOSINT_F64_I8;
411 if (RetVT == MVT::i16)
412 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]414 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]415 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]416 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]417 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]418 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]419 } else if (OpVT == MVT::f80) {
420 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]421 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]422 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]423 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]424 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]425 return FPTOSINT_F80_I128;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]426 } else if (OpVT == MVT::f128) {
427 if (RetVT == MVT::i32)
428 return FPTOSINT_F128_I32;
429 if (RetVT == MVT::i64)
430 return FPTOSINT_F128_I64;
431 if (RetVT == MVT::i128)
432 return FPTOSINT_F128_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]433 } else if (OpVT == MVT::ppcf128) {
434 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]435 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]436 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]439 return FPTOSINT_PPCF128_I128;
440 }
441 return UNKNOWN_LIBCALL;
442}
443
444/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
445/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]446RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 if (OpVT == MVT::f32) {
448 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]449 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]450 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]451 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]452 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]453 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]454 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]455 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]456 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]457 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]458 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]459 if (RetVT == MVT::i8)
460 return FPTOUINT_F64_I8;
461 if (RetVT == MVT::i16)
462 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]463 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]464 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]465 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]466 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]467 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]468 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]469 } else if (OpVT == MVT::f80) {
470 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]471 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]472 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]473 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]474 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]475 return FPTOUINT_F80_I128;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]476 } else if (OpVT == MVT::f128) {
477 if (RetVT == MVT::i32)
478 return FPTOUINT_F128_I32;
479 if (RetVT == MVT::i64)
480 return FPTOUINT_F128_I64;
481 if (RetVT == MVT::i128)
482 return FPTOUINT_F128_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]483 } else if (OpVT == MVT::ppcf128) {
484 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]485 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]486 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]487 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]488 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]489 return FPTOUINT_PPCF128_I128;
490 }
491 return UNKNOWN_LIBCALL;
492}
493
494/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
495/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]496RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]497 if (OpVT == MVT::i32) {
498 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]499 return SINTTOFP_I32_F32;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]500 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]501 return SINTTOFP_I32_F64;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]502 if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]503 return SINTTOFP_I32_F80;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]504 if (RetVT == MVT::f128)
505 return SINTTOFP_I32_F128;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]506 if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]507 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]508 } else if (OpVT == MVT::i64) {
509 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]510 return SINTTOFP_I64_F32;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]511 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]512 return SINTTOFP_I64_F64;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]513 if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]514 return SINTTOFP_I64_F80;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]515 if (RetVT == MVT::f128)
516 return SINTTOFP_I64_F128;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]517 if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]518 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]519 } else if (OpVT == MVT::i128) {
520 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]521 return SINTTOFP_I128_F32;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]522 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]523 return SINTTOFP_I128_F64;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]524 if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]525 return SINTTOFP_I128_F80;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]526 if (RetVT == MVT::f128)
527 return SINTTOFP_I128_F128;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]528 if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]529 return SINTTOFP_I128_PPCF128;
530 }
531 return UNKNOWN_LIBCALL;
532}
533
534/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
535/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]536RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]537 if (OpVT == MVT::i32) {
538 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]539 return UINTTOFP_I32_F32;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]540 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]541 return UINTTOFP_I32_F64;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]542 if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]543 return UINTTOFP_I32_F80;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]544 if (RetVT == MVT::f128)
545 return UINTTOFP_I32_F128;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]546 if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]547 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]548 } else if (OpVT == MVT::i64) {
549 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]550 return UINTTOFP_I64_F32;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]551 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]552 return UINTTOFP_I64_F64;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]553 if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]554 return UINTTOFP_I64_F80;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]555 if (RetVT == MVT::f128)
556 return UINTTOFP_I64_F128;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]557 if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]558 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]559 } else if (OpVT == MVT::i128) {
560 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]561 return UINTTOFP_I128_F32;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]562 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]563 return UINTTOFP_I128_F64;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]564 if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]565 return UINTTOFP_I128_F80;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]566 if (RetVT == MVT::f128)
567 return UINTTOFP_I128_F128;
Craig Toppera1b3c032012-12-19 06:39:17 +0000[diff] [blame]568 if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]569 return UINTTOFP_I128_PPCF128;
570 }
571 return UNKNOWN_LIBCALL;
572}
573
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]574/// InitCmpLibcallCCs - Set default comparison libcall CC.
575///
576static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
577 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
578 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
579 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]580 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]581 CCs[RTLIB::UNE_F32] = ISD::SETNE;
582 CCs[RTLIB::UNE_F64] = ISD::SETNE;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]583 CCs[RTLIB::UNE_F128] = ISD::SETNE;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]584 CCs[RTLIB::OGE_F32] = ISD::SETGE;
585 CCs[RTLIB::OGE_F64] = ISD::SETGE;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]586 CCs[RTLIB::OGE_F128] = ISD::SETGE;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]587 CCs[RTLIB::OLT_F32] = ISD::SETLT;
588 CCs[RTLIB::OLT_F64] = ISD::SETLT;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]589 CCs[RTLIB::OLT_F128] = ISD::SETLT;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]590 CCs[RTLIB::OLE_F32] = ISD::SETLE;
591 CCs[RTLIB::OLE_F64] = ISD::SETLE;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]592 CCs[RTLIB::OLE_F128] = ISD::SETLE;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]593 CCs[RTLIB::OGT_F32] = ISD::SETGT;
594 CCs[RTLIB::OGT_F64] = ISD::SETGT;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]595 CCs[RTLIB::OGT_F128] = ISD::SETGT;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]596 CCs[RTLIB::UO_F32] = ISD::SETNE;
597 CCs[RTLIB::UO_F64] = ISD::SETNE;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]598 CCs[RTLIB::UO_F128] = ISD::SETNE;
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]599 CCs[RTLIB::O_F32] = ISD::SETEQ;
600 CCs[RTLIB::O_F64] = ISD::SETEQ;
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]601 CCs[RTLIB::O_F128] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]602}
603
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]604/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]605TargetLowering::TargetLowering(const TargetMachine &tm,
606 const TargetLoweringObjectFile *tlof)
Micah Villmow3574eca2012-10-08 16:38:25 +0000[diff] [blame]607 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]608 // All operations default to being supported.
609 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]610 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]611 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]612 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]613 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]614
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]615 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]616 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]617 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]618 for (unsigned IM = (unsigned)ISD::PRE_INC;
619 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]620 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
621 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]622 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]623
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]624 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]625 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
626 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]627 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]628
629 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]630 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]631
632 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]633 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]634 // to optimize expansions for certain constants.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]635 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]636 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
637 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
638 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]639 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]640
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]641 // These library functions default to expand.
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]642 setOperationAction(ISD::FLOG , MVT::f16, Expand);
643 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
644 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
645 setOperationAction(ISD::FEXP , MVT::f16, Expand);
646 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
650 setOperationAction(ISD::FRINT, MVT::f16, Expand);
651 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Owen Anderson4a4fdf32011-12-08 19:32:14 +0000[diff] [blame]652 setOperationAction(ISD::FLOG , MVT::f32, Expand);
653 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
654 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
655 setOperationAction(ISD::FEXP , MVT::f32, Expand);
656 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
657 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
658 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
659 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
660 setOperationAction(ISD::FRINT, MVT::f32, Expand);
661 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Dan Gohmane3376ec2011-12-20 00:02:33 +0000[diff] [blame]662 setOperationAction(ISD::FLOG , MVT::f64, Expand);
663 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
664 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
665 setOperationAction(ISD::FEXP , MVT::f64, Expand);
666 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
667 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
668 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
669 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
670 setOperationAction(ISD::FRINT, MVT::f64, Expand);
671 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Tim Northover24d315d2013-01-08 17:09:59 +0000[diff] [blame^]672 setOperationAction(ISD::FLOG , MVT::f128, Expand);
673 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
674 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
675 setOperationAction(ISD::FEXP , MVT::f128, Expand);
676 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
677 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
678 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
679 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
680 setOperationAction(ISD::FRINT, MVT::f128, Expand);
681 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]682
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]683 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]684 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]685
Shuxin Yang970755e2012-10-19 20:11:16 +0000[diff] [blame]686 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
687 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
688 //
689 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
690
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]691 IsLittleEndian = TD->isLittleEndian();
Micah Villmow7d661462012-10-09 16:06:12 +0000[diff] [blame]692 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]693 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]694 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]695 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]696 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
697 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]698 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]699 UseUnderscoreSetJmp = false;
700 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]701 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]702 IntDivIsCheap = false;
703 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]704 JumpIsExpensive = false;
Benjamin Krameraaf723d2012-05-05 12:49:14 +0000[diff] [blame]705 predictableSelectIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]706 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]707 ExceptionPointerRegister = 0;
708 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]709 BooleanContents = UndefinedBooleanContent;
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]710 BooleanVectorContents = UndefinedBooleanContent;
Dan Gohman8c2d2702011-10-24 17:45:02 +0000[diff] [blame]711 SchedPreferenceInfo = Sched::ILP;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]712 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]713 JumpBufAlignment = 0;
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000[diff] [blame]714 MinFunctionAlignment = 0;
715 PrefFunctionAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]716 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]717 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]718 ShouldFoldAtomicFences = false;
Eli Friedman26689ac2011-08-03 21:06:02 +0000[diff] [blame]719 InsertFencesForAtomic = false;
Evan Cheng769951f2012-07-02 22:39:56 +0000[diff] [blame]720 SupportJumpTables = true;
Sebastian Pop1a37d7e2012-09-25 20:35:36 +0000[diff] [blame]721 MinimumJumpTableEntries = 4;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]722
723 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]724 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]725 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]726}
727
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]728TargetLowering::~TargetLowering() {
729 delete &TLOF;
730}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]731
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]732MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
Micah Villmow7d661462012-10-09 16:06:12 +0000[diff] [blame]733 return MVT::getIntegerVT(8*TD->getPointerSize(0));
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]734}
735
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]736/// canOpTrap - Returns true if the operation can trap for the value type.
737/// VT must be a legal type.
738bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
739 assert(isTypeLegal(VT));
740 switch (Op) {
741 default:
742 return false;
743 case ISD::FDIV:
744 case ISD::FREM:
745 case ISD::SDIV:
746 case ISD::UDIV:
747 case ISD::SREM:
748 case ISD::UREM:
749 return true;
750 }
751}
752
753
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]754static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]755 unsigned &NumIntermediates,
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]756 MVT &RegisterVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]757 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]758 // Figure out the right, legal destination reg to copy into.
759 unsigned NumElts = VT.getVectorNumElements();
760 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]761
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]762 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]763
764 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]765 // could break down into LHS/RHS like LegalizeDAG does.
766 if (!isPowerOf2_32(NumElts)) {
767 NumVectorRegs = NumElts;
768 NumElts = 1;
769 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]770
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]771 // Divide the input until we get to a supported size. This will always
772 // end with a scalar if the target doesn't support vectors.
773 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
774 NumElts >>= 1;
775 NumVectorRegs <<= 1;
776 }
777
778 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]779
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]780 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
781 if (!TLI->isTypeLegal(NewVT))
782 NewVT = EltTy;
783 IntermediateVT = NewVT;
784
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]785 unsigned NewVTSize = NewVT.getSizeInBits();
786
787 // Convert sizes such as i33 to i64.
788 if (!isPowerOf2_32(NewVTSize))
789 NewVTSize = NextPowerOf2(NewVTSize);
790
Patrik Hagglunddfcf33a2012-12-19 11:48:16 +0000[diff] [blame]791 MVT DestVT = TLI->getRegisterType(NewVT);
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]792 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]793 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]794 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]795
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]796 // Otherwise, promotion or legal types use the same number of registers as
797 // the vector decimated to the appropriate level.
798 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]799}
800
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]801/// isLegalRC - Return true if the value types that can be represented by the
802/// specified register class are all legal.
803bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
804 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
805 I != E; ++I) {
806 if (isTypeLegal(*I))
807 return true;
808 }
809 return false;
810}
811
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]812/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]813/// of the register class for the specified type and its associated "cost".
814std::pair<const TargetRegisterClass*, uint8_t>
Patrik Hagglund03405572012-12-19 11:30:36 +0000[diff] [blame]815TargetLowering::findRepresentativeClass(MVT VT) const {
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]816 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
Patrik Hagglund03405572012-12-19 11:30:36 +0000[diff] [blame]817 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]818 if (!RC)
819 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]820
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]821 // Compute the set of all super-register classes.
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]822 BitVector SuperRegRC(TRI->getNumRegClasses());
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]823 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]824 SuperRegRC.setBitsInMask(RCI.getMask());
825
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]826 // Find the first legal register class with the largest spill size.
827 const TargetRegisterClass *BestRC = RC;
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]828 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
829 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]830 // We want the largest possible spill size.
831 if (SuperRC->getSize() <= BestRC->getSize())
832 continue;
833 if (!isLegalRC(SuperRC))
834 continue;
835 BestRC = SuperRC;
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]836 }
Jakob Stoklund Olesen7fc4d9c2012-05-04 22:53:28 +0000[diff] [blame]837 return std::make_pair(BestRC, 1);
Jakob Stoklund Olesene3ee49f2012-05-04 02:19:22 +0000[diff] [blame]838}
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]839
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]840/// computeRegisterProperties - Once all of the register classes are added,
841/// this allows us to compute derived properties we expose.
842void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]843 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]844 "Too many value types for ValueTypeActions to hold!");
845
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]846 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]847 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]848 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]849 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]850 }
851 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]852 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]853
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]854 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]855 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]856 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]857 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]858
859 // Every integer value type larger than this largest register takes twice as
860 // many registers to represent as the previous ValueType.
Patrik Hägglundd5f03182012-11-23 08:35:04 +0000[diff] [blame]861 for (unsigned ExpandedReg = LargestIntReg + 1;
862 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]863 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]864 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
865 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Patrik Hägglundd5f03182012-11-23 08:35:04 +0000[diff] [blame]866 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
867 TypeExpandInteger);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]868 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]869
870 // Inspect all of the ValueType's smaller than the largest integer
871 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]872 unsigned LegalIntReg = LargestIntReg;
873 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]874 IntReg >= (unsigned)MVT::i1; --IntReg) {
Patrik Hagglund009e1e22012-12-13 20:42:43 +0000[diff] [blame]875 MVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]876 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]877 LegalIntReg = IntReg;
878 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]879 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Roman Divacky59324292012-09-05 22:26:57 +0000[diff] [blame]880 (const MVT::SimpleValueType)LegalIntReg;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]881 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]882 }
883 }
884
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]885 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]886 if (!isTypeLegal(MVT::ppcf128)) {
887 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
888 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
889 TransformToType[MVT::ppcf128] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]890 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]891 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]892
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]893 // Decide how to handle f64. If the target does not have native f64 support,
894 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]895 if (!isTypeLegal(MVT::f64)) {
896 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
897 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
898 TransformToType[MVT::f64] = MVT::i64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]899 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]900 }
901
902 // Decide how to handle f32. If the target does not have native support for
903 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]904 if (!isTypeLegal(MVT::f32)) {
905 if (isTypeLegal(MVT::f64)) {
906 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
907 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
908 TransformToType[MVT::f32] = MVT::f64;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]909 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]910 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]911 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
912 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
913 TransformToType[MVT::f32] = MVT::i32;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]914 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]915 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]916 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]917
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]918 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]919 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
920 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]921 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]922 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]923
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]924 // Determine if there is a legal wider type. If so, we should promote to
925 // that wider vector type.
Patrik Hagglundff012772012-12-19 11:42:00 +0000[diff] [blame]926 MVT EltVT = VT.getVectorElementType();
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]927 unsigned NElts = VT.getVectorNumElements();
Justin Holewinski3d200252012-11-29 14:26:24 +0000[diff] [blame]928 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]929 bool IsLegalWiderType = false;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]930 // First try to promote the elements of integer vectors. If no legal
931 // promotion was found, fallback to the widen-vector method.
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]932 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
Patrik Hagglundff012772012-12-19 11:42:00 +0000[diff] [blame]933 MVT SVT = (MVT::SimpleValueType)nVT;
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]934 // Promote vectors of integers to vectors with the same number
935 // of elements, with a wider element type.
936 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
937 && SVT.getVectorNumElements() == NElts &&
938 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
939 TransformToType[i] = SVT;
940 RegisterTypeForVT[i] = SVT;
941 NumRegistersForVT[i] = 1;
942 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
943 IsLegalWiderType = true;
944 break;
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]945 }
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]946 }
Nadav Rotemb6fbec32011-06-01 12:51:46 +0000[diff] [blame]947
Nadav Rotemf1c025d2011-06-04 20:32:01 +0000[diff] [blame]948 if (IsLegalWiderType) continue;
949
950 // Try to widen the vector.
951 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
Patrik Hagglundff012772012-12-19 11:42:00 +0000[diff] [blame]952 MVT SVT = (MVT::SimpleValueType)nVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]953 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]954 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]955 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]956 TransformToType[i] = SVT;
957 RegisterTypeForVT[i] = SVT;
958 NumRegistersForVT[i] = 1;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]959 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]960 IsLegalWiderType = true;
961 break;
962 }
963 }
964 if (IsLegalWiderType) continue;
965 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]966
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]967 MVT IntermediateVT;
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]968 MVT RegisterVT;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]969 unsigned NumIntermediates;
970 NumRegistersForVT[i] =
971 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
972 RegisterVT, this);
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]973 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]974
Patrik Hagglundff012772012-12-19 11:42:00 +0000[diff] [blame]975 MVT NVT = VT.getPow2VectorType();
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]976 if (NVT == VT) {
977 // Type is already a power of 2. The default action is to split.
978 TransformToType[i] = MVT::Other;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]979 unsigned NumElts = VT.getVectorNumElements();
980 ValueTypeActions.setTypeAction(VT,
981 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]982 } else {
983 TransformToType[i] = NVT;
Nadav Rotemb6aacae2011-05-28 17:57:14 +0000[diff] [blame]984 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]985 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]986 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]987
988 // Determine the 'representative' register class for each value type.
989 // An representative register class is the largest (meaning one which is
990 // not a sub-register class / subreg register class) legal register class for
991 // a group of value types. For example, on i386, i8, i16, and i32
992 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]993 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]994 const TargetRegisterClass* RRC;
995 uint8_t Cost;
996 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
997 RepRegClassForVT[i] = RRC;
998 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]999 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]1000}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]1001
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]1002const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
1003 return NULL;
1004}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1005
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]1006EVT TargetLowering::getSetCCResultType(EVT VT) const {
1007 assert(!VT.isVector() && "No default SetCC type for vectors!");
Micah Villmow7d661462012-10-09 16:06:12 +0000[diff] [blame]1008 return getPointerTy(0).SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]1009}
1010
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]1011MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
1012 return MVT::i32; // return the default value
1013}
1014
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]1015/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]1016/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1017/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1018/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1019///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]1020/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1021/// register. It also returns the VT and quantity of the intermediate values
1022/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1023///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1024unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1025 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1026 unsigned &NumIntermediates,
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]1027 MVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1028 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1029
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1030 // If there is a wider vector type with the same element type as this one,
Nadav Rotemdb346162012-04-21 20:08:32 +0000[diff] [blame]1031 // or a promoted vector type that has the same number of elements which
1032 // are wider, then we should convert to that legal vector type.
1033 // This handles things like <2 x float> -> <4 x float> and
1034 // <4 x i1> -> <4 x i32>.
1035 LegalizeTypeAction TA = getTypeAction(Context, VT);
1036 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]1037 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1038 if (isTypeLegal(RegisterEVT)) {
1039 IntermediateVT = RegisterEVT;
1040 RegisterVT = RegisterEVT.getSimpleVT();
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1041 NumIntermediates = 1;
1042 return 1;
1043 }
1044 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1045
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1046 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1047 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1048
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1049 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1050
1051 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]1052 // could break down into LHS/RHS like LegalizeDAG does.
1053 if (!isPowerOf2_32(NumElts)) {
1054 NumVectorRegs = NumElts;
1055 NumElts = 1;
1056 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1057
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1058 // Divide the input until we get to a supported size. This will always
1059 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1060 while (NumElts > 1 && !isTypeLegal(
1061 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1062 NumElts >>= 1;
1063 NumVectorRegs <<= 1;
1064 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1065
1066 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1067
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1068 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]1069 if (!isTypeLegal(NewVT))
1070 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1071 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1072
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]1073 MVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]1074 RegisterVT = DestVT;
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1075 unsigned NewVTSize = NewVT.getSizeInBits();
1076
1077 // Convert sizes such as i33 to i64.
1078 if (!isPowerOf2_32(NewVTSize))
1079 NewVTSize = NextPowerOf2(NewVTSize);
1080
Patrik Hagglundee211d22012-12-19 11:53:21 +0000[diff] [blame]1081 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1082 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1083
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]1084 // Otherwise, promotion or legal types use the same number of registers as
1085 // the vector decimated to the appropriate level.
1086 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]1087}
1088
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1089/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1090/// type of the given function. This does not require a DAG or a return value,
1091/// and is suitable for use before any DAGs for the function are constructed.
1092/// TODO: Move this out of TargetLowering.cpp.
Bill Wendling8b62abd2012-12-30 13:01:51 +0000[diff] [blame]1093void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1094 SmallVectorImpl<ISD::OutputArg> &Outs,
Eli Friedman2db0e9e2012-05-25 00:09:29 +0000[diff] [blame]1095 const TargetLowering &TLI) {
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1096 SmallVector<EVT, 4> ValueVTs;
1097 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1098 unsigned NumValues = ValueVTs.size();
1099 if (NumValues == 0) return;
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1100
1101 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1102 EVT VT = ValueVTs[j];
1103 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1104
Bill Wendling8b62abd2012-12-30 13:01:51 +0000[diff] [blame]1105 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1106 ExtendKind = ISD::SIGN_EXTEND;
Bill Wendling8b62abd2012-12-30 13:01:51 +0000[diff] [blame]1107 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1108 ExtendKind = ISD::ZERO_EXTEND;
1109
1110 // FIXME: C calling convention requires the return type to be promoted to
1111 // at least 32-bit. But this is not necessary for non-C calling
1112 // conventions. The frontend should mark functions whose return values
1113 // require promoting with signext or zeroext attributes.
1114 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
Patrik Hagglunddfcf33a2012-12-19 11:48:16 +0000[diff] [blame]1115 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1116 if (VT.bitsLT(MinVT))
1117 VT = MinVT;
1118 }
1119
1120 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
Patrik Hagglunddfcf33a2012-12-19 11:48:16 +0000[diff] [blame]1121 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1122
1123 // 'inreg' on function refers to return value
1124 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Bill Wendling8b62abd2012-12-30 13:01:51 +0000[diff] [blame]1125 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1126 Flags.setInReg();
1127
1128 // Propagate extension type if any
Bill Wendling8b62abd2012-12-30 13:01:51 +0000[diff] [blame]1129 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1130 Flags.setSExt();
Bill Wendling8b62abd2012-12-30 13:01:51 +0000[diff] [blame]1131 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1132 Flags.setZExt();
1133
Bill Wendlinge853d2e2012-09-19 23:35:21 +0000[diff] [blame]1134 for (unsigned i = 0; i < NumParts; ++i)
Manman Ren0a1544d2012-11-01 23:49:58 +0000[diff] [blame]1135 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0));
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]1136 }
1137}
1138
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1139/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1140/// function arguments in the caller parameter area. This is the actual
1141/// alignment, not its logarithm.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]1142unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1143 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1144}
1145
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1146/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1147/// current function. The returned value is a member of the
1148/// MachineJumpTableInfo::JTEntryKind enum.
1149unsigned TargetLowering::getJumpTableEncoding() const {
1150 // In non-pic modes, just use the address of a block.
1151 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1152 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1153
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1154 // In PIC mode, if the target supports a GPRel32 directive, use it.
1155 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1156 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1157
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1158 // Otherwise, use a label difference.
1159 return MachineJumpTableInfo::EK_LabelDifference32;
1160}
1161
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1162SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1163 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1164 // If our PIC model is GP relative, use the global offset table as the base.
Akira Hatanaka787c3fd2012-04-09 20:32:12 +0000[diff] [blame]1165 unsigned JTEncoding = getJumpTableEncoding();
1166
1167 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1168 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
Micah Villmow7d661462012-10-09 16:06:12 +0000[diff] [blame]1169 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
Akira Hatanaka787c3fd2012-04-09 20:32:12 +0000[diff] [blame]1170
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1171 return Table;
1172}
1173
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1174/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1175/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1176/// MCExpr.
1177const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1178TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1179 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1180 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1181 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1182}
1183
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1184bool
1185TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1186 // Assume that everything is safe in static mode.
1187 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1188 return true;
1189
1190 // In dynamic-no-pic mode, assume that known defined values are safe.
1191 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1192 GA &&
1193 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1194 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1195 return true;
1196
1197 // Otherwise assume nothing is safe.
1198 return false;
1199}
1200
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1201//===----------------------------------------------------------------------===//
Chandler Carruthaeef83c2013-01-07 01:37:14 +0000[diff] [blame]1202// TargetTransformInfo Helpers
1203//===----------------------------------------------------------------------===//
1204
1205int TargetLowering::InstructionOpcodeToISD(unsigned Opcode) const {
1206 enum InstructionOpcodes {
1207#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1208#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1209#include "llvm/IR/Instruction.def"
1210 };
1211 switch (static_cast<InstructionOpcodes>(Opcode)) {
1212 case Ret: return 0;
1213 case Br: return 0;
1214 case Switch: return 0;
1215 case IndirectBr: return 0;
1216 case Invoke: return 0;
1217 case Resume: return 0;
1218 case Unreachable: return 0;
1219 case Add: return ISD::ADD;
1220 case FAdd: return ISD::FADD;
1221 case Sub: return ISD::SUB;
1222 case FSub: return ISD::FSUB;
1223 case Mul: return ISD::MUL;
1224 case FMul: return ISD::FMUL;
1225 case UDiv: return ISD::UDIV;
1226 case SDiv: return ISD::UDIV;
1227 case FDiv: return ISD::FDIV;
1228 case URem: return ISD::UREM;
1229 case SRem: return ISD::SREM;
1230 case FRem: return ISD::FREM;
1231 case Shl: return ISD::SHL;
1232 case LShr: return ISD::SRL;
1233 case AShr: return ISD::SRA;
1234 case And: return ISD::AND;
1235 case Or: return ISD::OR;
1236 case Xor: return ISD::XOR;
1237 case Alloca: return 0;
1238 case Load: return ISD::LOAD;
1239 case Store: return ISD::STORE;
1240 case GetElementPtr: return 0;
1241 case Fence: return 0;
1242 case AtomicCmpXchg: return 0;
1243 case AtomicRMW: return 0;
1244 case Trunc: return ISD::TRUNCATE;
1245 case ZExt: return ISD::ZERO_EXTEND;
1246 case SExt: return ISD::SIGN_EXTEND;
1247 case FPToUI: return ISD::FP_TO_UINT;
1248 case FPToSI: return ISD::FP_TO_SINT;
1249 case UIToFP: return ISD::UINT_TO_FP;
1250 case SIToFP: return ISD::SINT_TO_FP;
1251 case FPTrunc: return ISD::FP_ROUND;
1252 case FPExt: return ISD::FP_EXTEND;
1253 case PtrToInt: return ISD::BITCAST;
1254 case IntToPtr: return ISD::BITCAST;
1255 case BitCast: return ISD::BITCAST;
1256 case ICmp: return ISD::SETCC;
1257 case FCmp: return ISD::SETCC;
1258 case PHI: return 0;
1259 case Call: return 0;
1260 case Select: return ISD::SELECT;
1261 case UserOp1: return 0;
1262 case UserOp2: return 0;
1263 case VAArg: return 0;
1264 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1265 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1266 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1267 case ExtractValue: return ISD::MERGE_VALUES;
1268 case InsertValue: return ISD::MERGE_VALUES;
1269 case LandingPad: return 0;
1270 }
1271
1272 llvm_unreachable("Unknown instruction type encountered!");
1273}
1274
1275std::pair<unsigned, MVT>
1276TargetLowering::getTypeLegalizationCost(Type *Ty) const {
1277 LLVMContext &C = Ty->getContext();
1278 EVT MTy = getValueType(Ty);
1279
1280 unsigned Cost = 1;
1281 // We keep legalizing the type until we find a legal kind. We assume that
1282 // the only operation that costs anything is the split. After splitting
1283 // we need to handle two types.
1284 while (true) {
1285 LegalizeKind LK = getTypeConversion(C, MTy);
1286
1287 if (LK.first == TypeLegal)
1288 return std::make_pair(Cost, MTy.getSimpleVT());
1289
1290 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1291 Cost *= 2;
1292
1293 // Keep legalizing the type.
1294 MTy = LK.second;
1295 }
1296}
1297
1298//===----------------------------------------------------------------------===//
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1299// Optimization Methods
1300//===----------------------------------------------------------------------===//
1301
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1302/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1303/// specified instruction is a constant integer. If so, check to see if there
1304/// are any bits set in the constant that are not demanded. If so, shrink the
1305/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1306bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1307 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1308 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1309
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1310 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1311 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1312 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1313 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1314 case ISD::AND:
1315 case ISD::OR: {
1316 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1317 if (!C) return false;
1318
1319 if (Op.getOpcode() == ISD::XOR &&
1320 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1321 return false;
1322
1323 // if we can expand it to have all bits set, do it
1324 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1325 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1326 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1327 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1328 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1329 VT));
1330 return CombineTo(Op, New);
1331 }
1332
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1333 break;
1334 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1335 }
1336
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1337 return false;
1338}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1339
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1340/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1341/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1342/// cast, but it could be generalized for targets with other types of
1343/// implicit widening casts.
1344bool
1345TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1346 unsigned BitWidth,
1347 const APInt &Demanded,
1348 DebugLoc dl) {
1349 assert(Op.getNumOperands() == 2 &&
1350 "ShrinkDemandedOp only supports binary operators!");
1351 assert(Op.getNode()->getNumValues() == 1 &&
1352 "ShrinkDemandedOp only supports nodes with one result!");
1353
1354 // Don't do this if the node has another user, which may require the
1355 // full value.
1356 if (!Op.getNode()->hasOneUse())
1357 return false;
1358
1359 // Search for the smallest integer type with free casts to and from
1360 // Op's type. For expedience, just check power-of-2 integer types.
1361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Nadav Rotembf5a2c62012-12-19 07:39:08 +0000[diff] [blame]1362 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
1363 unsigned SmallVTBits = DemandedSize;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1364 if (!isPowerOf2_32(SmallVTBits))
1365 SmallVTBits = NextPowerOf2(SmallVTBits);
1366 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1367 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1368 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1369 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1370 // We found a type with free casts.
1371 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1372 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1373 Op.getNode()->getOperand(0)),
1374 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1375 Op.getNode()->getOperand(1)));
Nadav Rotembf5a2c62012-12-19 07:39:08 +0000[diff] [blame]1376 bool NeedZext = DemandedSize > SmallVTBits;
1377 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
1378 dl, Op.getValueType(), X);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1379 return CombineTo(Op, Z);
1380 }
1381 }
1382 return false;
1383}
1384
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1385/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Chad Rosier8c1ec5a2011-06-11 02:27:46 +0000[diff] [blame]1386/// DemandedMask bits of the result of Op are ever used downstream. If we can
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1387/// use this information to simplify Op, create a new simplified DAG node and
1388/// return true, returning the original and new nodes in Old and New. Otherwise,
1389/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1390/// the expression (used to simplify the caller). The KnownZero/One bits may
1391/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1392bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1393 const APInt &DemandedMask,
1394 APInt &KnownZero,
1395 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1396 TargetLoweringOpt &TLO,
1397 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1398 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1399 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1400 "Mask size mismatches value type size!");
1401 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1402 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1403
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1404 // Don't know anything.
1405 KnownZero = KnownOne = APInt(BitWidth, 0);
1406
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1407 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1408 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1409 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1410 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1411 // simplify things downstream.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1412 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1413 return false;
1414 }
1415 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1416 // just set the NewMask to all bits.
1417 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1418 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1419 // Not demanding any bits from Op.
1420 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1421 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1422 return false;
1423 } else if (Depth == 6) { // Limit search depth.
1424 return false;
1425 }
1426
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1427 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1428 switch (Op.getOpcode()) {
1429 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1430 // We know all of the bits for a constant!
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1431 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1432 KnownZero = ~KnownOne;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1433 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1434 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1435 // If the RHS is a constant, check to see if the LHS would be zero without
1436 // using the bits from the RHS. Below, we use knowledge about the RHS to
1437 // simplify the LHS, here we're using information from the LHS to simplify
1438 // the RHS.
1439 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1440 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1441 // Do not increment Depth here; that can cause an infinite loop.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1442 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1443 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1444 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1445 return TLO.CombineTo(Op, Op.getOperand(0));
1446 // If any of the set bits in the RHS are known zero on the LHS, shrink
1447 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1448 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1449 return true;
1450 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1451
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1452 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1453 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1454 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1455 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1456 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1457 KnownZero2, KnownOne2, TLO, Depth+1))
1458 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1459 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1460
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1461 // If all of the demanded bits are known one on one side, return the other.
1462 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1463 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1464 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1465 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1466 return TLO.CombineTo(Op, Op.getOperand(1));
1467 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1468 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1469 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1470 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1471 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1472 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1473 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1474 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1475 return true;
1476
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1477 // Output known-1 bits are only known if set in both the LHS & RHS.
1478 KnownOne &= KnownOne2;
1479 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1480 KnownZero |= KnownZero2;
1481 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1482 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1483 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1484 KnownOne, TLO, Depth+1))
1485 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1486 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1487 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1488 KnownZero2, KnownOne2, TLO, Depth+1))
1489 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1490 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1491
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1492 // If all of the demanded bits are known zero on one side, return the other.
1493 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1494 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1495 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1496 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1497 return TLO.CombineTo(Op, Op.getOperand(1));
1498 // If all of the potentially set bits on one side are known to be set on
1499 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1500 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1501 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1502 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1503 return TLO.CombineTo(Op, Op.getOperand(1));
1504 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1505 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1506 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1507 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1508 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1509 return true;
1510
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1511 // Output known-0 bits are only known if clear in both the LHS & RHS.
1512 KnownZero &= KnownZero2;
1513 // Output known-1 are known to be set if set in either the LHS | RHS.
1514 KnownOne |= KnownOne2;
1515 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1516 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1517 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1518 KnownOne, TLO, Depth+1))
1519 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1520 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1521 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1522 KnownOne2, TLO, Depth+1))
1523 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1524 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1525
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1526 // If all of the demanded bits are known zero on one side, return the other.
1527 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1528 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1529 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1530 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1531 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1532 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1533 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1534 return true;
1535
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1536 // If all of the unknown bits are known to be zero on one side or the other
1537 // (but not both) turn this into an *inclusive* or.
Sylvestre Ledru94c22712012-09-27 10:14:43 +0000[diff] [blame]1538 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1539 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1540 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1541 Op.getOperand(0),
1542 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1543
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1544 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1545 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1546 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1547 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1548
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1549 // If all of the demanded bits on one side are known, and all of the set
1550 // bits on that side are also known to be set on the other side, turn this
1551 // into an AND, as we know the bits will be cleared.
Sylvestre Ledru94c22712012-09-27 10:14:43 +0000[diff] [blame]1552 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Joel Jonesd16ce172012-04-17 22:23:10 +0000[diff] [blame]1553 // NB: it is okay if more bits are known than are requested
1554 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1555 if (KnownOne == KnownOne2) { // set bits are the same on both sides
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1556 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1557 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1558 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1559 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1560 }
1561 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1562
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1563 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1564 // for XOR, we prefer to force bits to 1 if they will make a -1.
1565 // if we can't force bits, try to shrink constant
1566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1567 APInt Expanded = C->getAPIntValue() | (~NewMask);
1568 // if we can expand it to have all bits set, do it
1569 if (Expanded.isAllOnesValue()) {
1570 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1571 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1572 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1573 TLO.DAG.getConstant(Expanded, VT));
1574 return TLO.CombineTo(Op, New);
1575 }
1576 // if it already has all the bits set, nothing to change
1577 // but don't shrink either!
1578 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1579 return true;
1580 }
1581 }
1582
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1583 KnownZero = KnownZeroOut;
1584 KnownOne = KnownOneOut;
1585 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1586 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1587 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1588 KnownOne, TLO, Depth+1))
1589 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1590 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1591 KnownOne2, TLO, Depth+1))
1592 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1593 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1594 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1595
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1596 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1597 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1598 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1599
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1600 // Only known if known in both the LHS and RHS.
1601 KnownOne &= KnownOne2;
1602 KnownZero &= KnownZero2;
1603 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1604 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1605 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1606 KnownOne, TLO, Depth+1))
1607 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1608 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1609 KnownOne2, TLO, Depth+1))
1610 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1611 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1612 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1613
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1614 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1615 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1616 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1617
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1618 // Only known if known in both the LHS and RHS.
1619 KnownOne &= KnownOne2;
1620 KnownZero &= KnownZero2;
1621 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1622 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1623 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1624 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1625 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1626
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1627 // If the shift count is an invalid immediate, don't do anything.
1628 if (ShAmt >= BitWidth)
1629 break;
1630
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1631 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1632 // single shift. We can do this if the bottom bits (which are shifted
1633 // out) are never demanded.
1634 if (InOp.getOpcode() == ISD::SRL &&
1635 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1636 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1637 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1638 unsigned Opc = ISD::SHL;
1639 int Diff = ShAmt-C1;
1640 if (Diff < 0) {
1641 Diff = -Diff;
1642 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1643 }
1644
1645 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1646 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1647 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1648 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1649 InOp.getOperand(0), NewSA));
1650 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1651 }
1652
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1653 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1654 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1655 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1656
1657 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1658 // are not demanded. This will likely allow the anyext to be folded away.
1659 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1660 SDValue InnerOp = InOp.getNode()->getOperand(0);
1661 EVT InnerVT = InnerOp.getValueType();
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1662 unsigned InnerBits = InnerVT.getSizeInBits();
1663 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1664 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1665 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1666 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1667 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1668 SDValue NarrowShl =
1669 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1670 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1671 return
1672 TLO.CombineTo(Op,
1673 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1674 NarrowShl));
1675 }
1676 }
1677
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1678 KnownZero <<= SA->getZExtValue();
1679 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1680 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1681 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1682 }
1683 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1684 case ISD::SRL:
1685 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1686 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1687 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1688 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1689 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1690
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1691 // If the shift count is an invalid immediate, don't do anything.
1692 if (ShAmt >= BitWidth)
1693 break;
1694
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1695 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1696 // single shift. We can do this if the top bits (which are shifted out)
1697 // are never demanded.
1698 if (InOp.getOpcode() == ISD::SHL &&
1699 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1700 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1701 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1702 unsigned Opc = ISD::SRL;
1703 int Diff = ShAmt-C1;
1704 if (Diff < 0) {
1705 Diff = -Diff;
1706 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1707 }
1708
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1709 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1710 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1711 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1712 InOp.getOperand(0), NewSA));
1713 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1714 }
1715
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1716 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1717 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1718 KnownZero, KnownOne, TLO, Depth+1))
1719 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1720 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1721 KnownZero = KnownZero.lshr(ShAmt);
1722 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1723
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1724 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1725 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1726 }
1727 break;
1728 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1729 // If this is an arithmetic shift right and only the low-bit is set, we can
1730 // always convert this into a logical shr, even if the shift amount is
1731 // variable. The low bit of the shift cannot be an input sign bit unless
1732 // the shift amount is >= the size of the datatype, which is undefined.
Eli Friedman2dd03532011-12-09 01:16:26 +0000[diff] [blame]1733 if (NewMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1734 return TLO.CombineTo(Op,
1735 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1736 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1737
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1738 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1739 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1740 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1741
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1742 // If the shift count is an invalid immediate, don't do anything.
1743 if (ShAmt >= BitWidth)
1744 break;
1745
1746 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1747
1748 // If any of the demanded bits are produced by the sign extension, we also
1749 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1750 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1751 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1752 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1753
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1754 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1755 KnownZero, KnownOne, TLO, Depth+1))
1756 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1757 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1758 KnownZero = KnownZero.lshr(ShAmt);
1759 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1760
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1761 // Handle the sign bit, adjusted to where it is now in the mask.
1762 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1763
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1764 // If the input sign bit is known to be zero, or if none of the top bits
1765 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1766 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1767 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1768 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1769 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1770 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1771 KnownOne |= HighBits;
1772 }
1773 }
1774 break;
1775 case ISD::SIGN_EXTEND_INREG: {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1776 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1777
1778 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1779 // If we only care about the highest bit, don't bother shifting right.
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1780 if (MsbMask == DemandedMask) {
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1781 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1782 SDValue InOp = Op.getOperand(0);
Eli Friedmand49db362012-01-31 01:08:03 +0000[diff] [blame]1783
1784 // Compute the correct shift amount type, which must be getShiftAmountTy
1785 // for scalar types after legalization.
1786 EVT ShiftAmtTy = Op.getValueType();
1787 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1788 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1789
1790 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1791 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1792 Op.getValueType(), InOp, ShiftAmt));
1793 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1794
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1795 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1796 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1797 APInt NewBits =
1798 APInt::getHighBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1799 BitWidth - ExVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1800
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1801 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1802 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1803 return TLO.CombineTo(Op, Op.getOperand(0));
1804
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1805 APInt InSignBit =
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1806 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1807 APInt InputDemandedBits =
1808 APInt::getLowBitsSet(BitWidth,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1809 ExVT.getScalarType().getSizeInBits()) &
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1810 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1811
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1812 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1813 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1814 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1815
1816 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1817 KnownZero, KnownOne, TLO, Depth+1))
1818 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1819 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1820
1821 // If the sign bit of the input is known set or clear, then we know the
1822 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1823
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1824 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1825 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1826 return TLO.CombineTo(Op,
Nadav Rotemcc616562012-01-15 19:27:55 +0000[diff] [blame]1827 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1828
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1829 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1830 KnownOne |= NewBits;
1831 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1832 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1833 KnownZero &= ~NewBits;
1834 KnownOne &= ~NewBits;
1835 }
1836 break;
1837 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1838 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1839 unsigned OperandBitWidth =
1840 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1841 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1842
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1843 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1844 APInt NewBits =
1845 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1846 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1847 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1848 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1849 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1850
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1851 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1852 KnownZero, KnownOne, TLO, Depth+1))
1853 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1854 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1855 KnownZero = KnownZero.zext(BitWidth);
1856 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1857 KnownZero |= NewBits;
1858 break;
1859 }
1860 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1861 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1862 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1863 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1864 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1865 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1866
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1867 // If none of the top bits are demanded, convert this into an any_extend.
1868 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1869 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1870 Op.getValueType(),
1871 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1872
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1873 // Since some of the sign extended bits are demanded, we know that the sign
1874 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1875 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1876 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1877 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1878
1879 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1880 KnownOne, TLO, Depth+1))
1881 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1882 KnownZero = KnownZero.zext(BitWidth);
1883 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1884
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1885 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1886 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1887 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1888 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1889 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1890
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1891 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1892 if (KnownOne.intersects(InSignBit)) {
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1893 KnownOne |= NewBits;
1894 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1895 } else { // Otherwise, top bits aren't known.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]1896 assert((KnownOne & NewBits) == 0);
1897 assert((KnownZero & NewBits) == 0);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1898 }
1899 break;
1900 }
1901 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1902 unsigned OperandBitWidth =
1903 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1904 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1905 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1906 KnownZero, KnownOne, TLO, Depth+1))
1907 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1908 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1909 KnownZero = KnownZero.zext(BitWidth);
1910 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1911 break;
1912 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1913 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1914 // Simplify the input, using demanded bit information, and compute the known
1915 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1916 unsigned OperandBitWidth =
1917 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1918 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1919 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1920 KnownZero, KnownOne, TLO, Depth+1))
1921 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1922 KnownZero = KnownZero.trunc(BitWidth);
1923 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1924
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1925 // If the input is only used by this truncate, see if we can shrink it based
1926 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1927 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1928 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1929 switch (In.getOpcode()) {
1930 default: break;
1931 case ISD::SRL:
1932 // Shrink SRL by a constant if none of the high bits shifted in are
1933 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1934 if (TLO.LegalTypes() &&
1935 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1936 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1937 // undesirable.
1938 break;
1939 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1940 if (!ShAmt)
1941 break;
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1942 SDValue Shift = In.getOperand(1);
1943 if (TLO.LegalTypes()) {
1944 uint64_t ShVal = ShAmt->getZExtValue();
1945 Shift =
1946 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1947 }
1948
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1949 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1950 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1951 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1952
1953 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1954 // None of the shifted in bits are needed. Add a truncate of the
1955 // shift input, then shift it.
1956 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1957 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1958 In.getOperand(0));
1959 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1960 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1961 NewTrunc,
Owen Anderson7adf8622011-04-13 23:22:23 +0000[diff] [blame]1962 Shift));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1963 }
1964 break;
1965 }
1966 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1967
1968 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1969 break;
1970 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1971 case ISD::AssertZext: {
Owen Anderson7ab15f62011-09-03 00:26:49 +0000[diff] [blame]1972 // AssertZext demands all of the high bits, plus any of the low bits
1973 // demanded by its users.
1974 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1975 APInt InMask = APInt::getLowBitsSet(BitWidth,
1976 VT.getSizeInBits());
1977 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1978 KnownZero, KnownOne, TLO, Depth+1))
1979 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1980 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1981
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1982 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1983 break;
1984 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1985 case ISD::BITCAST:
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1986 // If this is an FP->Int bitcast and if the sign bit is the only
1987 // thing demanded, turn this into a FGETSIGN.
Eli Friedmanca072a32011-12-15 02:07:20 +0000[diff] [blame]1988 if (!TLO.LegalOperations() &&
1989 !Op.getValueType().isVector() &&
Eli Friedman0948f0a2011-11-09 22:25:12 +0000[diff] [blame]1990 !Op.getOperand(0).getValueType().isVector() &&
Nadav Rotem0c3e6782011-06-12 14:56:55 +0000[diff] [blame]1991 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1992 Op.getOperand(0).getValueType().isFloatingPoint()) {
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]1993 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1994 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1995 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1996 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1997 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1998 // place. We expect the SHL to be eliminated by other optimizations.
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]1999 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Stuart Hastings57f1fde2011-06-06 16:44:31 +0000[diff] [blame]2000 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
2001 if (!OpVTLegal && OpVTSizeInBits > 32)
Stuart Hastings090bf192011-06-01 18:32:25 +0000[diff] [blame]2002 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2003 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Stuart Hastingsbdce3722011-06-01 14:04:17 +0000[diff] [blame]2004 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Stuart Hastings3dfc4b122011-05-19 18:48:20 +0000[diff] [blame]2005 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
2006 Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]2007 Sign, ShAmt));
2008 }
2009 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]2010 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]2011 case ISD::ADD:
2012 case ISD::MUL:
2013 case ISD::SUB: {
2014 // Add, Sub, and Mul don't demand any bits in positions beyond that
2015 // of the highest bit demanded of them.
2016 APInt LoMask = APInt::getLowBitsSet(BitWidth,
2017 BitWidth - NewMask.countLeadingZeros());
2018 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
2019 KnownOne2, TLO, Depth+1))
2020 return true;
2021 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
2022 KnownOne2, TLO, Depth+1))
2023 return true;
2024 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]2025 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]2026 return true;
2027 }
2028 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]2029 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]2030 // Just use ComputeMaskedBits to compute output bits.
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]2031 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]2032 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]2033 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2034
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]2035 // If we know the value of all of the demanded bits, return this as a
2036 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]2037 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]2038 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2039
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]2040 return false;
2041}
2042
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2043/// computeMaskedBitsForTargetNode - Determine which of the bits specified
2044/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]2045/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2046void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2047 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]2048 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]2049 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]2050 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]2051 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2052 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2053 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2054 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]2055 "Should use MaskedValueIsZero if you don't know whether Op"
2056 " is a target node!");
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]2057 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]2058}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2059
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]2060/// ComputeNumSignBitsForTargetNode - This method can be implemented by
2061/// targets that want to expose additional information about sign bits to the
2062/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2063unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]2064 unsigned Depth) const {
2065 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2066 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2067 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2068 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
2069 "Should use ComputeNumSignBits if you don't know whether Op"
2070 " is a target node!");
2071 return 1;
2072}
2073
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]2074/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
2075/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
2076/// determine which bit is set.
2077///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2078static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]2079 // A left-shift of a constant one will have exactly one bit set, because
2080 // shifting the bit off the end is undefined.
2081 if (Val.getOpcode() == ISD::SHL)
2082 if (ConstantSDNode *C =
2083 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
2084 if (C->getAPIntValue() == 1)
2085 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2086
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]2087 // Similarly, a right-shift of a constant sign-bit will have exactly
2088 // one bit set.
2089 if (Val.getOpcode() == ISD::SRL)
2090 if (ConstantSDNode *C =
2091 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
2092 if (C->getAPIntValue().isSignBit())
2093 return true;
2094
2095 // More could be done here, though the above checks are enough
2096 // to handle some common cases.
2097
2098 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2099 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]2100 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2101 APInt KnownZero, KnownOne;
Rafael Espindola26c8dcc2012-04-04 12:51:34 +0000[diff] [blame]2102 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2103 return (KnownZero.countPopulation() == BitWidth - 1) &&
2104 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2105}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]2106
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2107/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2108/// and cc. If it is unable to simplify it, return a null SDValue.
2109SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2110TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2111 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2112 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2113 SelectionDAG &DAG = DCI.DAG;
2114
2115 // These setcc operations always fold.
2116 switch (Cond) {
2117 default: break;
2118 case ISD::SETFALSE:
2119 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2120 case ISD::SETTRUE:
2121 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2122 }
2123
Chris Lattner7a2bdde2011-04-15 05:18:47 +0000[diff] [blame]2124 // Ensure that the constant occurs on the RHS, and fold constant
2125 // comparisons.
2126 if (isa<ConstantSDNode>(N0.getNode()))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2127 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2128
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2129 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]2130 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2131
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2132 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
2133 // equality comparison, then we're just comparing whether X itself is
2134 // zero.
2135 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
2136 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
2137 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2138 const APInt &ShAmt
2139 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2140 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2141 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
2142 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
2143 // (srl (ctlz x), 5) == 0 -> X != 0
2144 // (srl (ctlz x), 5) != 1 -> X != 0
2145 Cond = ISD::SETNE;
2146 } else {
2147 // (srl (ctlz x), 5) != 0 -> X == 0
2148 // (srl (ctlz x), 5) == 1 -> X == 0
2149 Cond = ISD::SETEQ;
2150 }
2151 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2152 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
2153 Zero, Cond);
2154 }
2155 }
2156
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]2157 SDValue CTPOP = N0;
2158 // Look through truncs that don't change the value of a ctpop.
2159 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
2160 CTPOP = N0.getOperand(0);
2161
2162 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]2163 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]2164 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
2165 EVT CTVT = CTPOP.getValueType();
2166 SDValue CTOp = CTPOP.getOperand(0);
2167
2168 // (ctpop x) u< 2 -> (x & x-1) == 0
2169 // (ctpop x) u> 1 -> (x & x-1) != 0
2170 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2171 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2172 DAG.getConstant(1, CTVT));
2173 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2174 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2175 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
2176 }
2177
Sylvestre Ledru94c22712012-09-27 10:14:43 +0000[diff] [blame]2178 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]2179 }
2180
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]2181 // (zext x) == C --> x == (trunc C)
2182 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
2183 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2184 unsigned MinBits = N0.getValueSizeInBits();
2185 SDValue PreZExt;
2186 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2187 // ZExt
2188 MinBits = N0->getOperand(0).getValueSizeInBits();
2189 PreZExt = N0->getOperand(0);
2190 } else if (N0->getOpcode() == ISD::AND) {
2191 // DAGCombine turns costly ZExts into ANDs
2192 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2193 if ((C->getAPIntValue()+1).isPowerOf2()) {
2194 MinBits = C->getAPIntValue().countTrailingOnes();
2195 PreZExt = N0->getOperand(0);
2196 }
2197 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2198 // ZEXTLOAD
2199 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2200 MinBits = LN0->getMemoryVT().getSizeInBits();
2201 PreZExt = N0;
2202 }
2203 }
2204
Benjamin Kramerd9b0b022012-06-02 10:20:22 +0000[diff] [blame]2205 // Make sure we're not losing bits from the constant.
Benjamin Kramere7cf0622011-04-22 18:47:44 +0000[diff] [blame]2206 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2207 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2208 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2209 // Will get folded away.
2210 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2211 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2212 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2213 }
2214 }
2215 }
2216
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2217 // If the LHS is '(and load, const)', the RHS is 0,
2218 // the test is for equality or unsigned, and all 1 bits of the const are
2219 // in the same partial word, see if we can shorten the load.
2220 if (DCI.isBeforeLegalize() &&
2221 N0.getOpcode() == ISD::AND && C1 == 0 &&
2222 N0.getNode()->hasOneUse() &&
2223 isa<LoadSDNode>(N0.getOperand(0)) &&
2224 N0.getOperand(0).getNode()->hasOneUse() &&
2225 isa<ConstantSDNode>(N0.getOperand(1))) {
2226 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2227 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2228 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2229 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2230 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2231 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2232 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2233 // 8 bits, but have to be careful...
2234 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2235 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2236 const APInt &Mask =
2237 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2238 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2239 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2240 for (unsigned offset=0; offset<origWidth/width; offset++) {
2241 if ((newMask & Mask) == Mask) {
2242 if (!TD->isLittleEndian())
2243 bestOffset = (origWidth/width - offset - 1) * (width/8);
2244 else
2245 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2246 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2247 bestWidth = width;
2248 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2249 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2250 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]2251 }
2252 }
2253 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2254 if (bestWidth) {
Chris Lattnerc0c7fca2011-04-14 04:12:47 +0000[diff] [blame]2255 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2256 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2257 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2258 SDValue Ptr = Lod->getBasePtr();
2259 if (bestOffset != 0)
2260 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2261 DAG.getConstant(bestOffset, PtrType));
2262 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2263 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]2264 Lod->getPointerInfo().getWithOffset(bestOffset),
Pete Cooperd752e0f2011-11-08 18:42:53 +0000[diff] [blame]2265 false, false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2266 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2267 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2268 DAG.getConstant(bestMask.trunc(bestWidth),
2269 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2270 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2271 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2272 }
2273 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2274
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2275 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2276 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2277 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2278
2279 // If the comparison constant has bits in the upper part, the
2280 // zero-extended value could never match.
2281 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2282 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2283 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2284 case ISD::SETUGT:
2285 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2286 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2287 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2288 case ISD::SETULE:
2289 case ISD::SETNE: return DAG.getConstant(1, VT);
2290 case ISD::SETGT:
2291 case ISD::SETGE:
2292 // True if the sign bit of C1 is set.
2293 return DAG.getConstant(C1.isNegative(), VT);
2294 case ISD::SETLT:
2295 case ISD::SETLE:
2296 // True if the sign bit of C1 isn't set.
2297 return DAG.getConstant(C1.isNonNegative(), VT);
2298 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]2299 break;
2300 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2301 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2302
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2303 // Otherwise, we can perform the comparison with the low bits.
2304 switch (Cond) {
2305 case ISD::SETEQ:
2306 case ISD::SETNE:
2307 case ISD::SETUGT:
2308 case ISD::SETUGE:
2309 case ISD::SETULT:
2310 case ISD::SETULE: {
Patrik Hagglund34525f92012-12-11 11:14:33 +0000[diff] [blame]2311 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2312 if (DCI.isBeforeLegalizeOps() ||
2313 (isOperationLegal(ISD::SETCC, newVT) &&
Patrik Hagglund9c5ab932012-12-19 10:09:26 +0000[diff] [blame]2314 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal))
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2315 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2316 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2317 Cond);
2318 break;
2319 }
2320 default:
2321 break; // todo, be more careful with signed comparisons
2322 }
2323 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2324 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2325 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2326 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2327 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2328 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2329
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2330 // If the constant doesn't fit into the number of bits for the source of
2331 // the sign extension, it is impossible for both sides to be equal.
2332 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2333 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2334
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2335 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2336 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2337 if (Op0Ty == ExtSrcTy) {
2338 ZextOp = N0.getOperand(0);
2339 } else {
2340 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2341 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2342 DAG.getConstant(Imm, Op0Ty));
2343 }
2344 if (!DCI.isCalledByLegalizer())
2345 DCI.AddToWorklist(ZextOp.getNode());
2346 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2347 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2348 DAG.getConstant(C1 & APInt::getLowBitsSet(
2349 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2350 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2351 ExtDstTy),
2352 Cond);
2353 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2354 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2355 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2356 if (N0.getOpcode() == ISD::SETCC &&
2357 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2358 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2359 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2360 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2361 // Invert the condition.
2362 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2363 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2364 N0.getOperand(0).getValueType().isInteger());
2365 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2366 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2367
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2368 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2369 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2370 N0.getOperand(0).getOpcode() == ISD::XOR &&
2371 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2372 isa<ConstantSDNode>(N0.getOperand(1)) &&
2373 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2374 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2375 // can only do this if the top bits are known zero.
2376 unsigned BitWidth = N0.getValueSizeInBits();
2377 if (DAG.MaskedValueIsZero(N0,
2378 APInt::getHighBitsSet(BitWidth,
2379 BitWidth-1))) {
2380 // Okay, get the un-inverted input value.
2381 SDValue Val;
2382 if (N0.getOpcode() == ISD::XOR)
2383 Val = N0.getOperand(0);
2384 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2385 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2386 N0.getOperand(0).getOpcode() == ISD::XOR);
2387 // ((X^1)&1)^1 -> X & 1
2388 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2389 N0.getOperand(0).getOperand(0),
2390 N0.getOperand(1));
2391 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2392
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2393 return DAG.getSetCC(dl, VT, Val, N1,
2394 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2395 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2396 } else if (N1C->getAPIntValue() == 1 &&
2397 (VT == MVT::i1 ||
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]2398 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2399 SDValue Op0 = N0;
2400 if (Op0.getOpcode() == ISD::TRUNCATE)
2401 Op0 = Op0.getOperand(0);
2402
2403 if ((Op0.getOpcode() == ISD::XOR) &&
2404 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2405 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2406 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2407 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2408 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2409 Cond);
Craig Topper40b4a812012-12-19 06:12:28 +0000[diff] [blame]2410 }
2411 if (Op0.getOpcode() == ISD::AND &&
2412 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2413 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2414 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2415 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2416 Op0 = DAG.getNode(ISD::AND, dl, VT,
2417 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2418 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2419 else if (Op0.getValueType().bitsLT(VT))
2420 Op0 = DAG.getNode(ISD::AND, dl, VT,
2421 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2422 DAG.getConstant(1, VT));
2423
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2424 return DAG.getSetCC(dl, VT, Op0,
2425 DAG.getConstant(0, Op0.getValueType()),
2426 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2427 }
Craig Topper40b4a812012-12-19 06:12:28 +0000[diff] [blame]2428 if (Op0.getOpcode() == ISD::AssertZext &&
2429 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
2430 return DAG.getSetCC(dl, VT, Op0,
2431 DAG.getConstant(0, Op0.getValueType()),
2432 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2433 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2434 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2435
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2436 APInt MinVal, MaxVal;
2437 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2438 if (ISD::isSignedIntSetCC(Cond)) {
2439 MinVal = APInt::getSignedMinValue(OperandBitSize);
2440 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2441 } else {
2442 MinVal = APInt::getMinValue(OperandBitSize);
2443 MaxVal = APInt::getMaxValue(OperandBitSize);
2444 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2445
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2446 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2447 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2448 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2449 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2450 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2451 DAG.getConstant(C1-1, N1.getValueType()),
2452 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2453 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2454
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2455 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2456 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2457 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2458 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2459 DAG.getConstant(C1+1, N1.getValueType()),
2460 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2461 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2462
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2463 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2464 return DAG.getConstant(0, VT); // X < MIN --> false
2465 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2466 return DAG.getConstant(1, VT); // X >= MIN --> true
2467 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2468 return DAG.getConstant(0, VT); // X > MAX --> false
2469 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2470 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2471
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2472 // Canonicalize setgt X, Min --> setne X, Min
2473 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2474 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2475 // Canonicalize setlt X, Max --> setne X, Max
2476 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2477 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2478
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2479 // If we have setult X, 1, turn it into seteq X, 0
2480 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2481 return DAG.getSetCC(dl, VT, N0,
2482 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2483 ISD::SETEQ);
2484 // If we have setugt X, Max-1, turn it into seteq X, Max
Craig Topper85022562012-12-19 06:43:58 +0000[diff] [blame]2485 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2486 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2487 DAG.getConstant(MaxVal, N0.getValueType()),
2488 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2489
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2490 // If we have "setcc X, C0", check to see if we can shrink the immediate
2491 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2492
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2493 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2494 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2495 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2496 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2497 DAG.getConstant(0, N1.getValueType()),
2498 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2499
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2500 // SETULT X, SINTMIN -> SETGT X, -1
2501 if (Cond == ISD::SETULT &&
2502 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2503 SDValue ConstMinusOne =
2504 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2505 N1.getValueType());
2506 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2507 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2508
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2509 // Fold bit comparisons when we can.
2510 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2511 (VT == N0.getValueType() ||
2512 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2513 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2514 if (ConstantSDNode *AndRHS =
2515 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Benjamin Kramerb97cebd2012-08-17 15:54:21 +0000[diff] [blame]2516 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2517 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2518 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2519 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2520 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2521 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2522 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2523 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2524 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2525 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2526 // (X & 8) == 8 --> (X & 8) >> 3
2527 // Perform the xform if C1 is a single bit.
2528 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2529 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2530 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2531 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2532 }
2533 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2534 }
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2535
Evan Chengb4d49592012-07-17 07:47:50 +0000[diff] [blame]2536 if (C1.getMinSignedBits() <= 64 &&
2537 !isLegalICmpImmediate(C1.getSExtValue())) {
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2538 // (X & -256) == 256 -> (X >> 8) == 1
2539 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2540 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2541 if (ConstantSDNode *AndRHS =
2542 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2543 const APInt &AndRHSC = AndRHS->getAPIntValue();
2544 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2545 unsigned ShiftBits = AndRHSC.countTrailingZeros();
Benjamin Kramerb97cebd2012-08-17 15:54:21 +0000[diff] [blame]2546 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2547 getPointerTy() : getShiftAmountTy(N0.getValueType());
2548 EVT CmpTy = N0.getValueType();
2549 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2550 DAG.getConstant(ShiftBits, ShiftTy));
2551 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2552 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2553 }
2554 }
Evan Chengf5c05392012-07-17 08:31:11 +0000[diff] [blame]2555 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2556 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2557 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2558 // X < 0x100000000 -> (X >> 32) < 1
2559 // X >= 0x100000000 -> (X >> 32) >= 1
2560 // X <= 0x0ffffffff -> (X >> 32) < 1
2561 // X > 0x0ffffffff -> (X >> 32) >= 1
2562 unsigned ShiftBits;
2563 APInt NewC = C1;
2564 ISD::CondCode NewCond = Cond;
2565 if (AdjOne) {
2566 ShiftBits = C1.countTrailingOnes();
2567 NewC = NewC + 1;
2568 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2569 } else {
2570 ShiftBits = C1.countTrailingZeros();
2571 }
2572 NewC = NewC.lshr(ShiftBits);
2573 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
Benjamin Kramerb97cebd2012-08-17 15:54:21 +0000[diff] [blame]2574 EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Evan Chengf5c05392012-07-17 08:31:11 +0000[diff] [blame]2575 getPointerTy() : getShiftAmountTy(N0.getValueType());
2576 EVT CmpTy = N0.getValueType();
2577 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2578 DAG.getConstant(ShiftBits, ShiftTy));
2579 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
2580 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2581 }
Evan Cheng70e10d32012-07-17 06:53:39 +0000[diff] [blame]2582 }
2583 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2584 }
2585
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2586 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2587 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2588 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2589 if (O.getNode()) return O;
2590 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2591 // If the RHS of an FP comparison is a constant, simplify it away in
2592 // some cases.
2593 if (CFP->getValueAPF().isNaN()) {
2594 // If an operand is known to be a nan, we can fold it.
2595 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2596 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2597 case 0: // Known false.
2598 return DAG.getConstant(0, VT);
2599 case 1: // Known true.
2600 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2601 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2602 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2603 }
2604 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2605
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2606 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2607 // constant if knowing that the operand is non-nan is enough. We prefer to
2608 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2609 // materialize 0.0.
2610 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2611 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2612
2613 // If the condition is not legal, see if we can find an equivalent one
2614 // which is legal.
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2615 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2616 // If the comparison was an awkward floating-point == or != and one of
2617 // the comparison operands is infinity or negative infinity, convert the
2618 // condition to a less-awkward <= or >=.
2619 if (CFP->getValueAPF().isInfinity()) {
2620 if (CFP->getValueAPF().isNegative()) {
2621 if (Cond == ISD::SETOEQ &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2622 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2623 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2624 if (Cond == ISD::SETUEQ &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2625 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2626 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2627 if (Cond == ISD::SETUNE &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2628 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2629 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2630 if (Cond == ISD::SETONE &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2631 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2632 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2633 } else {
2634 if (Cond == ISD::SETOEQ &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2635 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2636 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2637 if (Cond == ISD::SETUEQ &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2638 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2639 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2640 if (Cond == ISD::SETUNE &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2641 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2642 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2643 if (Cond == ISD::SETONE &&
Patrik Hagglundfdbeb052012-12-19 10:19:55 +0000[diff] [blame]2644 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2645 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2646 }
2647 }
2648 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2649 }
2650
2651 if (N0 == N1) {
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2652 // The sext(setcc()) => setcc() optimization relies on the appropriate
2653 // constant being emitted.
Nadav Roteme7576402012-09-06 11:13:55 +0000[diff] [blame]2654 uint64_t EqVal = 0;
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2655 switch (getBooleanContents(N0.getValueType().isVector())) {
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2656 case UndefinedBooleanContent:
2657 case ZeroOrOneBooleanContent:
2658 EqVal = ISD::isTrueWhenEqual(Cond);
2659 break;
2660 case ZeroOrNegativeOneBooleanContent:
2661 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2662 break;
2663 }
2664
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2665 // We can always fold X == X for integer setcc's.
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2666 if (N0.getValueType().isInteger()) {
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2667 return DAG.getConstant(EqVal, VT);
Chad Rosier9dbb0182012-04-03 20:11:24 +0000[diff] [blame]2668 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2669 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2670 if (UOF == 2) // FP operators that are undefined on NaNs.
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2671 return DAG.getConstant(EqVal, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2672 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
Duncan Sandse7de3b22012-07-05 09:32:46 +0000[diff] [blame]2673 return DAG.getConstant(EqVal, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2674 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2675 // if it is not already.
2676 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
Micah Villmow8c574be2012-07-31 18:07:43 +0000[diff] [blame]2677 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
Patrik Hagglund9c5ab932012-12-19 10:09:26 +0000[diff] [blame]2678 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2679 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2680 }
2681
2682 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2683 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2684 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2685 N0.getOpcode() == ISD::XOR) {
2686 // Simplify (X+Y) == (X+Z) --> Y == Z
2687 if (N0.getOpcode() == N1.getOpcode()) {
2688 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2689 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2690 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2691 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2692 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2693 // If X op Y == Y op X, try other combinations.
2694 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2695 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2696 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2697 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2698 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2699 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2700 }
2701 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2702
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2703 // If RHS is a legal immediate value for a compare instruction, we need
2704 // to be careful about increasing register pressure needlessly.
2705 bool LegalRHSImm = false;
2706
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2707 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2708 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2709 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2710 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2711 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2712 DAG.getConstant(RHSC->getAPIntValue()-
2713 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2714 N0.getValueType()), Cond);
2715 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2716
Sylvestre Ledru94c22712012-09-27 10:14:43 +0000[diff] [blame]2717 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2718 if (N0.getOpcode() == ISD::XOR)
2719 // If we know that all of the inverted bits are zero, don't bother
2720 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2721 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2722 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2723 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2724 DAG.getConstant(LHSR->getAPIntValue() ^
2725 RHSC->getAPIntValue(),
2726 N0.getValueType()),
2727 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2728 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2729
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2730 // Turn (C1-X) == C2 --> X == C1-C2
2731 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2732 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2733 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2734 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2735 DAG.getConstant(SUBC->getAPIntValue() -
2736 RHSC->getAPIntValue(),
2737 N0.getValueType()),
2738 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2739 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2740 }
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2741
2742 // Could RHSC fold directly into a compare?
2743 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2744 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2745 }
2746
2747 // Simplify (X+Z) == X --> Z == 0
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2748 // Don't do this if X is an immediate that can fold into a cmp
2749 // instruction and X+Z has other uses. It could be an induction variable
2750 // chain, and the transform would increase register pressure.
2751 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2752 if (N0.getOperand(0) == N1)
2753 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2754 DAG.getConstant(0, N0.getValueType()), Cond);
2755 if (N0.getOperand(1) == N1) {
2756 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2757 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2758 DAG.getConstant(0, N0.getValueType()), Cond);
Craig Topper85022562012-12-19 06:43:58 +0000[diff] [blame]2759 if (N0.getNode()->hasOneUse()) {
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2760 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2761 // (Z-X) == X --> Z == X<<1
2762 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2763 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Jakob Stoklund Olesen740cd652012-04-05 20:30:20 +0000[diff] [blame]2764 if (!DCI.isCalledByLegalizer())
2765 DCI.AddToWorklist(SH.getNode());
2766 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2767 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2768 }
2769 }
2770 }
2771
2772 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2773 N1.getOpcode() == ISD::XOR) {
2774 // Simplify X == (X+Z) --> Z == 0
Craig Topper85022562012-12-19 06:43:58 +0000[diff] [blame]2775 if (N1.getOperand(0) == N0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2776 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2777 DAG.getConstant(0, N1.getValueType()), Cond);
Craig Topper85022562012-12-19 06:43:58 +0000[diff] [blame]2778 if (N1.getOperand(1) == N0) {
2779 if (DAG.isCommutativeBinOp(N1.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2780 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2781 DAG.getConstant(0, N1.getValueType()), Cond);
Craig Topper85022562012-12-19 06:43:58 +0000[diff] [blame]2782 if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2783 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2784 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2785 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2786 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2787 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2788 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2789 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2790 }
2791 }
2792 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2793
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2794 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2795 // Note that where y is variable and is known to have at most
2796 // one bit set (for example, if it is z&1) we cannot do this;
2797 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2798 if (N0.getOpcode() == ISD::AND)
2799 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2800 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2801 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2802 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2803 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2804 }
2805 }
2806 if (N1.getOpcode() == ISD::AND)
2807 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2808 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2809 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2810 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2811 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2812 }
2813 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2814 }
2815
2816 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2817 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2818 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2819 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2820 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2821 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2822 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2823 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2824 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2825 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2826 break;
2827 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2828 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2829 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2830 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2831 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2832 Temp = DAG.getNOT(dl, N0, MVT::i1);
2833 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2834 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2835 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2836 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2837 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2838 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2839 Temp = DAG.getNOT(dl, N1, MVT::i1);
2840 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2841 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2842 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2843 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2844 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2845 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2846 Temp = DAG.getNOT(dl, N0, MVT::i1);
2847 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2848 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2849 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2850 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2851 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2852 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2853 Temp = DAG.getNOT(dl, N1, MVT::i1);
2854 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2855 break;
2856 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2857 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2858 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2859 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2860 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2861 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2862 }
2863 return N0;
2864 }
2865
2866 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2867 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2868}
2869
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2870/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2871/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2872bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2873 int64_t &Offset) const {
2874 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2875 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2876 GA = GASD->getGlobal();
2877 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2878 return true;
2879 }
2880
2881 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2882 SDValue N1 = N->getOperand(0);
2883 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2884 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2885 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2886 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2887 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2888 return true;
2889 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2890 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2891 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2892 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2893 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2894 return true;
2895 }
2896 }
2897 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2898
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2899 return false;
2900}
2901
2902
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2903SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2904PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2905 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2906 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2907}
2908
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2909//===----------------------------------------------------------------------===//
2910// Inline Assembler Implementation Methods
2911//===----------------------------------------------------------------------===//
2912
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2913
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2914TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2915TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2916 if (Constraint.size() == 1) {
2917 switch (Constraint[0]) {
2918 default: break;
2919 case 'r': return C_RegisterClass;
2920 case 'm': // memory
2921 case 'o': // offsetable
2922 case 'V': // not offsetable
2923 return C_Memory;
2924 case 'i': // Simple Integer or Relocatable Constant
2925 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2926 case 'E': // Floating Point Constant
2927 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2928 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2929 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2930 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2931 case 'I': // Target registers.
2932 case 'J':
2933 case 'K':
2934 case 'L':
2935 case 'M':
2936 case 'N':
2937 case 'O':
2938 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2939 case '<':
2940 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2941 return C_Other;
2942 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2943 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2944
2945 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2946 Constraint[Constraint.size()-1] == '}')
2947 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2948 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2949}
2950
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2951/// LowerXConstraint - try to replace an X constraint, which matches anything,
2952/// with another that has more specific requirements based on the type of the
2953/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2954const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2955 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2956 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2957 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2958 return "f"; // works for many targets
2959 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2960}
2961
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2962/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2963/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2964void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2965 std::string &Constraint,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2966 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2967 SelectionDAG &DAG) const {
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2968
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2969 if (Constraint.length() > 1) return;
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]2970
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]2971 char ConstraintLetter = Constraint[0];
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2972 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2973 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2974 case 'X': // Allows any operand; labels (basic block) use this.
2975 if (Op.getOpcode() == ISD::BasicBlock) {
2976 Ops.push_back(Op);
2977 return;
2978 }
2979 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2980 case 'i': // Simple Integer or Relocatable Constant
2981 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2982 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2983 // These operands are interested in values of the form (GV+C), where C may
2984 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2985 // is possible and fine if either GV or C are missing.
2986 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2987 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2988
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2989 // If we have "(add GV, C)", pull out GV/C
2990 if (Op.getOpcode() == ISD::ADD) {
2991 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2992 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2993 if (C == 0 || GA == 0) {
2994 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2995 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2996 }
2997 if (C == 0 || GA == 0)
2998 C = 0, GA = 0;
2999 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3000
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]3001 // If we find a valid operand, map to the TargetXXX version so that the
3002 // value itself doesn't get selected.
3003 if (GA) { // Either &GV or &GV+C
3004 if (ConstraintLetter != 'n') {
3005 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]3006 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3007 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]3008 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]3009 Op.getValueType(), Offs));
3010 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]3011 }
3012 }
3013 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]3014 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]3015 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]3016 // gcc prints these as sign extended. Sign extend value to 64 bits
3017 // now; without this it would get ZExt'd later in
3018 // ScheduleDAGSDNodes::EmitNode, which is very generic.
3019 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]3020 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]3021 return;
3022 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]3023 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]3024 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]3025 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]3026 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]3027}
3028
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3029std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]3030getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3031 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3032 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]3033 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]3034 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
3035
3036 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]3037 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3038
Hal Finkelca2dd362012-12-18 17:50:58 +0000[diff] [blame]3039 std::pair<unsigned, const TargetRegisterClass*> R =
3040 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3041
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3042 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]3043 const TargetRegisterInfo *RI = TM.getRegisterInfo();
3044 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3045 E = RI->regclass_end(); RCI != E; ++RCI) {
3046 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3047
3048 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]3049 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Jakob Stoklund Olesen22e8a362011-10-12 01:24:51 +0000[diff] [blame]3050 if (!isLegalRC(RC))
3051 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3052
3053 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3054 I != E; ++I) {
Hal Finkelca2dd362012-12-18 17:50:58 +0000[diff] [blame]3055 if (RegName.equals_lower(RI->getName(*I))) {
3056 std::pair<unsigned, const TargetRegisterClass*> S =
3057 std::make_pair(*I, RC);
3058
3059 // If this register class has the requested value type, return it,
3060 // otherwise keep searching and return the first class found
3061 // if no other is found which explicitly has the requested type.
3062 if (RC->hasType(VT))
3063 return S;
3064 else if (!R.second)
3065 R = S;
3066 }
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]3067 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]3068 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3069
Hal Finkelca2dd362012-12-18 17:50:58 +0000[diff] [blame]3070 return R;
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]3071}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3072
3073//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3074// Constraint Selection.
3075
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]3076/// isMatchingInputConstraint - Return true of this is an input operand that is
3077/// a matching constraint like "4".
3078bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]3079 assert(!ConstraintCode.empty() && "No known constraint!");
3080 return isdigit(ConstraintCode[0]);
3081}
3082
3083/// getMatchedOperand - If this is an input matching constraint, this method
3084/// returns the output operand it matches.
3085unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
3086 assert(!ConstraintCode.empty() && "No known constraint!");
3087 return atoi(ConstraintCode.c_str());
3088}
3089
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3090
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3091/// ParseConstraints - Split up the constraint string from the inline
3092/// assembly value into the specific constraints and their prefixes,
3093/// and also tie in the associated operand values.
3094/// If this returns an empty vector, and if the constraint string itself
3095/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3096TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3097 ImmutableCallSite CS) const {
3098 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3099 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3100 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3101 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3102
3103 // Do a prepass over the constraints, canonicalizing them, and building up the
3104 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3105 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3106 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3107
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3108 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3109 unsigned ResNo = 0; // ResNo - The result number of the next output.
3110
3111 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3112 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3113 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3114
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3115 // Update multiple alternative constraint count.
3116 if (OpInfo.multipleAlternatives.size() > maCount)
3117 maCount = OpInfo.multipleAlternatives.size();
3118
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3119 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3120
3121 // Compute the value type for each operand.
3122 switch (OpInfo.Type) {
3123 case InlineAsm::isOutput:
3124 // Indirect outputs just consume an argument.
3125 if (OpInfo.isIndirect) {
3126 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3127 break;
3128 }
3129
3130 // The return value of the call is this value. As such, there is no
3131 // corresponding argument.
3132 assert(!CS.getType()->isVoidTy() &&
3133 "Bad inline asm!");
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3134 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
Patrik Hagglundc698d3a2012-12-19 15:19:11 +0000[diff] [blame]3135 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3136 } else {
3137 assert(ResNo == 0 && "Asm only has one result!");
Patrik Hagglundc698d3a2012-12-19 15:19:11 +0000[diff] [blame]3138 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3139 }
3140 ++ResNo;
3141 break;
3142 case InlineAsm::isInput:
3143 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
3144 break;
3145 case InlineAsm::isClobber:
3146 // Nothing to do.
3147 break;
3148 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3149
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3150 if (OpInfo.CallOperandVal) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3151 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3152 if (OpInfo.isIndirect) {
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3153 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3154 if (!PtrTy)
3155 report_fatal_error("Indirect operand for inline asm not a pointer!");
3156 OpTy = PtrTy->getElementType();
3157 }
Eric Christopher362fee92011-06-17 20:41:29 +0000[diff] [blame]3158
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]3159 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3160 if (StructType *STy = dyn_cast<StructType>(OpTy))
Eric Christophercef81b72011-05-09 20:04:43 +0000[diff] [blame]3161 if (STy->getNumElements() == 1)
3162 OpTy = STy->getElementType(0);
3163
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3164 // If OpTy is not a single value, it may be a struct/union that we
3165 // can tile with integers.
3166 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
3167 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3168 switch (BitSize) {
3169 default: break;
3170 case 1:
3171 case 8:
3172 case 16:
3173 case 32:
3174 case 64:
3175 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]3176 OpInfo.ConstraintVT =
Patrik Hagglundc698d3a2012-12-19 15:19:11 +0000[diff] [blame]3177 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3178 break;
3179 }
Micah Villmow7d661462012-10-09 16:06:12 +0000[diff] [blame]3180 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
3181 OpInfo.ConstraintVT = MVT::getIntegerVT(
3182 8*TD->getPointerSize(PT->getAddressSpace()));
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3183 } else {
Patrik Hagglundc698d3a2012-12-19 15:19:11 +0000[diff] [blame]3184 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3185 }
3186 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3187 }
3188
3189 // If we have multiple alternative constraints, select the best alternative.
3190 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3191 if (maCount) {
3192 unsigned bestMAIndex = 0;
3193 int bestWeight = -1;
3194 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
3195 int weight = -1;
3196 unsigned maIndex;
3197 // Compute the sums of the weights for each alternative, keeping track
3198 // of the best (highest weight) one so far.
3199 for (maIndex = 0; maIndex < maCount; ++maIndex) {
3200 int weightSum = 0;
3201 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3202 cIndex != eIndex; ++cIndex) {
3203 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3204 if (OpInfo.Type == InlineAsm::isClobber)
3205 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3206
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3207 // If this is an output operand with a matching input operand,
3208 // look up the matching input. If their types mismatch, e.g. one
3209 // is an integer, the other is floating point, or their sizes are
3210 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3211 if (OpInfo.hasMatchingInput()) {
3212 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3213 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3214 if ((OpInfo.ConstraintVT.isInteger() !=
3215 Input.ConstraintVT.isInteger()) ||
3216 (OpInfo.ConstraintVT.getSizeInBits() !=
3217 Input.ConstraintVT.getSizeInBits())) {
3218 weightSum = -1; // Can't match.
3219 break;
3220 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3221 }
3222 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3223 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
3224 if (weight == -1) {
3225 weightSum = -1;
3226 break;
3227 }
3228 weightSum += weight;
3229 }
3230 // Update best.
3231 if (weightSum > bestWeight) {
3232 bestWeight = weightSum;
3233 bestMAIndex = maIndex;
3234 }
3235 }
3236
3237 // Now select chosen alternative in each constraint.
3238 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3239 cIndex != eIndex; ++cIndex) {
3240 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3241 if (cInfo.Type == InlineAsm::isClobber)
3242 continue;
3243 cInfo.selectAlternative(bestMAIndex);
3244 }
3245 }
3246 }
3247
3248 // Check and hook up tied operands, choose constraint code to use.
3249 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3250 cIndex != eIndex; ++cIndex) {
3251 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3252
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3253 // If this is an output operand with a matching input operand, look up the
3254 // matching input. If their types mismatch, e.g. one is an integer, the
3255 // other is floating point, or their sizes are different, flag it as an
3256 // error.
3257 if (OpInfo.hasMatchingInput()) {
3258 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3259
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3260 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Bill Wendling96cb1122012-07-19 00:04:14 +0000[diff] [blame]3261 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3262 getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3263 OpInfo.ConstraintVT);
3264 std::pair<unsigned, const TargetRegisterClass*> InputRC =
3265 getRegForInlineAsmConstraint(Input.ConstraintCode,
3266 Input.ConstraintVT);
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3267 if ((OpInfo.ConstraintVT.isInteger() !=
3268 Input.ConstraintVT.isInteger()) ||
Eric Christopher5427ede2011-07-14 20:13:52 +0000[diff] [blame]3269 (MatchRC.second != InputRC.second)) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3270 report_fatal_error("Unsupported asm: input constraint"
3271 " with a matching output constraint of"
3272 " incompatible type!");
3273 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3274 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3275
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3276 }
3277 }
3278
3279 return ConstraintOperands;
3280}
3281
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]3282
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3283/// getConstraintGenerality - Return an integer indicating how general CT
3284/// is.
3285static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3286 switch (CT) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3287 case TargetLowering::C_Other:
3288 case TargetLowering::C_Unknown:
3289 return 0;
3290 case TargetLowering::C_Register:
3291 return 1;
3292 case TargetLowering::C_RegisterClass:
3293 return 2;
3294 case TargetLowering::C_Memory:
3295 return 3;
3296 }
Chandler Carruth732f05c2012-01-10 18:08:01 +0000[diff] [blame]3297 llvm_unreachable("Invalid constraint type");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3298}
3299
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3300/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3301/// This object must already have been set up with the operand type
3302/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3303TargetLowering::ConstraintWeight
3304 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3305 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3306 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3307 if (maIndex >= (int)info.multipleAlternatives.size())
3308 rCodes = &info.Codes;
3309 else
3310 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3311 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3312
3313 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]3314 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3315 ConstraintWeight weight =
3316 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3317 if (weight > BestWeight)
3318 BestWeight = weight;
3319 }
3320
3321 return BestWeight;
3322}
3323
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3324/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3325/// This object must already have been set up with the operand type
3326/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3327TargetLowering::ConstraintWeight
3328 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3329 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3330 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3331 Value *CallOperandVal = info.CallOperandVal;
3332 // If we don't have a value, we can't do a match,
3333 // but allow it at the lowest weight.
3334 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3335 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3336 // Look at the constraint type.
3337 switch (*constraint) {
3338 case 'i': // immediate integer.
3339 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3340 if (isa<ConstantInt>(CallOperandVal))
3341 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3342 break;
3343 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3344 if (isa<GlobalValue>(CallOperandVal))
3345 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3346 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3347 case 'E': // immediate float if host format.
3348 case 'F': // immediate float.
3349 if (isa<ConstantFP>(CallOperandVal))
3350 weight = CW_Constant;
3351 break;
3352 case '<': // memory operand with autodecrement.
3353 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3354 case 'm': // memory operand.
3355 case 'o': // offsettable memory operand
3356 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3357 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3358 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3359 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3360 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3361 // note: Clang converts "g" to "imr".
3362 if (CallOperandVal->getType()->isIntegerTy())
3363 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3364 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3365 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3366 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]3367 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]3368 break;
3369 }
3370 return weight;
3371}
3372
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3373/// ChooseConstraint - If there are multiple different constraints that we
3374/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]3375/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3376/// Other -> immediates and magic values
3377/// Register -> one specific register
3378/// RegisterClass -> a group of regs
3379/// Memory -> memory
3380/// Ideally, we would pick the most specific constraint possible: if we have
3381/// something that fits into a register, we would pick it. The problem here
3382/// is that if we have something that could either be in a register or in
3383/// memory that use of the register could cause selection of *other*
3384/// operands to fail: they might only succeed if we pick memory. Because of
3385/// this the heuristic we use is:
3386///
3387/// 1) If there is an 'other' constraint, and if the operand is valid for
3388/// that constraint, use it. This makes us take advantage of 'i'
3389/// constraints when available.
3390/// 2) Otherwise, pick the most general constraint present. This prefers
3391/// 'm' over 'r', for example.
3392///
3393static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3394 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3395 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3396 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3397 unsigned BestIdx = 0;
3398 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3399 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3400
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3401 // Loop over the options, keeping track of the most general one.
3402 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3403 TargetLowering::ConstraintType CType =
3404 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3405
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3406 // If this is an 'other' constraint, see if the operand is valid for it.
3407 // For example, on X86 we might have an 'rI' constraint. If the operand
3408 // is an integer in the range [0..31] we want to use I (saving a load
3409 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3410 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3411 assert(OpInfo.Codes[i].size() == 1 &&
3412 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3413 std::vector<SDValue> ResultOps;
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]3414 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3415 ResultOps, *DAG);
3416 if (!ResultOps.empty()) {
3417 BestType = CType;
3418 BestIdx = i;
3419 break;
3420 }
3421 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3422
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3423 // Things with matching constraints can only be registers, per gcc
3424 // documentation. This mainly affects "g" constraints.
3425 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3426 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3427
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3428 // This constraint letter is more general than the previous one, use it.
3429 int Generality = getConstraintGenerality(CType);
3430 if (Generality > BestGenerality) {
3431 BestType = CType;
3432 BestIdx = i;
3433 BestGenerality = Generality;
3434 }
3435 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3436
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3437 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3438 OpInfo.ConstraintType = BestType;
3439}
3440
3441/// ComputeConstraintToUse - Determines the constraint code and constraint
3442/// type to use for the specific AsmOperandInfo, setting
3443/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3444void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3445 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3446 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3447 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3448
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3449 // Single-letter constraints ('r') are very common.
3450 if (OpInfo.Codes.size() == 1) {
3451 OpInfo.ConstraintCode = OpInfo.Codes[0];
3452 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3453 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3454 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3455 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3456
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3457 // 'X' matches anything.
3458 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3459 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3460 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3461 // the result, which is not what we want to look at; leave them alone.
3462 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3463 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3464 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3465 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3466 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3467
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3468 // Otherwise, try to resolve it to something we know about by looking at
3469 // the actual operand type.
3470 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3471 OpInfo.ConstraintCode = Repl;
3472 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3473 }
3474 }
3475}
3476
3477//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3478// Loop Strength Reduction hooks
3479//===----------------------------------------------------------------------===//
3480
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3481/// isLegalAddressingMode - Return true if the addressing mode represented
3482/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3483bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]3484 Type *Ty) const {
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3485 // The default implementation of this implements a conservative RISCy, r+r and
3486 // r+i addr mode.
3487
3488 // Allows a sign-extended 16-bit immediate field.
3489 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3490 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3491
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3492 // No global is ever allowed as a base.
3493 if (AM.BaseGV)
3494 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3495
3496 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3497 switch (AM.Scale) {
3498 case 0: // "r+i" or just "i", depending on HasBaseReg.
3499 break;
3500 case 1:
3501 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3502 return false;
3503 // Otherwise we have r+r or r+i.
3504 break;
3505 case 2:
3506 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3507 return false;
3508 // Allow 2*r as r+r.
3509 break;
3510 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3511
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3512 return true;
3513}
3514
Benjamin Kramer9c640302011-07-08 10:31:30 +0000[diff] [blame]3515/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3516/// with the multiplicative inverse of the constant.
3517SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3518 SelectionDAG &DAG) const {
3519 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3520 APInt d = C->getAPIntValue();
3521 assert(d != 0 && "Division by zero!");
3522
3523 // Shift the value upfront if it is even, so the LSB is one.
3524 unsigned ShAmt = d.countTrailingZeros();
3525 if (ShAmt) {
3526 // TODO: For UDIV use SRL instead of SRA.
3527 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3528 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3529 d = d.ashr(ShAmt);
3530 }
3531
3532 // Calculate the multiplicative inverse, using Newton's method.
3533 APInt t, xn = d;
3534 while ((t = d*xn) != 1)
3535 xn *= APInt(d.getBitWidth(), 2) - t;
3536
3537 Op2 = DAG.getConstant(xn, Op1.getValueType());
3538 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3539}
3540
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3541/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3542/// return a DAG expression to select that will generate the same value by
3543/// multiplying by a magic number. See:
3544/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3545SDValue TargetLowering::
3546BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
Eric Christopher9171fb92012-12-10 22:00:20 +0000[diff] [blame]3547 std::vector<SDNode*> *Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3548 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3549 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3550
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3551 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3552 // FIXME: We should be more aggressive here.
3553 if (!isTypeLegal(VT))
3554 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3555
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3556 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3557 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3558
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3559 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3560 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3561 SDValue Q;
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3562 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3563 isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3564 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3565 DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3566 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3567 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3568 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3569 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3570 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3571 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3572 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3573 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3574 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3575 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3576 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3577 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3578 }
3579 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3580 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3581 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3582 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3583 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3584 }
3585 // Shift right algebraic if shift value is nonzero
3586 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3587 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3588 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3589 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3590 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3591 }
3592 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3593 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3594 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3595 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3596 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3597 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3598 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3599}
3600
3601/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3602/// return a DAG expression to select that will generate the same value by
3603/// multiplying by a magic number. See:
3604/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3605SDValue TargetLowering::
3606BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
Eric Christopher9171fb92012-12-10 22:00:20 +0000[diff] [blame]3607 std::vector<SDNode*> *Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3608 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3609 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3610
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3611 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3612 // FIXME: We should be more aggressive here.
3613 if (!isTypeLegal(VT))
3614 return SDValue();
3615
3616 // FIXME: We should use a narrower constant when the upper
3617 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3618 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3619 APInt::mu magics = N1C.magicu();
3620
3621 SDValue Q = N->getOperand(0);
3622
3623 // If the divisor is even, we can avoid using the expensive fixup by shifting
3624 // the divided value upfront.
3625 if (magics.a != 0 && !N1C[0]) {
3626 unsigned Shift = N1C.countTrailingZeros();
3627 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3628 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3629 if (Created)
3630 Created->push_back(Q.getNode());
3631
3632 // Get magic number for the shifted divisor.
3633 magics = N1C.lshr(Shift).magicu(Shift);
3634 assert(magics.a == 0 && "Should use cheap fixup now");
3635 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3636
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3637 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3638 // FIXME: We should support doing a MUL in a wider type
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3639 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3640 isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3641 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Richard Osborne19a4daf2011-11-07 17:09:05 +0000[diff] [blame]3642 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3643 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3644 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3645 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3646 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3647 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3648 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3649 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3650
3651 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3652 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3653 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3654 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3655 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3656 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3657 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3658 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3659 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3660 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3661 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3662 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3663 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3664 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3665 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3666 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3667 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3668 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3669 }
3670}