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Scott Michel564427e2007-12-05 01:24:05 +00001//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Scott Michel564427e2007-12-05 01:24:05 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CellSPU-specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SPUSubtarget.h"
15#include "SPU.h"
Scott Michel564427e2007-12-05 01:24:05 +000016#include "SPUGenSubtarget.inc"
Kalle Raiskilac2ebfd42010-11-29 10:30:25 +000017#include "llvm/ADT/SmallVector.h"
18#include "SPURegisterInfo.h"
Scott Michel564427e2007-12-05 01:24:05 +000019
20using namespace llvm;
21
Daniel Dunbar3be03402009-08-02 22:11:08 +000022SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &FS) :
Scott Michel564427e2007-12-05 01:24:05 +000023 StackAlignment(16),
24 ProcDirective(SPU::DEFAULT_PROC),
25 UseLargeMem(false)
26{
27 // Should be the target SPU processor type. For now, since there's only
28 // one, simply default to the current "v0" default:
29 std::string default_cpu("v0");
30
31 // Parse features string.
32 ParseSubtargetFeatures(FS, default_cpu);
33}
34
35/// SetJITMode - This is called to inform the subtarget info that we are
36/// producing code for the JIT.
37void SPUSubtarget::SetJITMode() {
38}
Kalle Raiskilac2ebfd42010-11-29 10:30:25 +000039
40/// Enable PostRA scheduling for optimization levels -O2 and -O3.
41bool SPUSubtarget::enablePostRAScheduler(
42 CodeGenOpt::Level OptLevel,
43 TargetSubtarget::AntiDepBreakMode& Mode,
44 RegClassVector& CriticalPathRCs) const {
45 Mode = TargetSubtarget::ANTIDEP_CRITICAL;
46 // CriticalPathsRCs seems to be the set of
47 // RegisterClasses that antidep breakings are performed for.
48 // Do it for all register classes
49 CriticalPathRCs.clear();
50 CriticalPathRCs.push_back(&SPU::R8CRegClass);
51 CriticalPathRCs.push_back(&SPU::R16CRegClass);
52 CriticalPathRCs.push_back(&SPU::R32CRegClass);
53 CriticalPathRCs.push_back(&SPU::R32FPRegClass);
54 CriticalPathRCs.push_back(&SPU::R64CRegClass);
55 CriticalPathRCs.push_back(&SPU::VECREGRegClass);
56 return OptLevel >= CodeGenOpt::Default;
57}