Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 Register file, defining the registers themselves, |
| 11 | // aliases between the registers, and the register classes built out of the |
| 12 | // registers. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | // Register definitions... |
| 18 | // |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 19 | let Namespace = "X86" in { |
Chris Lattner | b228657 | 2004-09-14 04:17:02 +0000 | [diff] [blame] | 20 | |
| 21 | // In the register alias definitions below, we define which registers alias |
| 22 | // which others. We only specify which registers the small registers alias, |
| 23 | // because the register file generator is smart enough to figure out that |
| 24 | // AL aliases AX if we tell it that AX aliased AL (for example). |
| 25 | |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 26 | // Dwarf numbering is different for 32-bit and 64-bit, and there are |
| 27 | // variations by target as well. Currently the first entry is for X86-64, |
Anton Korobeynikov | 8eea339 | 2008-01-25 00:34:13 +0000 | [diff] [blame] | 28 | // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux |
| 29 | // and debug information on X86-32/Darwin) |
Dale Johannesen | 4542edc | 2007-11-07 21:48:35 +0000 | [diff] [blame] | 30 | |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 31 | // 8-bit registers |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 32 | // Low registers |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 33 | def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>; |
| 34 | def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>; |
| 35 | def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>; |
| 36 | def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 37 | |
| 38 | // X86-64 only |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 39 | def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>; |
| 40 | def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>; |
| 41 | def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>; |
| 42 | def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>; |
| 43 | def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>; |
| 44 | def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>; |
| 45 | def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>; |
| 46 | def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>; |
| 47 | def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>; |
| 48 | def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>; |
| 49 | def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>; |
| 50 | def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 51 | |
| 52 | // High registers X86-32 only |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 53 | def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>; |
| 54 | def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>; |
| 55 | def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>; |
| 56 | def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 57 | |
| 58 | // 16-bit registers |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 59 | def AX : RegisterWithSubRegs<"ax", [AH,AL]>, DwarfRegNum<[0, 0, 0]>; |
| 60 | def DX : RegisterWithSubRegs<"dx", [DH,DL]>, DwarfRegNum<[1, 2, 2]>; |
| 61 | def CX : RegisterWithSubRegs<"cx", [CH,CL]>, DwarfRegNum<[2, 1, 1]>; |
| 62 | def BX : RegisterWithSubRegs<"bx", [BH,BL]>, DwarfRegNum<[3, 3, 3]>; |
| 63 | def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>; |
| 64 | def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>; |
| 65 | def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>; |
| 66 | def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>; |
| 67 | def IP : Register<"ip">, DwarfRegNum<[16]>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 68 | |
| 69 | // X86-64 only |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 70 | def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>; |
| 71 | def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>; |
| 72 | def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>; |
| 73 | def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>; |
| 74 | def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>; |
| 75 | def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>; |
| 76 | def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>; |
| 77 | def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 78 | |
| 79 | // 32-bit registers |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 80 | def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>; |
| 81 | def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>; |
| 82 | def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>; |
| 83 | def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>; |
| 84 | def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>; |
| 85 | def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>; |
| 86 | def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>; |
| 87 | def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>; |
| 88 | def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 89 | |
| 90 | // X86-64 only |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 91 | def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>; |
| 92 | def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>; |
| 93 | def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>; |
| 94 | def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>; |
| 95 | def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>; |
| 96 | def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>; |
| 97 | def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>; |
| 98 | def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 99 | |
| 100 | // 64-bit registers, X86-64 only |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 101 | def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>; |
| 102 | def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>; |
| 103 | def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>; |
| 104 | def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>; |
| 105 | def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>; |
| 106 | def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>; |
| 107 | def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>; |
| 108 | def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 109 | |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 110 | def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>; |
| 111 | def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>; |
| 112 | def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>; |
| 113 | def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>; |
| 114 | def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>; |
| 115 | def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>; |
| 116 | def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>; |
| 117 | def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>; |
| 118 | def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>; |
Evan Cheng | aea20f5 | 2006-02-20 22:34:53 +0000 | [diff] [blame] | 119 | |
| 120 | // MMX Registers. These are actually aliased to ST0 .. ST7 |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 121 | def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>; |
| 122 | def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>; |
| 123 | def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>; |
| 124 | def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>; |
| 125 | def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>; |
| 126 | def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>; |
| 127 | def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>; |
| 128 | def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 129 | |
| 130 | // Pseudo Floating Point registers |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 131 | def FP0 : Register<"fp0">; |
| 132 | def FP1 : Register<"fp1">; |
| 133 | def FP2 : Register<"fp2">; |
| 134 | def FP3 : Register<"fp3">; |
| 135 | def FP4 : Register<"fp4">; |
| 136 | def FP5 : Register<"fp5">; |
| 137 | def FP6 : Register<"fp6">; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 138 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 139 | // XMM Registers, used by the various SSE instruction set extensions |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 140 | def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>; |
| 141 | def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>; |
| 142 | def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>; |
| 143 | def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>; |
| 144 | def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>; |
| 145 | def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>; |
| 146 | def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>; |
| 147 | def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 148 | |
| 149 | // X86-64 only |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 150 | def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>; |
| 151 | def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>; |
| 152 | def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>; |
| 153 | def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>; |
| 154 | def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>; |
| 155 | def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>; |
| 156 | def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>; |
| 157 | def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 158 | |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 159 | // Floating point stack registers |
Evan Cheng | ae270f6 | 2008-07-07 22:21:06 +0000 | [diff] [blame] | 160 | def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>; |
| 161 | def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>; |
| 162 | def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>; |
| 163 | def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>; |
| 164 | def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>; |
| 165 | def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>; |
| 166 | def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>; |
| 167 | def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>; |
Evan Cheng | 3054dde | 2007-09-11 19:53:28 +0000 | [diff] [blame] | 168 | |
| 169 | // Status flags register |
Evan Cheng | 599a6a8 | 2009-03-04 01:41:49 +0000 | [diff] [blame] | 170 | def EFLAGS : Register<"flags">; |
Rafael Espindola | 2a6411b | 2009-04-07 21:37:46 +0000 | [diff] [blame^] | 171 | |
| 172 | // Segment registers |
| 173 | def CS : Register<"cs">; |
| 174 | def DS : Register<"ds">; |
| 175 | def SS : Register<"ss">; |
| 176 | def ES : Register<"es">; |
| 177 | def FS : Register<"fs">; |
| 178 | def GS : Register<"gs">; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 179 | } |
| 180 | |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 181 | |
| 182 | //===----------------------------------------------------------------------===// |
| 183 | // Subregister Set Definitions... now that we have all of the pieces, define the |
| 184 | // sub registers for each register. |
| 185 | // |
| 186 | |
Christopher Lamb | 1fab4a6 | 2008-03-11 10:09:17 +0000 | [diff] [blame] | 187 | def x86_subreg_8bit : PatLeaf<(i32 1)>; |
| 188 | def x86_subreg_16bit : PatLeaf<(i32 2)>; |
| 189 | def x86_subreg_32bit : PatLeaf<(i32 3)>; |
| 190 | |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 191 | def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, |
| 192 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], |
| 193 | [AL, CL, DL, BL, SPL, BPL, SIL, DIL, |
| 194 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; |
| 195 | |
| 196 | // It's unclear if this subreg set is safe, given that not all registers |
| 197 | // in the class have an 'H' subreg. |
| 198 | // def : SubRegSet<2, [AX, CX, DX, BX], |
| 199 | // [AH, CH, DH, BH]>; |
| 200 | |
| 201 | def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, |
| 202 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], |
| 203 | [AL, CL, DL, BL, SPL, BPL, SIL, DIL, |
| 204 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; |
| 205 | |
| 206 | def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, |
| 207 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], |
| 208 | [AX, CX, DX, BX, SP, BP, SI, DI, |
| 209 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; |
| 210 | |
| 211 | |
| 212 | def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, |
| 213 | R8, R9, R10, R11, R12, R13, R14, R15], |
| 214 | [AL, CL, DL, BL, SPL, BPL, SIL, DIL, |
| 215 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; |
| 216 | |
| 217 | def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, |
| 218 | R8, R9, R10, R11, R12, R13, R14, R15], |
| 219 | [AX, CX, DX, BX, SP, BP, SI, DI, |
| 220 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; |
| 221 | |
| 222 | def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, |
| 223 | R8, R9, R10, R11, R12, R13, R14, R15], |
| 224 | [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, |
| 225 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>; |
| 226 | |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 227 | //===----------------------------------------------------------------------===// |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 228 | // Register Class Definitions... now that we have all of the pieces, define the |
| 229 | // top-level register classes. The order specified in the register list is |
| 230 | // implicitly defined to be the register allocation order. |
| 231 | // |
Chris Lattner | 0539313 | 2005-01-05 16:09:16 +0000 | [diff] [blame] | 232 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 233 | // List call-clobbered registers before callee-save registers. RBX, RBP, (and |
| 234 | // R12, R13, R14, and R15 for X86-64) are callee-save registers. |
| 235 | // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and |
| 236 | // R8B, ... R15B. |
Stuart Hastings | be362ab | 2008-11-19 17:19:35 +0000 | [diff] [blame] | 237 | // Allocate R12 and R13 last, as these require an extra byte when |
| 238 | // encoded in x86_64 instructions. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 239 | // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions, |
| 240 | def GR8 : RegisterClass<"X86", [i8], 8, |
| 241 | [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL, |
Stuart Hastings | be362ab | 2008-11-19 17:19:35 +0000 | [diff] [blame] | 242 | R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 243 | let MethodProtos = [{ |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 244 | iterator allocation_order_begin(const MachineFunction &MF) const; |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 245 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 246 | }]; |
| 247 | let MethodBodies = [{ |
Dan Gohman | d3f1849 | 2009-01-27 19:25:38 +0000 | [diff] [blame] | 248 | // Does the function dedicate RBP / EBP to being a frame ptr? |
| 249 | // If so, don't allocate SPL or BPL. |
| 250 | static const unsigned X86_GR8_AO_64_fp[] = { |
| 251 | X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, |
| 252 | X86::R8B, X86::R9B, X86::R10B, X86::R11B, |
| 253 | X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B |
| 254 | }; |
| 255 | // If not, just don't allocate SPL. |
| 256 | static const unsigned X86_GR8_AO_64[] = { |
| 257 | X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, |
| 258 | X86::R8B, X86::R9B, X86::R10B, X86::R11B, |
| 259 | X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL |
| 260 | }; |
| 261 | // In 32-mode, none of the 8-bit registers aliases EBP or ESP. |
| 262 | static const unsigned X86_GR8_AO_32[] = { |
| 263 | X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH |
| 264 | }; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 265 | |
| 266 | GR8Class::iterator |
| 267 | GR8Class::allocation_order_begin(const MachineFunction &MF) const { |
| 268 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 269 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 270 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 271 | if (!Subtarget.is64Bit()) |
| 272 | return X86_GR8_AO_32; |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 273 | else if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 274 | return X86_GR8_AO_64_fp; |
| 275 | else |
| 276 | return X86_GR8_AO_64; |
| 277 | } |
| 278 | |
| 279 | GR8Class::iterator |
| 280 | GR8Class::allocation_order_end(const MachineFunction &MF) const { |
| 281 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 282 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 283 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 284 | if (!Subtarget.is64Bit()) |
| 285 | return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned)); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 286 | else if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 287 | return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned)); |
| 288 | else |
| 289 | return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned)); |
| 290 | } |
| 291 | }]; |
| 292 | } |
| 293 | |
| 294 | |
| 295 | def GR16 : RegisterClass<"X86", [i16], 16, |
| 296 | [AX, CX, DX, SI, DI, BX, BP, SP, |
Stuart Hastings | be362ab | 2008-11-19 17:19:35 +0000 | [diff] [blame] | 297 | R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> { |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 298 | let SubRegClassList = [GR8]; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 299 | let MethodProtos = [{ |
| 300 | iterator allocation_order_begin(const MachineFunction &MF) const; |
| 301 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 302 | }]; |
| 303 | let MethodBodies = [{ |
Dan Gohman | d3f1849 | 2009-01-27 19:25:38 +0000 | [diff] [blame] | 304 | // Does the function dedicate RBP / EBP to being a frame ptr? |
| 305 | // If so, don't allocate SP or BP. |
| 306 | static const unsigned X86_GR16_AO_64_fp[] = { |
| 307 | X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, |
| 308 | X86::R8W, X86::R9W, X86::R10W, X86::R11W, |
| 309 | X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W |
| 310 | }; |
| 311 | static const unsigned X86_GR16_AO_32_fp[] = { |
| 312 | X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX |
| 313 | }; |
| 314 | // If not, just don't allocate SPL. |
| 315 | static const unsigned X86_GR16_AO_64[] = { |
| 316 | X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, |
| 317 | X86::R8W, X86::R9W, X86::R10W, X86::R11W, |
| 318 | X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP |
| 319 | }; |
| 320 | static const unsigned X86_GR16_AO_32[] = { |
| 321 | X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP |
| 322 | }; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 323 | |
| 324 | GR16Class::iterator |
| 325 | GR16Class::allocation_order_begin(const MachineFunction &MF) const { |
| 326 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 327 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 328 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 329 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 330 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 331 | return X86_GR16_AO_64_fp; |
| 332 | else |
| 333 | return X86_GR16_AO_64; |
| 334 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 335 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 336 | return X86_GR16_AO_32_fp; |
| 337 | else |
| 338 | return X86_GR16_AO_32; |
| 339 | } |
| 340 | } |
| 341 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 342 | GR16Class::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 343 | GR16Class::allocation_order_end(const MachineFunction &MF) const { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 344 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 345 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 346 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 347 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 348 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 349 | return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned)); |
| 350 | else |
| 351 | return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned)); |
| 352 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 353 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 354 | return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned)); |
| 355 | else |
| 356 | return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned)); |
| 357 | } |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 358 | } |
| 359 | }]; |
| 360 | } |
| 361 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 362 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 363 | def GR32 : RegisterClass<"X86", [i32], 32, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 364 | [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, |
Stuart Hastings | be362ab | 2008-11-19 17:19:35 +0000 | [diff] [blame] | 365 | R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> { |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 366 | let SubRegClassList = [GR8, GR16]; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 367 | let MethodProtos = [{ |
| 368 | iterator allocation_order_begin(const MachineFunction &MF) const; |
| 369 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 370 | }]; |
| 371 | let MethodBodies = [{ |
Dan Gohman | d3f1849 | 2009-01-27 19:25:38 +0000 | [diff] [blame] | 372 | // Does the function dedicate RBP / EBP to being a frame ptr? |
| 373 | // If so, don't allocate ESP or EBP. |
| 374 | static const unsigned X86_GR32_AO_64_fp[] = { |
| 375 | X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, |
| 376 | X86::R8D, X86::R9D, X86::R10D, X86::R11D, |
| 377 | X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D |
| 378 | }; |
| 379 | static const unsigned X86_GR32_AO_32_fp[] = { |
| 380 | X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX |
| 381 | }; |
| 382 | // If not, just don't allocate SPL. |
| 383 | static const unsigned X86_GR32_AO_64[] = { |
| 384 | X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, |
| 385 | X86::R8D, X86::R9D, X86::R10D, X86::R11D, |
| 386 | X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP |
| 387 | }; |
| 388 | static const unsigned X86_GR32_AO_32[] = { |
| 389 | X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP |
| 390 | }; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 391 | |
| 392 | GR32Class::iterator |
| 393 | GR32Class::allocation_order_begin(const MachineFunction &MF) const { |
| 394 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 395 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 396 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 397 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 398 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 399 | return X86_GR32_AO_64_fp; |
| 400 | else |
| 401 | return X86_GR32_AO_64; |
| 402 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 403 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 404 | return X86_GR32_AO_32_fp; |
| 405 | else |
| 406 | return X86_GR32_AO_32; |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | GR32Class::iterator |
| 411 | GR32Class::allocation_order_end(const MachineFunction &MF) const { |
| 412 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 413 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 414 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 415 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 416 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 417 | return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned)); |
| 418 | else |
| 419 | return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned)); |
| 420 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 421 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 422 | return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned)); |
| 423 | else |
| 424 | return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned)); |
| 425 | } |
| 426 | } |
| 427 | }]; |
| 428 | } |
| 429 | |
| 430 | |
| 431 | def GR64 : RegisterClass<"X86", [i64], 64, |
| 432 | [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, |
Stuart Hastings | be362ab | 2008-11-19 17:19:35 +0000 | [diff] [blame] | 433 | RBX, R14, R15, R12, R13, RBP, RSP]> { |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 434 | let SubRegClassList = [GR8, GR16, GR32]; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 435 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 436 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 437 | }]; |
| 438 | let MethodBodies = [{ |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 439 | GR64Class::iterator |
| 440 | GR64Class::allocation_order_end(const MachineFunction &MF) const { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 441 | const TargetMachine &TM = MF.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 442 | const TargetRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 204496d | 2008-03-11 07:16:00 +0000 | [diff] [blame] | 443 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 444 | if (!Subtarget.is64Bit()) |
| 445 | return begin(); // None of these are allocatable in 32-bit. |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 446 | if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 447 | return end()-2; // If so, don't allocate RSP or RBP |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 448 | else |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 449 | return end()-1; // If not, just don't allocate RSP |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 450 | } |
| 451 | }]; |
| 452 | } |
| 453 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 454 | |
Evan Cheng | a333b41 | 2007-08-09 18:05:17 +0000 | [diff] [blame] | 455 | // GR16, GR32 subclasses which contain registers that have GR8 sub-registers. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 456 | // These should only be used for 32-bit mode. |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 457 | def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> { |
Evan Cheng | a3231ba | 2007-08-09 22:25:35 +0000 | [diff] [blame] | 458 | let SubRegClassList = [GR8]; |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 459 | } |
| 460 | def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> { |
Evan Cheng | a3231ba | 2007-08-09 22:25:35 +0000 | [diff] [blame] | 461 | let SubRegClassList = [GR8, GR16]; |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 462 | } |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 463 | |
Dale Johannesen | 330169f | 2008-11-13 21:52:36 +0000 | [diff] [blame] | 464 | // A class to support the 'A' assembler constraint: EAX then EDX. |
Dale Johannesen | fb88f1f | 2008-11-14 18:10:48 +0000 | [diff] [blame] | 465 | def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>; |
Dale Johannesen | 330169f | 2008-11-13 21:52:36 +0000 | [diff] [blame] | 466 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 467 | // Scalar SSE2 floating point registers. |
| 468 | def FR32 : RegisterClass<"X86", [f32], 32, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 469 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 470 | XMM8, XMM9, XMM10, XMM11, |
| 471 | XMM12, XMM13, XMM14, XMM15]> { |
| 472 | let MethodProtos = [{ |
| 473 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 474 | }]; |
| 475 | let MethodBodies = [{ |
| 476 | FR32Class::iterator |
| 477 | FR32Class::allocation_order_end(const MachineFunction &MF) const { |
| 478 | const TargetMachine &TM = MF.getTarget(); |
| 479 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 480 | if (!Subtarget.is64Bit()) |
| 481 | return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. |
| 482 | else |
| 483 | return end(); |
| 484 | } |
| 485 | }]; |
| 486 | } |
| 487 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 488 | def FR64 : RegisterClass<"X86", [f64], 64, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 489 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 490 | XMM8, XMM9, XMM10, XMM11, |
| 491 | XMM12, XMM13, XMM14, XMM15]> { |
| 492 | let MethodProtos = [{ |
| 493 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 494 | }]; |
| 495 | let MethodBodies = [{ |
| 496 | FR64Class::iterator |
| 497 | FR64Class::allocation_order_end(const MachineFunction &MF) const { |
| 498 | const TargetMachine &TM = MF.getTarget(); |
| 499 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 500 | if (!Subtarget.is64Bit()) |
| 501 | return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. |
| 502 | else |
| 503 | return end(); |
| 504 | } |
| 505 | }]; |
| 506 | } |
| 507 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 508 | |
Chris Lattner | 45de191 | 2004-12-02 18:17:31 +0000 | [diff] [blame] | 509 | // FIXME: This sets up the floating point register files as though they are f64 |
| 510 | // values, though they really are f80 values. This will cause us to spill |
| 511 | // values as 64-bit quantities instead of 80-bit quantities, which is much much |
| 512 | // faster on common hardware. In reality, this should be controlled by a |
| 513 | // command line option or something. |
| 514 | |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 515 | def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; |
| 516 | def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; |
| 517 | def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 518 | |
Alkis Evlogimenos | 65cbfa0 | 2004-09-21 21:22:11 +0000 | [diff] [blame] | 519 | // Floating point stack registers (these are not allocatable by the |
| 520 | // register allocator - the floating point stackifier is responsible |
| 521 | // for transforming FPn allocations to STn registers) |
Chris Lattner | 8e6da15 | 2008-03-10 21:08:41 +0000 | [diff] [blame] | 522 | def RST : RegisterClass<"X86", [f80, f64, f32], 32, |
Chris Lattner | 03ba7b9 | 2005-08-19 18:51:57 +0000 | [diff] [blame] | 523 | [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 524 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 525 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 526 | }]; |
| 527 | let MethodBodies = [{ |
| 528 | RSTClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 529 | RSTClass::allocation_order_end(const MachineFunction &MF) const { |
Alkis Evlogimenos | 65cbfa0 | 2004-09-21 21:22:11 +0000 | [diff] [blame] | 530 | return begin(); |
| 531 | } |
| 532 | }]; |
| 533 | } |
Evan Cheng | aea20f5 | 2006-02-20 22:34:53 +0000 | [diff] [blame] | 534 | |
Evan Cheng | 933be33 | 2006-02-21 01:38:21 +0000 | [diff] [blame] | 535 | // Generic vector registers: VR64 and VR128. |
Dale Johannesen | a68f901 | 2008-06-24 22:01:44 +0000 | [diff] [blame] | 536 | def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64, |
Evan Cheng | 933be33 | 2006-02-21 01:38:21 +0000 | [diff] [blame] | 537 | [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; |
| 538 | def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 539 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 540 | XMM8, XMM9, XMM10, XMM11, |
| 541 | XMM12, XMM13, XMM14, XMM15]> { |
| 542 | let MethodProtos = [{ |
| 543 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 544 | }]; |
| 545 | let MethodBodies = [{ |
| 546 | VR128Class::iterator |
| 547 | VR128Class::allocation_order_end(const MachineFunction &MF) const { |
| 548 | const TargetMachine &TM = MF.getTarget(); |
| 549 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 550 | if (!Subtarget.is64Bit()) |
| 551 | return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. |
| 552 | else |
| 553 | return end(); |
| 554 | } |
| 555 | }]; |
| 556 | } |
Evan Cheng | 3054dde | 2007-09-11 19:53:28 +0000 | [diff] [blame] | 557 | |
| 558 | // Status flags registers. |
Evan Cheng | dcfa73f | 2007-09-19 01:36:39 +0000 | [diff] [blame] | 559 | def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> { |
| 560 | let CopyCost = -1; // Don't allow copying of status registers. |
| 561 | } |