Akira Hatanaka | fd89e6f | 2012-09-27 02:05:42 +0000 | [diff] [blame^] | 1 | ; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s |
| 2 | |
| 3 | define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { |
| 4 | entry: |
| 5 | ; CHECK: extr.w |
| 6 | |
| 7 | %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15) |
| 8 | ret i32 %1 |
| 9 | } |
| 10 | |
| 11 | declare i32 @llvm.mips.extr.w(i64, i32) nounwind |
| 12 | |
| 13 | define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { |
| 14 | entry: |
| 15 | ; CHECK: extrv.w |
| 16 | |
| 17 | %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1) |
| 18 | ret i32 %1 |
| 19 | } |
| 20 | |
| 21 | define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind { |
| 22 | entry: |
| 23 | ; CHECK: extr_r.w |
| 24 | |
| 25 | %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15) |
| 26 | ret i32 %1 |
| 27 | } |
| 28 | |
| 29 | declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind |
| 30 | |
| 31 | define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { |
| 32 | entry: |
| 33 | ; CHECK: extrv_s.h |
| 34 | |
| 35 | %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1) |
| 36 | ret i32 %1 |
| 37 | } |
| 38 | |
| 39 | declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind |
| 40 | |
| 41 | define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind { |
| 42 | entry: |
| 43 | ; CHECK: extr_rs.w |
| 44 | |
| 45 | %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15) |
| 46 | ret i32 %1 |
| 47 | } |
| 48 | |
| 49 | declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind |
| 50 | |
| 51 | define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { |
| 52 | entry: |
| 53 | ; CHECK: extrv_rs.w |
| 54 | |
| 55 | %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1) |
| 56 | ret i32 %1 |
| 57 | } |
| 58 | |
| 59 | define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind { |
| 60 | entry: |
| 61 | ; CHECK: extr_s.h |
| 62 | |
| 63 | %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15) |
| 64 | ret i32 %1 |
| 65 | } |
| 66 | |
| 67 | define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { |
| 68 | entry: |
| 69 | ; CHECK: extrv_r.w |
| 70 | |
| 71 | %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1) |
| 72 | ret i32 %1 |
| 73 | } |
| 74 | |
| 75 | define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind { |
| 76 | entry: |
| 77 | ; CHECK: extp |
| 78 | |
| 79 | %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15) |
| 80 | ret i32 %1 |
| 81 | } |
| 82 | |
| 83 | declare i32 @llvm.mips.extp(i64, i32) nounwind |
| 84 | |
| 85 | define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { |
| 86 | entry: |
| 87 | ; CHECK: extpv |
| 88 | |
| 89 | %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1) |
| 90 | ret i32 %1 |
| 91 | } |
| 92 | |
| 93 | define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind { |
| 94 | entry: |
| 95 | ; CHECK: extpdp |
| 96 | |
| 97 | %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15) |
| 98 | ret i32 %1 |
| 99 | } |
| 100 | |
| 101 | declare i32 @llvm.mips.extpdp(i64, i32) nounwind |
| 102 | |
| 103 | define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind { |
| 104 | entry: |
| 105 | ; CHECK: extpdpv |
| 106 | |
| 107 | %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1) |
| 108 | ret i32 %1 |
| 109 | } |
| 110 | |