blob: a5f43cd57b615c0650cc07e75565ac99f83f28ec [file] [log] [blame]
Akira Hatanakafd89e6f2012-09-27 02:05:42 +00001; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
2
3define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
4entry:
5; CHECK: extr.w
6
7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
8 ret i32 %1
9}
10
11declare i32 @llvm.mips.extr.w(i64, i32) nounwind
12
13define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
14entry:
15; CHECK: extrv.w
16
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
18 ret i32 %1
19}
20
21define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {
22entry:
23; CHECK: extr_r.w
24
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
26 ret i32 %1
27}
28
29declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
30
31define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
32entry:
33; CHECK: extrv_s.h
34
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
36 ret i32 %1
37}
38
39declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
40
41define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {
42entry:
43; CHECK: extr_rs.w
44
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
46 ret i32 %1
47}
48
49declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
50
51define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
52entry:
53; CHECK: extrv_rs.w
54
55 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)
56 ret i32 %1
57}
58
59define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {
60entry:
61; CHECK: extr_s.h
62
63 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15)
64 ret i32 %1
65}
66
67define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
68entry:
69; CHECK: extrv_r.w
70
71 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1)
72 ret i32 %1
73}
74
75define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
76entry:
77; CHECK: extp
78
79 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)
80 ret i32 %1
81}
82
83declare i32 @llvm.mips.extp(i64, i32) nounwind
84
85define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
86entry:
87; CHECK: extpv
88
89 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1)
90 ret i32 %1
91}
92
93define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
94entry:
95; CHECK: extpdp
96
97 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)
98 ret i32 %1
99}
100
101declare i32 @llvm.mips.extpdp(i64, i32) nounwind
102
103define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
104entry:
105; CHECK: extpdpv
106
107 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1)
108 ret i32 %1
109}
110