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Andrew Trick14e8d712010-10-22 23:09:15 +00001//===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// LiveIntervalUnion is a union of live segments across multiple live virtual
11// registers. This may be used during coalescing to represent a congruence
12// class, or during register allocation to model liveness of a physical
13// register.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_LIVEINTERVALUNION
18#define LLVM_CODEGEN_LIVEINTERVALUNION
19
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000020#include "llvm/ADT/IntervalMap.h"
Andrew Trick14e8d712010-10-22 23:09:15 +000021#include "llvm/CodeGen/LiveInterval.h"
Andrew Trick14e8d712010-10-22 23:09:15 +000022
Jakob Stoklund Olesenbfce6782010-12-14 19:38:49 +000023#include <algorithm>
24
Andrew Trick14e8d712010-10-22 23:09:15 +000025namespace llvm {
26
Jakob Stoklund Olesenff2e9b42010-12-17 04:09:47 +000027class MachineLoopRange;
Jakob Stoklund Olesen4a84cce2010-12-14 18:53:47 +000028class TargetRegisterInfo;
29
Andrew Trick071d1c02010-11-09 21:04:34 +000030#ifndef NDEBUG
31// forward declaration
32template <unsigned Element> class SparseBitVector;
Andrew Trick18c57a82010-11-30 23:18:47 +000033typedef SparseBitVector<128> LiveVirtRegBitSet;
Andrew Trick071d1c02010-11-09 21:04:34 +000034#endif
35
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000036/// Compare a live virtual register segment to a LiveIntervalUnion segment.
37inline bool
38overlap(const LiveRange &VRSeg,
39 const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
40 return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
41}
42
Andrew Trick14e8d712010-10-22 23:09:15 +000043/// Union of live intervals that are strong candidates for coalescing into a
44/// single register (either physical or virtual depending on the context). We
45/// expect the constituent live intervals to be disjoint, although we may
46/// eventually make exceptions to handle value-based interference.
47class LiveIntervalUnion {
48 // A set of live virtual register segments that supports fast insertion,
Andrew Trick18c57a82010-11-30 23:18:47 +000049 // intersection, and removal.
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000050 // Mapping SlotIndex intervals to virtual register numbers.
51 typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
Andrew Trick14e8d712010-10-22 23:09:15 +000052
Andrew Trick14e8d712010-10-22 23:09:15 +000053public:
54 // SegmentIter can advance to the next segment ordered by starting position
55 // which may belong to a different live virtual register. We also must be able
56 // to reach the current segment's containing virtual register.
57 typedef LiveSegments::iterator SegmentIter;
58
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000059 // LiveIntervalUnions share an external allocator.
60 typedef LiveSegments::Allocator Allocator;
61
Andrew Trick14e8d712010-10-22 23:09:15 +000062 class Query;
63
64private:
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000065 const unsigned RepReg; // representative register number
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +000066 unsigned Tag; // unique tag for current contents.
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000067 LiveSegments Segments; // union of virtual reg segments
Andrew Trick14e8d712010-10-22 23:09:15 +000068
69public:
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +000070 LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Tag(0), Segments(a)
71 {}
Andrew Trick14e8d712010-10-22 23:09:15 +000072
Andrew Tricke16eecc2010-10-26 18:34:01 +000073 // Iterate over all segments in the union of live virtual registers ordered
74 // by their starting position.
Andrew Trick18c57a82010-11-30 23:18:47 +000075 SegmentIter begin() { return Segments.begin(); }
76 SegmentIter end() { return Segments.end(); }
Jakob Stoklund Olesena35cce12010-12-09 01:06:52 +000077 SegmentIter find(SlotIndex x) { return Segments.find(x); }
Jakob Stoklund Olesenbfce6782010-12-14 19:38:49 +000078 bool empty() const { return Segments.empty(); }
79 SlotIndex startIndex() const { return Segments.start(); }
Andrew Trick14e8d712010-10-22 23:09:15 +000080
Jakob Stoklund Olesenff2e9b42010-12-17 04:09:47 +000081 // Provide public access to the underlying map to allow overlap iteration.
82 typedef LiveSegments Map;
83 const Map &getMap() { return Segments; }
84
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +000085 /// getTag - Return an opaque tag representing the current state of the union.
86 unsigned getTag() const { return Tag; }
87
88 /// changedSince - Return true if the union change since getTag returned tag.
89 bool changedSince(unsigned tag) const { return tag != Tag; }
90
Andrew Tricke16eecc2010-10-26 18:34:01 +000091 // Add a live virtual register to this union and merge its segments.
Andrew Trick18c57a82010-11-30 23:18:47 +000092 void unify(LiveInterval &VirtReg);
Andrew Trick14e8d712010-10-22 23:09:15 +000093
Andrew Tricke141a492010-11-08 18:02:08 +000094 // Remove a live virtual register's segments from this union.
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000095 void extract(LiveInterval &VirtReg);
Andrew Trick14e8d712010-10-22 23:09:15 +000096
Jakob Stoklund Olesen560ab9e2011-04-11 23:57:14 +000097 // Remove all inserted virtual registers.
98 void clear() { Segments.clear(); ++Tag; }
99
Jakob Stoklund Olesen4a84cce2010-12-14 18:53:47 +0000100 // Print union, using TRI to translate register names
101 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
Andrew Trick18c57a82010-11-30 23:18:47 +0000102
Andrew Trick071d1c02010-11-09 21:04:34 +0000103#ifndef NDEBUG
104 // Verify the live intervals in this union and add them to the visited set.
Andrew Trick18c57a82010-11-30 23:18:47 +0000105 void verify(LiveVirtRegBitSet& VisitedVRegs);
Andrew Trick071d1c02010-11-09 21:04:34 +0000106#endif
107
Andrew Trick14e8d712010-10-22 23:09:15 +0000108 /// Query interferences between a single live virtual register and a live
109 /// interval union.
110 class Query {
Andrew Trick18c57a82010-11-30 23:18:47 +0000111 LiveIntervalUnion *LiveUnion;
112 LiveInterval *VirtReg;
Jakob Stoklund Olesenfe026e1822011-08-11 22:46:04 +0000113 LiveInterval::iterator VirtRegI; // current position in VirtReg
114 SegmentIter LiveUnionI; // current position in LiveUnion
Andrew Trick18c57a82010-11-30 23:18:47 +0000115 SmallVector<LiveInterval*,4> InterferingVRegs;
Jakob Stoklund Olesena35cce12010-12-09 01:06:52 +0000116 bool CheckedFirstInterference;
Andrew Trick18c57a82010-11-30 23:18:47 +0000117 bool SeenAllInterferences;
118 bool SeenUnspillableVReg;
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000119 unsigned Tag, UserTag;
Andrew Trick14e8d712010-10-22 23:09:15 +0000120
121 public:
Jakob Stoklund Olesen314a3ef2011-03-31 15:14:11 +0000122 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
Andrew Trick14e8d712010-10-22 23:09:15 +0000123
Andrew Trick18c57a82010-11-30 23:18:47 +0000124 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
Jakob Stoklund Olesena0382c62010-12-09 21:20:44 +0000125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
126 SeenAllInterferences(false), SeenUnspillableVReg(false)
Andrew Trick18c57a82010-11-30 23:18:47 +0000127 {}
Andrew Tricke141a492010-11-08 18:02:08 +0000128
129 void clear() {
Andrew Trick18c57a82010-11-30 23:18:47 +0000130 LiveUnion = NULL;
131 VirtReg = NULL;
Andrew Trick18c57a82010-11-30 23:18:47 +0000132 InterferingVRegs.clear();
Jakob Stoklund Olesena35cce12010-12-09 01:06:52 +0000133 CheckedFirstInterference = false;
Andrew Trick18c57a82010-11-30 23:18:47 +0000134 SeenAllInterferences = false;
135 SeenUnspillableVReg = false;
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +0000136 Tag = 0;
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000137 UserTag = 0;
Andrew Tricke141a492010-11-08 18:02:08 +0000138 }
Andrew Trick18c57a82010-11-30 23:18:47 +0000139
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000140 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) {
Jakob Stoklund Olesena0382c62010-12-09 21:20:44 +0000141 assert(VReg && LIU && "Invalid arguments");
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000142 if (UserTag == UTag && VirtReg == VReg &&
143 LiveUnion == LIU && !LIU->changedSince(Tag)) {
Andrew Tricke141a492010-11-08 18:02:08 +0000144 // Retain cached results, e.g. firstInterference.
145 return;
146 }
Andrew Trick18c57a82010-11-30 23:18:47 +0000147 clear();
148 LiveUnion = LIU;
149 VirtReg = VReg;
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +0000150 Tag = LIU->getTag();
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000151 UserTag = UTag;
Andrew Tricke141a492010-11-08 18:02:08 +0000152 }
153
Andrew Trick18c57a82010-11-30 23:18:47 +0000154 LiveInterval &virtReg() const {
155 assert(VirtReg && "uninitialized");
156 return *VirtReg;
157 }
Andrew Trick14e8d712010-10-22 23:09:15 +0000158
Andrew Trick18c57a82010-11-30 23:18:47 +0000159 // Does this live virtual register interfere with the union?
Jakob Stoklund Olesen9942ba92011-08-11 21:18:34 +0000160 bool checkInterference() { return collectInterferingVRegs(1); }
Andrew Trick14e8d712010-10-22 23:09:15 +0000161
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000162 // Count the virtual registers in this union that interfere with this
163 // query's live virtual register, up to maxInterferingRegs.
Jakob Stoklund Olesen51458ed2011-07-08 20:46:18 +0000164 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000165
166 // Was this virtual register visited during collectInterferingVRegs?
Andrew Trick18c57a82010-11-30 23:18:47 +0000167 bool isSeenInterference(LiveInterval *VReg) const;
168
169 // Did collectInterferingVRegs collect all interferences?
170 bool seenAllInterferences() const { return SeenAllInterferences; }
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000171
172 // Did collectInterferingVRegs encounter an unspillable vreg?
Andrew Trick18c57a82010-11-30 23:18:47 +0000173 bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000174
175 // Vector generated by collectInterferingVRegs.
176 const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
Andrew Trick18c57a82010-11-30 23:18:47 +0000177 return InterferingVRegs;
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000178 }
Andrew Trick18c57a82010-11-30 23:18:47 +0000179
Jakob Stoklund Olesenff2e9b42010-12-17 04:09:47 +0000180 /// checkLoopInterference - Return true if there is interference overlapping
181 /// Loop.
182 bool checkLoopInterference(MachineLoopRange*);
183
Andrew Trick14e8d712010-10-22 23:09:15 +0000184 private:
Andrew Trick8a83d542010-11-11 17:46:29 +0000185 Query(const Query&); // DO NOT IMPLEMENT
186 void operator=(const Query&); // DO NOT IMPLEMENT
Andrew Trick14e8d712010-10-22 23:09:15 +0000187 };
188};
189
190} // end namespace llvm
191
192#endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)