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Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001//===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating from LLVM IR into SelectionDAG IR.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
15#include "SelectionDAGBuild.h"
16#include "llvm/ADT/BitVector.h"
Dan Gohman5b229802008-09-04 20:49:27 +000017#include "llvm/ADT/SmallSet.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000018#include "llvm/Analysis/AliasAnalysis.h"
19#include "llvm/Constants.h"
20#include "llvm/CallingConv.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/InlineAsm.h"
25#include "llvm/Instructions.h"
26#include "llvm/Intrinsics.h"
27#include "llvm/IntrinsicInst.h"
Bill Wendlingb2a42982008-11-06 02:29:10 +000028#include "llvm/Module.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000029#include "llvm/CodeGen/FastISel.h"
30#include "llvm/CodeGen/GCStrategy.h"
31#include "llvm/CodeGen/GCMetadata.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineJumpTableInfo.h"
36#include "llvm/CodeGen/MachineModuleInfo.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
Bill Wendlingb2a42982008-11-06 02:29:10 +000038#include "llvm/CodeGen/PseudoSourceValue.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000039#include "llvm/CodeGen/SelectionDAG.h"
Devang Patel83489bb2009-01-13 00:35:13 +000040#include "llvm/CodeGen/DwarfWriter.h"
41#include "llvm/Analysis/DebugInfo.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000042#include "llvm/Target/TargetRegisterInfo.h"
43#include "llvm/Target/TargetData.h"
44#include "llvm/Target/TargetFrameInfo.h"
45#include "llvm/Target/TargetInstrInfo.h"
46#include "llvm/Target/TargetLowering.h"
47#include "llvm/Target/TargetMachine.h"
48#include "llvm/Target/TargetOptions.h"
49#include "llvm/Support/Compiler.h"
Mikhail Glushenkov2388a582009-01-16 07:02:28 +000050#include "llvm/Support/CommandLine.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000051#include "llvm/Support/Debug.h"
52#include "llvm/Support/MathExtras.h"
Anton Korobeynikov56d245b2008-12-23 22:26:18 +000053#include "llvm/Support/raw_ostream.h"
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000054#include <algorithm>
55using namespace llvm;
56
Dale Johannesen601d3c02008-09-05 01:48:15 +000057/// LimitFloatPrecision - Generate low-precision inline sequences for
58/// some float libcalls (6, 8 or 12 bits).
59static unsigned LimitFloatPrecision;
60
61static cl::opt<unsigned, true>
62LimitFPPrecision("limit-float-precision",
63 cl::desc("Generate low-precision inline sequences "
64 "for some float libcalls"),
65 cl::location(LimitFloatPrecision),
66 cl::init(0));
67
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000068/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
Dan Gohman2c91d102009-01-06 22:53:52 +000069/// of insertvalue or extractvalue indices that identify a member, return
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000070/// the linearized index of the start of the member.
71///
72static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
73 const unsigned *Indices,
74 const unsigned *IndicesEnd,
75 unsigned CurIndex = 0) {
76 // Base case: We're done.
77 if (Indices && Indices == IndicesEnd)
78 return CurIndex;
79
80 // Given a struct type, recursively traverse the elements.
81 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
82 for (StructType::element_iterator EB = STy->element_begin(),
83 EI = EB,
84 EE = STy->element_end();
85 EI != EE; ++EI) {
86 if (Indices && *Indices == unsigned(EI - EB))
87 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
88 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
89 }
Dan Gohman2c91d102009-01-06 22:53:52 +000090 return CurIndex;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +000091 }
92 // Given an array type, recursively traverse the elements.
93 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
94 const Type *EltTy = ATy->getElementType();
95 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
96 if (Indices && *Indices == i)
97 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
98 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
99 }
Dan Gohman2c91d102009-01-06 22:53:52 +0000100 return CurIndex;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000101 }
102 // We haven't found the type we're looking for, so keep searching.
103 return CurIndex + 1;
104}
105
106/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
107/// MVTs that represent all the individual underlying
108/// non-aggregate types that comprise it.
109///
110/// If Offsets is non-null, it points to a vector to be filled in
111/// with the in-memory offsets of each of the individual values.
112///
113static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
114 SmallVectorImpl<MVT> &ValueVTs,
115 SmallVectorImpl<uint64_t> *Offsets = 0,
116 uint64_t StartingOffset = 0) {
117 // Given a struct type, recursively traverse the elements.
118 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
119 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
120 for (StructType::element_iterator EB = STy->element_begin(),
121 EI = EB,
122 EE = STy->element_end();
123 EI != EE; ++EI)
124 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
125 StartingOffset + SL->getElementOffset(EI - EB));
126 return;
127 }
128 // Given an array type, recursively traverse the elements.
129 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
130 const Type *EltTy = ATy->getElementType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +0000131 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000132 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
133 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
134 StartingOffset + i * EltSize);
135 return;
136 }
137 // Base case: we can get an MVT for this LLVM IR type.
138 ValueVTs.push_back(TLI.getValueType(Ty));
139 if (Offsets)
140 Offsets->push_back(StartingOffset);
141}
142
Dan Gohman2a7c6712008-09-03 23:18:39 +0000143namespace llvm {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000144 /// RegsForValue - This struct represents the registers (physical or virtual)
145 /// that a particular set of values is assigned, and the type information about
146 /// the value. The most common situation is to represent one value at a time,
147 /// but struct or array values are handled element-wise as multiple values.
148 /// The splitting of aggregates is performed recursively, so that we never
149 /// have aggregate-typed registers. The values at this point do not necessarily
150 /// have legal types, so each value may require one or more registers of some
151 /// legal type.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000152 ///
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000153 struct VISIBILITY_HIDDEN RegsForValue {
154 /// TLI - The TargetLowering object.
155 ///
156 const TargetLowering *TLI;
157
158 /// ValueVTs - The value types of the values, which may not be legal, and
159 /// may need be promoted or synthesized from one or more registers.
160 ///
161 SmallVector<MVT, 4> ValueVTs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000162
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000163 /// RegVTs - The value types of the registers. This is the same size as
164 /// ValueVTs and it records, for each value, what the type of the assigned
165 /// register or registers are. (Individual values are never synthesized
166 /// from more than one type of register.)
167 ///
168 /// With virtual registers, the contents of RegVTs is redundant with TLI's
169 /// getRegisterType member function, however when with physical registers
170 /// it is necessary to have a separate record of the types.
171 ///
172 SmallVector<MVT, 4> RegVTs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000173
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000174 /// Regs - This list holds the registers assigned to the values.
175 /// Each legal or promoted value requires one register, and each
176 /// expanded value requires multiple registers.
177 ///
178 SmallVector<unsigned, 4> Regs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000179
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000180 RegsForValue() : TLI(0) {}
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000181
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000182 RegsForValue(const TargetLowering &tli,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000183 const SmallVector<unsigned, 4> &regs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000184 MVT regvt, MVT valuevt)
185 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
186 RegsForValue(const TargetLowering &tli,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000187 const SmallVector<unsigned, 4> &regs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000188 const SmallVector<MVT, 4> &regvts,
189 const SmallVector<MVT, 4> &valuevts)
190 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 unsigned Reg, const Type *Ty) : TLI(&tli) {
193 ComputeValueVTs(tli, Ty, ValueVTs);
194
195 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
196 MVT ValueVT = ValueVTs[Value];
197 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
198 MVT RegisterVT = TLI->getRegisterType(ValueVT);
199 for (unsigned i = 0; i != NumRegs; ++i)
200 Regs.push_back(Reg + i);
201 RegVTs.push_back(RegisterVT);
202 Reg += NumRegs;
203 }
204 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000205
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000206 /// append - Add the specified values to this one.
207 void append(const RegsForValue &RHS) {
208 TLI = RHS.TLI;
209 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
210 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
211 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
212 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000213
214
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000215 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000216 /// this value and returns the result as a ValueVTs value. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000217 /// Chain/Flag as the input and updates them for the output Chain/Flag.
218 /// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000219 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000220 SDValue &Chain, SDValue *Flag) const;
221
222 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000223 /// specified value into the registers specified by this object. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000224 /// Chain/Flag as the input and updates them for the output Chain/Flag.
225 /// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000226 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000227 SDValue &Chain, SDValue *Flag) const;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000228
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000229 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000230 /// operand list. This adds the code marker and includes the number of
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000231 /// values added into it.
232 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
233 std::vector<SDValue> &Ops) const;
234 };
235}
236
237/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000238/// PHI nodes or outside of the basic block that defines it, or used by a
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000239/// switch or atomic instruction, which may expand to multiple basic blocks.
240static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
241 if (isa<PHINode>(I)) return true;
242 BasicBlock *BB = I->getParent();
243 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
244 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
245 // FIXME: Remove switchinst special case.
246 isa<SwitchInst>(*UI))
247 return true;
248 return false;
249}
250
251/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
252/// entry block, return true. This includes arguments used by switches, since
253/// the switch may expand into multiple basic blocks.
254static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
255 // With FastISel active, we may be splitting blocks, so force creation
256 // of virtual registers for all non-dead arguments.
Dan Gohman33134c42008-09-25 17:05:24 +0000257 // Don't force virtual registers for byval arguments though, because
258 // fast-isel can't handle those in all cases.
259 if (EnableFastISel && !A->hasByValAttr())
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000260 return A->use_empty();
261
262 BasicBlock *Entry = A->getParent()->begin();
263 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
264 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
265 return false; // Use not in entry block.
266 return true;
267}
268
269FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
270 : TLI(tli) {
271}
272
273void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
Bill Wendling6a8a0d72009-02-03 02:20:52 +0000274 SelectionDAG &DAG,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000275 bool EnableFastISel) {
276 Fn = &fn;
277 MF = &mf;
278 RegInfo = &MF->getRegInfo();
279
280 // Create a vreg for each argument register that is not dead and is used
281 // outside of the entry block for the function.
282 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
283 AI != E; ++AI)
284 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
285 InitializeRegForValue(AI);
286
287 // Initialize the mapping of values to registers. This is only set up for
288 // instruction values that are used outside of the block that defines
289 // them.
290 Function::iterator BB = Fn->begin(), EB = Fn->end();
291 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
292 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
293 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
294 const Type *Ty = AI->getAllocatedType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +0000295 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000296 unsigned Align =
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000297 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
298 AI->getAlignment());
299
300 TySize *= CUI->getZExtValue(); // Get total allocated size.
301 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
302 StaticAllocaMap[AI] =
303 MF->getFrameInfo()->CreateStackObject(TySize, Align);
304 }
305
306 for (; BB != EB; ++BB)
307 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
308 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
309 if (!isa<AllocaInst>(I) ||
310 !StaticAllocaMap.count(cast<AllocaInst>(I)))
311 InitializeRegForValue(I);
312
313 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
314 // also creates the initial PHI MachineInstrs, though none of the input
315 // operands are populated.
316 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
317 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
318 MBBMap[BB] = MBB;
319 MF->push_back(MBB);
320
321 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
322 // appropriate.
323 PHINode *PN;
Bill Wendling6a8a0d72009-02-03 02:20:52 +0000324 DebugLoc DL;
325 for (BasicBlock::iterator
326 I = BB->begin(), E = BB->end(); I != E; ++I) {
327 if (CallInst *CI = dyn_cast<CallInst>(I)) {
328 if (Function *F = CI->getCalledFunction()) {
329 switch (F->getIntrinsicID()) {
330 default: break;
331 case Intrinsic::dbg_stoppoint: {
332 DwarfWriter *DW = DAG.getDwarfWriter();
333 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
334
335 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
336 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
337 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
338 CU.getFilename());
339 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
340 SPI->getLine(),
341 SPI->getColumn());
342 DL = DebugLoc::get(idx);
343 }
344
345 break;
346 }
347 case Intrinsic::dbg_func_start: {
348 DwarfWriter *DW = DAG.getDwarfWriter();
349 if (DW) {
350 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
351 Value *SP = FSI->getSubprogram();
352
353 if (DW->ValidDebugInfo(SP)) {
354 DISubprogram Subprogram(cast<GlobalVariable>(SP));
355 DICompileUnit CU(Subprogram.getCompileUnit());
356 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
357 CU.getFilename());
358 unsigned Line = Subprogram.getLineNumber();
359 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
360 }
361 }
362
363 break;
364 }
365 }
366 }
367 }
368
369 PN = dyn_cast<PHINode>(I);
370 if (!PN || PN->use_empty()) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000371
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000372 unsigned PHIReg = ValueMap[PN];
373 assert(PHIReg && "PHI node does not have an assigned virtual register!");
374
375 SmallVector<MVT, 4> ValueVTs;
376 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
377 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
378 MVT VT = ValueVTs[vti];
379 unsigned NumRegisters = TLI.getNumRegisters(VT);
Dan Gohman6448d912008-09-04 15:39:15 +0000380 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000381 for (unsigned i = 0; i != NumRegisters; ++i)
Bill Wendling6a8a0d72009-02-03 02:20:52 +0000382 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000383 PHIReg += NumRegisters;
384 }
385 }
386 }
387}
388
389unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
390 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
391}
392
393/// CreateRegForValue - Allocate the appropriate number of virtual registers of
394/// the correctly promoted or expanded types. Assign these registers
395/// consecutive vreg numbers and return the first assigned number.
396///
397/// In the case that the given value has struct or array type, this function
398/// will assign registers for each member or element.
399///
400unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
401 SmallVector<MVT, 4> ValueVTs;
402 ComputeValueVTs(TLI, V->getType(), ValueVTs);
403
404 unsigned FirstReg = 0;
405 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
406 MVT ValueVT = ValueVTs[Value];
407 MVT RegisterVT = TLI.getRegisterType(ValueVT);
408
409 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
410 for (unsigned i = 0; i != NumRegs; ++i) {
411 unsigned R = MakeReg(RegisterVT);
412 if (!FirstReg) FirstReg = R;
413 }
414 }
415 return FirstReg;
416}
417
418/// getCopyFromParts - Create a value that contains the specified legal parts
419/// combined into the value they represent. If the parts combine to a type
420/// larger then ValueVT then AssertOp can be used to specify whether the extra
421/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
422/// (ISD::AssertSext).
Dale Johannesen66978ee2009-01-31 02:22:37 +0000423static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
424 const SDValue *Parts,
Duncan Sands0b3aa262009-01-28 14:42:54 +0000425 unsigned NumParts, MVT PartVT, MVT ValueVT,
426 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000427 assert(NumParts > 0 && "No parts to assemble!");
Dan Gohmane9530ec2009-01-15 16:58:17 +0000428 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000429 SDValue Val = Parts[0];
430
431 if (NumParts > 1) {
432 // Assemble the value from multiple parts.
433 if (!ValueVT.isVector()) {
434 unsigned PartBits = PartVT.getSizeInBits();
435 unsigned ValueBits = ValueVT.getSizeInBits();
436
437 // Assemble the power of 2 part.
438 unsigned RoundParts = NumParts & (NumParts - 1) ?
439 1 << Log2_32(NumParts) : NumParts;
440 unsigned RoundBits = PartBits * RoundParts;
441 MVT RoundVT = RoundBits == ValueBits ?
442 ValueVT : MVT::getIntegerVT(RoundBits);
443 SDValue Lo, Hi;
444
Duncan Sandsd22ec5f2008-10-29 14:22:20 +0000445 MVT HalfVT = ValueVT.isInteger() ?
446 MVT::getIntegerVT(RoundBits/2) :
447 MVT::getFloatingPointVT(RoundBits/2);
448
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000449 if (RoundParts > 2) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000450 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
451 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000452 PartVT, HalfVT);
453 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000454 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
455 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000456 }
457 if (TLI.isBigEndian())
458 std::swap(Lo, Hi);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000459 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000460
461 if (RoundParts < NumParts) {
462 // Assemble the trailing non-power-of-2 part.
463 unsigned OddParts = NumParts - RoundParts;
464 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000465 Hi = getCopyFromParts(DAG, dl,
466 Parts+RoundParts, OddParts, PartVT, OddVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000467
468 // Combine the round and odd parts.
469 Lo = Val;
470 if (TLI.isBigEndian())
471 std::swap(Lo, Hi);
472 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000473 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
474 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000475 DAG.getConstant(Lo.getValueType().getSizeInBits(),
Duncan Sands92abc622009-01-31 15:50:11 +0000476 TLI.getPointerTy()));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000477 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
478 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000479 }
480 } else {
481 // Handle a multi-element vector.
482 MVT IntermediateVT, RegisterVT;
483 unsigned NumIntermediates;
484 unsigned NumRegs =
485 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
486 RegisterVT);
487 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
488 NumParts = NumRegs; // Silence a compiler warning.
489 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
490 assert(RegisterVT == Parts[0].getValueType() &&
491 "Part type doesn't match part!");
492
493 // Assemble the parts into intermediate operands.
494 SmallVector<SDValue, 8> Ops(NumIntermediates);
495 if (NumIntermediates == NumParts) {
496 // If the register was not expanded, truncate or copy the value,
497 // as appropriate.
498 for (unsigned i = 0; i != NumParts; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000499 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000500 PartVT, IntermediateVT);
501 } else if (NumParts > 0) {
502 // If the intermediate type was expanded, build the intermediate operands
503 // from the parts.
504 assert(NumParts % NumIntermediates == 0 &&
505 "Must expand into a divisible number of parts!");
506 unsigned Factor = NumParts / NumIntermediates;
507 for (unsigned i = 0; i != NumIntermediates; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000508 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000509 PartVT, IntermediateVT);
510 }
511
512 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
513 // operands.
514 Val = DAG.getNode(IntermediateVT.isVector() ?
Dale Johannesen66978ee2009-01-31 02:22:37 +0000515 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000516 ValueVT, &Ops[0], NumIntermediates);
517 }
518 }
519
520 // There is now one part, held in Val. Correct it to match ValueVT.
521 PartVT = Val.getValueType();
522
523 if (PartVT == ValueVT)
524 return Val;
525
526 if (PartVT.isVector()) {
527 assert(ValueVT.isVector() && "Unknown vector conversion!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000528 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000529 }
530
531 if (ValueVT.isVector()) {
532 assert(ValueVT.getVectorElementType() == PartVT &&
533 ValueVT.getVectorNumElements() == 1 &&
534 "Only trivial scalar-to-vector conversions should get here!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000535 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000536 }
537
538 if (PartVT.isInteger() &&
539 ValueVT.isInteger()) {
540 if (ValueVT.bitsLT(PartVT)) {
541 // For a truncate, see if we have any information to
542 // indicate whether the truncated bits will always be
543 // zero or sign-extension.
544 if (AssertOp != ISD::DELETED_NODE)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000545 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000546 DAG.getValueType(ValueVT));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000547 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000548 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000549 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000550 }
551 }
552
553 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
554 if (ValueVT.bitsLT(Val.getValueType()))
555 // FP_ROUND's are always exact here.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000556 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000557 DAG.getIntPtrConstant(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000558 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000559 }
560
561 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
Dale Johannesen66978ee2009-01-31 02:22:37 +0000562 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000563
564 assert(0 && "Unknown mismatch!");
565 return SDValue();
566}
567
568/// getCopyToParts - Create a series of nodes that contain the specified value
569/// split into legal parts. If the parts contain more bits than Val, then, for
570/// integers, ExtendKind can be used to specify how to generate the extra bits.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000571static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
Chris Lattner01426e12008-10-21 00:45:36 +0000572 SDValue *Parts, unsigned NumParts, MVT PartVT,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000573 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
Dan Gohmane9530ec2009-01-15 16:58:17 +0000574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000575 MVT PtrVT = TLI.getPointerTy();
576 MVT ValueVT = Val.getValueType();
577 unsigned PartBits = PartVT.getSizeInBits();
578 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
579
580 if (!NumParts)
581 return;
582
583 if (!ValueVT.isVector()) {
584 if (PartVT == ValueVT) {
585 assert(NumParts == 1 && "No-op copy with multiple parts!");
586 Parts[0] = Val;
587 return;
588 }
589
590 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
591 // If the parts cover more bits than the value has, promote the value.
592 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
593 assert(NumParts == 1 && "Do not know what to promote to!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000594 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000595 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
596 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000597 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000598 } else {
599 assert(0 && "Unknown mismatch!");
600 }
601 } else if (PartBits == ValueVT.getSizeInBits()) {
602 // Different types of the same size.
603 assert(NumParts == 1 && PartVT != ValueVT);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000604 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000605 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
606 // If the parts cover less bits than value has, truncate the value.
607 if (PartVT.isInteger() && ValueVT.isInteger()) {
608 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000609 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000610 } else {
611 assert(0 && "Unknown mismatch!");
612 }
613 }
614
615 // The value may have changed - recompute ValueVT.
616 ValueVT = Val.getValueType();
617 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
618 "Failed to tile the value with PartVT!");
619
620 if (NumParts == 1) {
621 assert(PartVT == ValueVT && "Type conversion failed!");
622 Parts[0] = Val;
623 return;
624 }
625
626 // Expand the value into multiple parts.
627 if (NumParts & (NumParts - 1)) {
628 // The number of parts is not a power of 2. Split off and copy the tail.
629 assert(PartVT.isInteger() && ValueVT.isInteger() &&
630 "Do not know what to expand to!");
631 unsigned RoundParts = 1 << Log2_32(NumParts);
632 unsigned RoundBits = RoundParts * PartBits;
633 unsigned OddParts = NumParts - RoundParts;
Dale Johannesen66978ee2009-01-31 02:22:37 +0000634 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
Duncan Sands0b3aa262009-01-28 14:42:54 +0000635 DAG.getConstant(RoundBits,
Duncan Sands92abc622009-01-31 15:50:11 +0000636 TLI.getPointerTy()));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000637 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000638 if (TLI.isBigEndian())
639 // The odd parts were reversed by getCopyToParts - unreverse them.
640 std::reverse(Parts + RoundParts, Parts + NumParts);
641 NumParts = RoundParts;
642 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000643 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000644 }
645
646 // The number of parts is a power of 2. Repeatedly bisect the value using
647 // EXTRACT_ELEMENT.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000648 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000649 MVT::getIntegerVT(ValueVT.getSizeInBits()),
650 Val);
651 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
652 for (unsigned i = 0; i < NumParts; i += StepSize) {
653 unsigned ThisBits = StepSize * PartBits / 2;
654 MVT ThisVT = MVT::getIntegerVT (ThisBits);
655 SDValue &Part0 = Parts[i];
656 SDValue &Part1 = Parts[i+StepSize/2];
657
Dale Johannesen66978ee2009-01-31 02:22:37 +0000658 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000659 ThisVT, Part0,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000660 DAG.getConstant(1, PtrVT));
Dale Johannesen66978ee2009-01-31 02:22:37 +0000661 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000662 ThisVT, Part0,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000663 DAG.getConstant(0, PtrVT));
664
665 if (ThisBits == PartBits && ThisVT != PartVT) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000666 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000667 PartVT, Part0);
Dale Johannesen66978ee2009-01-31 02:22:37 +0000668 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000669 PartVT, Part1);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000670 }
671 }
672 }
673
674 if (TLI.isBigEndian())
675 std::reverse(Parts, Parts + NumParts);
676
677 return;
678 }
679
680 // Vector ValueVT.
681 if (NumParts == 1) {
682 if (PartVT != ValueVT) {
683 if (PartVT.isVector()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000684 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000685 } else {
686 assert(ValueVT.getVectorElementType() == PartVT &&
687 ValueVT.getVectorNumElements() == 1 &&
688 "Only trivial vector-to-scalar conversions should get here!");
Dale Johannesen66978ee2009-01-31 02:22:37 +0000689 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000690 PartVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000691 DAG.getConstant(0, PtrVT));
692 }
693 }
694
695 Parts[0] = Val;
696 return;
697 }
698
699 // Handle a multi-element vector.
700 MVT IntermediateVT, RegisterVT;
701 unsigned NumIntermediates;
Dan Gohmane9530ec2009-01-15 16:58:17 +0000702 unsigned NumRegs = TLI
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000703 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
704 RegisterVT);
705 unsigned NumElements = ValueVT.getVectorNumElements();
706
707 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
708 NumParts = NumRegs; // Silence a compiler warning.
709 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
710
711 // Split the vector into intermediate operands.
712 SmallVector<SDValue, 8> Ops(NumIntermediates);
713 for (unsigned i = 0; i != NumIntermediates; ++i)
714 if (IntermediateVT.isVector())
Dale Johannesen66978ee2009-01-31 02:22:37 +0000715 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000716 IntermediateVT, Val,
717 DAG.getConstant(i * (NumElements / NumIntermediates),
718 PtrVT));
719 else
Dale Johannesen66978ee2009-01-31 02:22:37 +0000720 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000721 IntermediateVT, Val,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000722 DAG.getConstant(i, PtrVT));
723
724 // Split the intermediate operands into legal parts.
725 if (NumParts == NumIntermediates) {
726 // If the register was not expanded, promote or copy the value,
727 // as appropriate.
728 for (unsigned i = 0; i != NumParts; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000729 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000730 } else if (NumParts > 0) {
731 // If the intermediate type was expanded, split each the value into
732 // legal parts.
733 assert(NumParts % NumIntermediates == 0 &&
734 "Must expand into a divisible number of parts!");
735 unsigned Factor = NumParts / NumIntermediates;
736 for (unsigned i = 0; i != NumIntermediates; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +0000737 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000738 }
739}
740
741
742void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
743 AA = &aa;
744 GFI = gfi;
745 TD = DAG.getTarget().getTargetData();
746}
747
748/// clear - Clear out the curret SelectionDAG and the associated
749/// state and prepare this SelectionDAGLowering object to be used
750/// for a new block. This doesn't clear out information about
751/// additional blocks that are needed to complete switch lowering
752/// or PHI node updating; that information is cleared out as it is
753/// consumed.
754void SelectionDAGLowering::clear() {
755 NodeMap.clear();
756 PendingLoads.clear();
757 PendingExports.clear();
758 DAG.clear();
759}
760
761/// getRoot - Return the current virtual root of the Selection DAG,
762/// flushing any PendingLoad items. This must be done before emitting
763/// a store or any other node that may need to be ordered after any
764/// prior load instructions.
765///
766SDValue SelectionDAGLowering::getRoot() {
767 if (PendingLoads.empty())
768 return DAG.getRoot();
769
770 if (PendingLoads.size() == 1) {
771 SDValue Root = PendingLoads[0];
772 DAG.setRoot(Root);
773 PendingLoads.clear();
774 return Root;
775 }
776
777 // Otherwise, we have to make a token factor node.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000778 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000779 &PendingLoads[0], PendingLoads.size());
780 PendingLoads.clear();
781 DAG.setRoot(Root);
782 return Root;
783}
784
785/// getControlRoot - Similar to getRoot, but instead of flushing all the
786/// PendingLoad items, flush all the PendingExports items. It is necessary
787/// to do this before emitting a terminator instruction.
788///
789SDValue SelectionDAGLowering::getControlRoot() {
790 SDValue Root = DAG.getRoot();
791
792 if (PendingExports.empty())
793 return Root;
794
795 // Turn all of the CopyToReg chains into one factored node.
796 if (Root.getOpcode() != ISD::EntryToken) {
797 unsigned i = 0, e = PendingExports.size();
798 for (; i != e; ++i) {
799 assert(PendingExports[i].getNode()->getNumOperands() > 1);
800 if (PendingExports[i].getNode()->getOperand(0) == Root)
801 break; // Don't add the root if we already indirectly depend on it.
802 }
803
804 if (i == e)
805 PendingExports.push_back(Root);
806 }
807
Dale Johannesen66978ee2009-01-31 02:22:37 +0000808 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000809 &PendingExports[0],
810 PendingExports.size());
811 PendingExports.clear();
812 DAG.setRoot(Root);
813 return Root;
814}
815
816void SelectionDAGLowering::visit(Instruction &I) {
817 visit(I.getOpcode(), I);
818}
819
820void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
821 // Note: this doesn't use InstVisitor, because it has to work with
822 // ConstantExpr's in addition to instructions.
823 switch (Opcode) {
824 default: assert(0 && "Unknown instruction type encountered!");
825 abort();
826 // Build the switch statement using the Instruction.def file.
827#define HANDLE_INST(NUM, OPCODE, CLASS) \
828 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
829#include "llvm/Instruction.def"
830 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000831}
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000832
833void SelectionDAGLowering::visitAdd(User &I) {
834 if (I.getType()->isFPOrFPVector())
835 visitBinary(I, ISD::FADD);
836 else
837 visitBinary(I, ISD::ADD);
838}
839
840void SelectionDAGLowering::visitMul(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FMUL);
843 else
844 visitBinary(I, ISD::MUL);
845}
846
847SDValue SelectionDAGLowering::getValue(const Value *V) {
848 SDValue &N = NodeMap[V];
849 if (N.getNode()) return N;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000850
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000851 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
852 MVT VT = TLI.getValueType(V->getType(), true);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000853
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000854 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
Dan Gohman4fbd7962008-09-12 18:08:03 +0000855 return N = DAG.getConstant(*CI, VT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000856
857 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
858 return N = DAG.getGlobalAddress(GV, VT);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000859
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000860 if (isa<ConstantPointerNull>(C))
861 return N = DAG.getConstant(0, TLI.getPointerTy());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000862
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000863 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
Dan Gohman4fbd7962008-09-12 18:08:03 +0000864 return N = DAG.getConstantFP(*CFP, VT);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000865
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000866 if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
867 !V->getType()->isAggregateType())
Dale Johannesen66978ee2009-01-31 02:22:37 +0000868 return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000869
870 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
871 visit(CE->getOpcode(), *CE);
872 SDValue N1 = NodeMap[V];
873 assert(N1.getNode() && "visit didn't populate the ValueMap!");
874 return N1;
875 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000876
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000877 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
878 SmallVector<SDValue, 4> Constants;
879 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
880 OI != OE; ++OI) {
881 SDNode *Val = getValue(*OI).getNode();
882 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
883 Constants.push_back(SDValue(Val, i));
884 }
Dale Johannesen4be0bdf2009-02-05 00:20:09 +0000885 return DAG.getMergeValues(&Constants[0], Constants.size(),
886 getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000887 }
888
889 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
890 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
891 "Unknown struct or array constant!");
892
893 SmallVector<MVT, 4> ValueVTs;
894 ComputeValueVTs(TLI, C->getType(), ValueVTs);
895 unsigned NumElts = ValueVTs.size();
896 if (NumElts == 0)
897 return SDValue(); // empty struct
898 SmallVector<SDValue, 4> Constants(NumElts);
899 for (unsigned i = 0; i != NumElts; ++i) {
900 MVT EltVT = ValueVTs[i];
901 if (isa<UndefValue>(C))
Dale Johannesen66978ee2009-01-31 02:22:37 +0000902 Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000903 else if (EltVT.isFloatingPoint())
904 Constants[i] = DAG.getConstantFP(0, EltVT);
905 else
906 Constants[i] = DAG.getConstant(0, EltVT);
907 }
Dale Johannesen4be0bdf2009-02-05 00:20:09 +0000908 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000909 }
910
911 const VectorType *VecTy = cast<VectorType>(V->getType());
912 unsigned NumElements = VecTy->getNumElements();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000913
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000914 // Now that we know the number and type of the elements, get that number of
915 // elements into the Ops array based on what kind of constant it is.
916 SmallVector<SDValue, 16> Ops;
917 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
918 for (unsigned i = 0; i != NumElements; ++i)
919 Ops.push_back(getValue(CP->getOperand(i)));
920 } else {
921 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
922 "Unknown vector constant!");
923 MVT EltVT = TLI.getValueType(VecTy->getElementType());
924
925 SDValue Op;
926 if (isa<UndefValue>(C))
Dale Johannesen66978ee2009-01-31 02:22:37 +0000927 Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000928 else if (EltVT.isFloatingPoint())
929 Op = DAG.getConstantFP(0, EltVT);
930 else
931 Op = DAG.getConstant(0, EltVT);
932 Ops.assign(NumElements, Op);
933 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000934
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000935 // Create a BUILD_VECTOR node.
Dale Johannesen66978ee2009-01-31 02:22:37 +0000936 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000937 VT, &Ops[0], Ops.size());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000938 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000939
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000940 // If this is a static alloca, generate it as the frameindex instead of
941 // computation.
942 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
943 DenseMap<const AllocaInst*, int>::iterator SI =
944 FuncInfo.StaticAllocaMap.find(AI);
945 if (SI != FuncInfo.StaticAllocaMap.end())
946 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
947 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000948
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000949 unsigned InReg = FuncInfo.ValueMap[V];
950 assert(InReg && "Value not in map!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000951
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000952 RegsForValue RFV(TLI, InReg, V->getType());
953 SDValue Chain = DAG.getEntryNode();
Dale Johannesen66978ee2009-01-31 02:22:37 +0000954 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000955}
956
957
958void SelectionDAGLowering::visitRet(ReturnInst &I) {
959 if (I.getNumOperands() == 0) {
Dale Johannesen66978ee2009-01-31 02:22:37 +0000960 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +0000961 MVT::Other, getControlRoot()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000962 return;
963 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000964
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000965 SmallVector<SDValue, 8> NewValues;
966 NewValues.push_back(getControlRoot());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000967 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000968 SmallVector<MVT, 4> ValueVTs;
969 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
Dan Gohman7ea1ca62008-10-21 20:00:42 +0000970 unsigned NumValues = ValueVTs.size();
971 if (NumValues == 0) continue;
972
973 SDValue RetOp = getValue(I.getOperand(i));
974 for (unsigned j = 0, f = NumValues; j != f; ++j) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000975 MVT VT = ValueVTs[j];
976
977 // FIXME: C calling convention requires the return type to be promoted to
Dale Johannesenc9c6da62008-09-25 20:47:45 +0000978 // at least 32-bit. But this is not necessary for non-C calling
979 // conventions.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000980 if (VT.isInteger()) {
981 MVT MinVT = TLI.getRegisterType(MVT::i32);
982 if (VT.bitsLT(MinVT))
983 VT = MinVT;
984 }
985
986 unsigned NumParts = TLI.getNumRegisters(VT);
987 MVT PartVT = TLI.getRegisterType(VT);
988 SmallVector<SDValue, 4> Parts(NumParts);
989 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +0000990
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000991 const Function *F = I.getParent()->getParent();
Devang Patel05988662008-09-25 21:00:45 +0000992 if (F->paramHasAttr(0, Attribute::SExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000993 ExtendKind = ISD::SIGN_EXTEND;
Devang Patel05988662008-09-25 21:00:45 +0000994 else if (F->paramHasAttr(0, Attribute::ZExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000995 ExtendKind = ISD::ZERO_EXTEND;
996
Dale Johannesen66978ee2009-01-31 02:22:37 +0000997 getCopyToParts(DAG, getCurDebugLoc(),
998 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +0000999 &Parts[0], NumParts, PartVT, ExtendKind);
1000
Dale Johannesenc9c6da62008-09-25 20:47:45 +00001001 // 'inreg' on function refers to return value
1002 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Devang Patel05988662008-09-25 21:00:45 +00001003 if (F->paramHasAttr(0, Attribute::InReg))
Dale Johannesenc9c6da62008-09-25 20:47:45 +00001004 Flags.setInReg();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001005 for (unsigned i = 0; i < NumParts; ++i) {
1006 NewValues.push_back(Parts[i]);
Dale Johannesenc9c6da62008-09-25 20:47:45 +00001007 NewValues.push_back(DAG.getArgFlags(Flags));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001008 }
1009 }
1010 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00001011 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001012 &NewValues[0], NewValues.size()));
1013}
1014
1015/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1016/// the current basic block, add it to ValueMap now so that we'll get a
1017/// CopyTo/FromReg.
1018void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1019 // No need to export constants.
1020 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001021
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001022 // Already exported?
1023 if (FuncInfo.isExportedInst(V)) return;
1024
1025 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1026 CopyValueToVirtualRegister(V, Reg);
1027}
1028
1029bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1030 const BasicBlock *FromBB) {
1031 // The operands of the setcc have to be in this block. We don't know
1032 // how to export them from some other block.
1033 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1034 // Can export from current BB.
1035 if (VI->getParent() == FromBB)
1036 return true;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001037
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001038 // Is already exported, noop.
1039 return FuncInfo.isExportedInst(V);
1040 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001041
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001042 // If this is an argument, we can export it if the BB is the entry block or
1043 // if it is already exported.
1044 if (isa<Argument>(V)) {
1045 if (FromBB == &FromBB->getParent()->getEntryBlock())
1046 return true;
1047
1048 // Otherwise, can only export this if it is already exported.
1049 return FuncInfo.isExportedInst(V);
1050 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001051
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001052 // Otherwise, constants can always be exported.
1053 return true;
1054}
1055
1056static bool InBlock(const Value *V, const BasicBlock *BB) {
1057 if (const Instruction *I = dyn_cast<Instruction>(V))
1058 return I->getParent() == BB;
1059 return true;
1060}
1061
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001062/// getFCmpCondCode - Return the ISD condition code corresponding to
1063/// the given LLVM IR floating-point condition code. This includes
1064/// consideration of global floating-point math flags.
1065///
1066static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1067 ISD::CondCode FPC, FOC;
1068 switch (Pred) {
1069 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1070 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1071 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1072 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1073 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1074 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1075 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1076 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1077 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1078 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1079 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1080 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1081 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1082 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1083 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1084 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1085 default:
1086 assert(0 && "Invalid FCmp predicate opcode!");
1087 FOC = FPC = ISD::SETFALSE;
1088 break;
1089 }
1090 if (FiniteOnlyFPMath())
1091 return FOC;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001092 else
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001093 return FPC;
1094}
1095
1096/// getICmpCondCode - Return the ISD condition code corresponding to
1097/// the given LLVM IR integer condition code.
1098///
1099static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1100 switch (Pred) {
1101 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1102 case ICmpInst::ICMP_NE: return ISD::SETNE;
1103 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1104 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1105 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1106 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1107 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1108 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1109 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1110 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1111 default:
1112 assert(0 && "Invalid ICmp predicate opcode!");
1113 return ISD::SETNE;
1114 }
1115}
1116
Dan Gohmanc2277342008-10-17 21:16:08 +00001117/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1118/// This function emits a branch and is used at the leaves of an OR or an
1119/// AND operator tree.
1120///
1121void
1122SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1123 MachineBasicBlock *TBB,
1124 MachineBasicBlock *FBB,
1125 MachineBasicBlock *CurBB) {
1126 const BasicBlock *BB = CurBB->getBasicBlock();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001127
Dan Gohmanc2277342008-10-17 21:16:08 +00001128 // If the leaf of the tree is a comparison, merge the condition into
1129 // the caseblock.
1130 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1131 // The operands of the cmp have to be in this block. We don't know
1132 // how to export them from some other block. If this is the first block
1133 // of the sequence, no exporting is needed.
1134 if (CurBB == CurMBB ||
1135 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1136 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001137 ISD::CondCode Condition;
1138 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001139 Condition = getICmpCondCode(IC->getPredicate());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001140 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00001141 Condition = getFCmpCondCode(FC->getPredicate());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001142 } else {
1143 Condition = ISD::SETEQ; // silence warning.
1144 assert(0 && "Unknown compare instruction");
1145 }
Dan Gohmanc2277342008-10-17 21:16:08 +00001146
1147 CaseBlock CB(Condition, BOp->getOperand(0),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001148 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1149 SwitchCases.push_back(CB);
1150 return;
1151 }
Dan Gohmanc2277342008-10-17 21:16:08 +00001152 }
1153
1154 // Create a CaseBlock record representing this branch.
1155 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1156 NULL, TBB, FBB, CurBB);
1157 SwitchCases.push_back(CB);
1158}
1159
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001160/// FindMergedConditions - If Cond is an expression like
Dan Gohmanc2277342008-10-17 21:16:08 +00001161void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1162 MachineBasicBlock *TBB,
1163 MachineBasicBlock *FBB,
1164 MachineBasicBlock *CurBB,
1165 unsigned Opc) {
1166 // If this node is not part of the or/and tree, emit it as a branch.
1167 Instruction *BOp = dyn_cast<Instruction>(Cond);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001168 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
Dan Gohmanc2277342008-10-17 21:16:08 +00001169 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1170 BOp->getParent() != CurBB->getBasicBlock() ||
1171 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1172 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1173 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001174 return;
1175 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001176
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001177 // Create TmpBB after CurBB.
1178 MachineFunction::iterator BBI = CurBB;
1179 MachineFunction &MF = DAG.getMachineFunction();
1180 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1181 CurBB->getParent()->insert(++BBI, TmpBB);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001182
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001183 if (Opc == Instruction::Or) {
1184 // Codegen X | Y as:
1185 // jmp_if_X TBB
1186 // jmp TmpBB
1187 // TmpBB:
1188 // jmp_if_Y TBB
1189 // jmp FBB
1190 //
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001191
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001192 // Emit the LHS condition.
1193 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001194
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001195 // Emit the RHS condition into TmpBB.
1196 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1197 } else {
1198 assert(Opc == Instruction::And && "Unknown merge op!");
1199 // Codegen X & Y as:
1200 // jmp_if_X TmpBB
1201 // jmp FBB
1202 // TmpBB:
1203 // jmp_if_Y TBB
1204 // jmp FBB
1205 //
1206 // This requires creation of TmpBB after CurBB.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001207
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001208 // Emit the LHS condition.
1209 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001210
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001211 // Emit the RHS condition into TmpBB.
1212 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1213 }
1214}
1215
1216/// If the set of cases should be emitted as a series of branches, return true.
1217/// If we should emit this as a bunch of and/or'd together conditions, return
1218/// false.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001219bool
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001220SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1221 if (Cases.size() != 2) return true;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001222
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001223 // If this is two comparisons of the same values or'd or and'd together, they
1224 // will get folded into a single comparison, so don't emit two blocks.
1225 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1226 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1227 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1228 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1229 return false;
1230 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001231
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001232 return true;
1233}
1234
1235void SelectionDAGLowering::visitBr(BranchInst &I) {
1236 // Update machine-CFG edges.
1237 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1238
1239 // Figure out which block is immediately after the current one.
1240 MachineBasicBlock *NextBlock = 0;
1241 MachineFunction::iterator BBI = CurMBB;
1242 if (++BBI != CurMBB->getParent()->end())
1243 NextBlock = BBI;
1244
1245 if (I.isUnconditional()) {
1246 // Update machine-CFG edges.
1247 CurMBB->addSuccessor(Succ0MBB);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001248
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001249 // If this is not a fall-through branch, emit the branch.
1250 if (Succ0MBB != NextBlock)
Dale Johannesen66978ee2009-01-31 02:22:37 +00001251 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001252 MVT::Other, getControlRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001253 DAG.getBasicBlock(Succ0MBB)));
1254 return;
1255 }
1256
1257 // If this condition is one of the special cases we handle, do special stuff
1258 // now.
1259 Value *CondVal = I.getCondition();
1260 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1261
1262 // If this is a series of conditions that are or'd or and'd together, emit
1263 // this as a sequence of branches instead of setcc's with and/or operations.
1264 // For example, instead of something like:
1265 // cmp A, B
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001266 // C = seteq
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001267 // cmp D, E
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001268 // F = setle
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001269 // or C, F
1270 // jnz foo
1271 // Emit:
1272 // cmp A, B
1273 // je foo
1274 // cmp D, E
1275 // jle foo
1276 //
1277 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001278 if (BOp->hasOneUse() &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001279 (BOp->getOpcode() == Instruction::And ||
1280 BOp->getOpcode() == Instruction::Or)) {
1281 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1282 // If the compares in later blocks need to use values not currently
1283 // exported from this block, export them now. This block should always
1284 // be the first entry.
1285 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001286
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001287 // Allow some cases to be rejected.
1288 if (ShouldEmitAsBranches(SwitchCases)) {
1289 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1290 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1291 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1292 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001293
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001294 // Emit the branch for this block.
1295 visitSwitchCase(SwitchCases[0]);
1296 SwitchCases.erase(SwitchCases.begin());
1297 return;
1298 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001299
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001300 // Okay, we decided not to do this, remove any inserted MBB's and clear
1301 // SwitchCases.
1302 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1303 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001304
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001305 SwitchCases.clear();
1306 }
1307 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001308
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001309 // Create a CaseBlock record representing this branch.
1310 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1311 NULL, Succ0MBB, Succ1MBB, CurMBB);
1312 // Use visitSwitchCase to actually insert the fast branch sequence for this
1313 // cond branch.
1314 visitSwitchCase(CB);
1315}
1316
1317/// visitSwitchCase - Emits the necessary code to represent a single node in
1318/// the binary search tree resulting from lowering a switch instruction.
1319void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1320 SDValue Cond;
1321 SDValue CondLHS = getValue(CB.CmpLHS);
Dale Johannesenf5d97892009-02-04 01:48:28 +00001322 DebugLoc dl = getCurDebugLoc();
Anton Korobeynikov23218582008-12-23 22:25:27 +00001323
1324 // Build the setcc now.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001325 if (CB.CmpMHS == NULL) {
1326 // Fold "(X == true)" to X and "(X == false)" to !X to
1327 // handle common cases produced by branch lowering.
1328 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1329 Cond = CondLHS;
1330 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1331 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Dale Johannesenf5d97892009-02-04 01:48:28 +00001332 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001333 } else
Dale Johannesenf5d97892009-02-04 01:48:28 +00001334 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001335 } else {
1336 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1337
Anton Korobeynikov23218582008-12-23 22:25:27 +00001338 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1339 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001340
1341 SDValue CmpOp = getValue(CB.CmpMHS);
1342 MVT VT = CmpOp.getValueType();
1343
1344 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
Dale Johannesenf5d97892009-02-04 01:48:28 +00001345 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1346 ISD::SETLE);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001347 } else {
Dale Johannesenf5d97892009-02-04 01:48:28 +00001348 SDValue SUB = DAG.getNode(ISD::SUB, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001349 VT, CmpOp, DAG.getConstant(Low, VT));
Dale Johannesenf5d97892009-02-04 01:48:28 +00001350 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001351 DAG.getConstant(High-Low, VT), ISD::SETULE);
1352 }
1353 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001354
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001355 // Update successor info
1356 CurMBB->addSuccessor(CB.TrueBB);
1357 CurMBB->addSuccessor(CB.FalseBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001358
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001359 // Set NextBlock to be the MBB immediately after the current one, if any.
1360 // This is used to avoid emitting unnecessary branches to the next block.
1361 MachineBasicBlock *NextBlock = 0;
1362 MachineFunction::iterator BBI = CurMBB;
1363 if (++BBI != CurMBB->getParent()->end())
1364 NextBlock = BBI;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001365
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001366 // If the lhs block is the next block, invert the condition so that we can
1367 // fall through to the lhs instead of the rhs block.
1368 if (CB.TrueBB == NextBlock) {
1369 std::swap(CB.TrueBB, CB.FalseBB);
1370 SDValue True = DAG.getConstant(1, Cond.getValueType());
Dale Johannesenf5d97892009-02-04 01:48:28 +00001371 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001372 }
Dale Johannesenf5d97892009-02-04 01:48:28 +00001373 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001374 MVT::Other, getControlRoot(), Cond,
1375 DAG.getBasicBlock(CB.TrueBB));
Anton Korobeynikov23218582008-12-23 22:25:27 +00001376
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001377 // If the branch was constant folded, fix up the CFG.
1378 if (BrCond.getOpcode() == ISD::BR) {
1379 CurMBB->removeSuccessor(CB.FalseBB);
1380 DAG.setRoot(BrCond);
1381 } else {
1382 // Otherwise, go ahead and insert the false branch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001383 if (BrCond == getControlRoot())
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001384 CurMBB->removeSuccessor(CB.TrueBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001385
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001386 if (CB.FalseBB == NextBlock)
1387 DAG.setRoot(BrCond);
1388 else
Dale Johannesenf5d97892009-02-04 01:48:28 +00001389 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001390 DAG.getBasicBlock(CB.FalseBB)));
1391 }
1392}
1393
1394/// visitJumpTable - Emit JumpTable node in the current MBB
1395void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1396 // Emit the code for the jump table
1397 assert(JT.Reg != -1U && "Should lower JT Header first!");
1398 MVT PTy = TLI.getPointerTy();
Dale Johannesena04b7572009-02-03 23:04:43 +00001399 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1400 JT.Reg, PTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001401 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
Dale Johannesen66978ee2009-01-31 02:22:37 +00001402 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001403 MVT::Other, Index.getValue(1),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001404 Table, Index));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001405}
1406
1407/// visitJumpTableHeader - This function emits necessary code to produce index
1408/// in the JumpTable from switch case.
1409void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1410 JumpTableHeader &JTH) {
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001411 // Subtract the lowest switch case value from the value being switched on and
1412 // conditional branch to default mbb if the result is greater than the
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001413 // difference between smallest and largest cases.
1414 SDValue SwitchOp = getValue(JTH.SValue);
1415 MVT VT = SwitchOp.getValueType();
Dale Johannesen66978ee2009-01-31 02:22:37 +00001416 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001417 DAG.getConstant(JTH.First, VT));
Anton Korobeynikov23218582008-12-23 22:25:27 +00001418
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001419 // The SDNode we just created, which holds the value being switched on minus
1420 // the the smallest case value, needs to be copied to a virtual register so it
1421 // can be used as an index into the jump table in a subsequent basic block.
1422 // This value may be smaller or larger than the target's pointer type, and
1423 // therefore require extension or truncating.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001424 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00001425 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001426 TLI.getPointerTy(), SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001427 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001428 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001429 TLI.getPointerTy(), SUB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001430
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001431 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
Dale Johannesena04b7572009-02-03 23:04:43 +00001432 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1433 JumpTableReg, SwitchOp);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001434 JT.Reg = JumpTableReg;
1435
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001436 // Emit the range check for the jump table, and branch to the default block
1437 // for the switch statement if the value being switched on exceeds the largest
1438 // case in the switch.
Dale Johannesenf5d97892009-02-04 01:48:28 +00001439 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1440 TLI.getSetCCResultType(SUB.getValueType()), SUB,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001441 DAG.getConstant(JTH.Last-JTH.First,VT),
1442 ISD::SETUGT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001443
1444 // Set NextBlock to be the MBB immediately after the current one, if any.
1445 // This is used to avoid emitting unnecessary branches to the next block.
1446 MachineBasicBlock *NextBlock = 0;
1447 MachineFunction::iterator BBI = CurMBB;
1448 if (++BBI != CurMBB->getParent()->end())
1449 NextBlock = BBI;
1450
Dale Johannesen66978ee2009-01-31 02:22:37 +00001451 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001452 MVT::Other, CopyTo, CMP,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001453 DAG.getBasicBlock(JT.Default));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001454
1455 if (JT.MBB == NextBlock)
1456 DAG.setRoot(BrCond);
1457 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001458 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001459 DAG.getBasicBlock(JT.MBB)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001460}
1461
1462/// visitBitTestHeader - This function emits necessary code to produce value
1463/// suitable for "bit tests"
1464void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1465 // Subtract the minimum value
1466 SDValue SwitchOp = getValue(B.SValue);
1467 MVT VT = SwitchOp.getValueType();
Dale Johannesen66978ee2009-01-31 02:22:37 +00001468 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001469 DAG.getConstant(B.First, VT));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001470
1471 // Check range
Dale Johannesenf5d97892009-02-04 01:48:28 +00001472 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1473 TLI.getSetCCResultType(SUB.getValueType()),
1474 SUB, DAG.getConstant(B.Range, VT),
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001475 ISD::SETUGT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001476
1477 SDValue ShiftOp;
Duncan Sands92abc622009-01-31 15:50:11 +00001478 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00001479 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00001480 TLI.getPointerTy(), SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001481 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001482 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00001483 TLI.getPointerTy(), SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001484
Duncan Sands92abc622009-01-31 15:50:11 +00001485 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
Dale Johannesena04b7572009-02-03 23:04:43 +00001486 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1487 B.Reg, ShiftOp);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001488
1489 // Set NextBlock to be the MBB immediately after the current one, if any.
1490 // This is used to avoid emitting unnecessary branches to the next block.
1491 MachineBasicBlock *NextBlock = 0;
1492 MachineFunction::iterator BBI = CurMBB;
1493 if (++BBI != CurMBB->getParent()->end())
1494 NextBlock = BBI;
1495
1496 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1497
1498 CurMBB->addSuccessor(B.Default);
1499 CurMBB->addSuccessor(MBB);
1500
Dale Johannesen66978ee2009-01-31 02:22:37 +00001501 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001502 MVT::Other, CopyTo, RangeCmp,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001503 DAG.getBasicBlock(B.Default));
Anton Korobeynikov23218582008-12-23 22:25:27 +00001504
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001505 if (MBB == NextBlock)
1506 DAG.setRoot(BrRange);
1507 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001508 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001509 DAG.getBasicBlock(MBB)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001510}
1511
1512/// visitBitTestCase - this function produces one "bit test"
1513void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1514 unsigned Reg,
1515 BitTestCase &B) {
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001516 // Make desired shift
Dale Johannesena04b7572009-02-03 23:04:43 +00001517 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
Duncan Sands92abc622009-01-31 15:50:11 +00001518 TLI.getPointerTy());
Dale Johannesen66978ee2009-01-31 02:22:37 +00001519 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001520 TLI.getPointerTy(),
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001521 DAG.getConstant(1, TLI.getPointerTy()),
1522 ShiftOp);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001523
Anton Korobeynikov36c826a2009-01-26 19:26:01 +00001524 // Emit bit tests and jumps
Dale Johannesen66978ee2009-01-31 02:22:37 +00001525 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001526 TLI.getPointerTy(), SwitchVal,
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001527 DAG.getConstant(B.Mask, TLI.getPointerTy()));
Dale Johannesenf5d97892009-02-04 01:48:28 +00001528 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1529 TLI.getSetCCResultType(AndOp.getValueType()),
Duncan Sands5480c042009-01-01 15:52:00 +00001530 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001531 ISD::SETNE);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001532
1533 CurMBB->addSuccessor(B.TargetBB);
1534 CurMBB->addSuccessor(NextMBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001535
Dale Johannesen66978ee2009-01-31 02:22:37 +00001536 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001537 MVT::Other, getControlRoot(),
Anton Korobeynikov1bfe2372008-12-23 22:25:45 +00001538 AndCmp, DAG.getBasicBlock(B.TargetBB));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001539
1540 // Set NextBlock to be the MBB immediately after the current one, if any.
1541 // This is used to avoid emitting unnecessary branches to the next block.
1542 MachineBasicBlock *NextBlock = 0;
1543 MachineFunction::iterator BBI = CurMBB;
1544 if (++BBI != CurMBB->getParent()->end())
1545 NextBlock = BBI;
1546
1547 if (NextMBB == NextBlock)
1548 DAG.setRoot(BrAnd);
1549 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00001550 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001551 DAG.getBasicBlock(NextMBB)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001552}
1553
1554void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1555 // Retrieve successors.
1556 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1557 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1558
Gabor Greifb67e6b32009-01-15 11:10:44 +00001559 const Value *Callee(I.getCalledValue());
1560 if (isa<InlineAsm>(Callee))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001561 visitInlineAsm(&I);
1562 else
Gabor Greifb67e6b32009-01-15 11:10:44 +00001563 LowerCallTo(&I, getValue(Callee), false, LandingPad);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001564
1565 // If the value of the invoke is used outside of its defining block, make it
1566 // available as a virtual register.
1567 if (!I.use_empty()) {
1568 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1569 if (VMI != FuncInfo.ValueMap.end())
1570 CopyValueToVirtualRegister(&I, VMI->second);
1571 }
1572
1573 // Update successor info
1574 CurMBB->addSuccessor(Return);
1575 CurMBB->addSuccessor(LandingPad);
1576
1577 // Drop into normal successor.
Dale Johannesen66978ee2009-01-31 02:22:37 +00001578 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00001579 MVT::Other, getControlRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001580 DAG.getBasicBlock(Return)));
1581}
1582
1583void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1584}
1585
1586/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1587/// small case ranges).
1588bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1589 CaseRecVector& WorkList,
1590 Value* SV,
1591 MachineBasicBlock* Default) {
1592 Case& BackCase = *(CR.Range.second-1);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001593
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001594 // Size is the number of Cases represented by this range.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001595 size_t Size = CR.Range.second - CR.Range.first;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001596 if (Size > 3)
Anton Korobeynikov23218582008-12-23 22:25:27 +00001597 return false;
1598
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001599 // Get the MachineFunction which holds the current MBB. This is used when
1600 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001601 MachineFunction *CurMF = CurMBB->getParent();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001602
1603 // Figure out which block is immediately after the current one.
1604 MachineBasicBlock *NextBlock = 0;
1605 MachineFunction::iterator BBI = CR.CaseBB;
1606
1607 if (++BBI != CurMBB->getParent()->end())
1608 NextBlock = BBI;
1609
1610 // TODO: If any two of the cases has the same destination, and if one value
1611 // is the same as the other, but has one bit unset that the other has set,
1612 // use bit manipulation to do two compares at once. For example:
1613 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
Anton Korobeynikov23218582008-12-23 22:25:27 +00001614
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001615 // Rearrange the case blocks so that the last one falls through if possible.
1616 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1617 // The last case block won't fall through into 'NextBlock' if we emit the
1618 // branches in this order. See if rearranging a case value would help.
1619 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1620 if (I->BB == NextBlock) {
1621 std::swap(*I, BackCase);
1622 break;
1623 }
1624 }
1625 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001626
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001627 // Create a CaseBlock record representing a conditional branch to
1628 // the Case's target mbb if the value being switched on SV is equal
1629 // to C.
1630 MachineBasicBlock *CurBlock = CR.CaseBB;
1631 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1632 MachineBasicBlock *FallThrough;
1633 if (I != E-1) {
1634 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1635 CurMF->insert(BBI, FallThrough);
1636 } else {
1637 // If the last case doesn't match, go to the default block.
1638 FallThrough = Default;
1639 }
1640
1641 Value *RHS, *LHS, *MHS;
1642 ISD::CondCode CC;
1643 if (I->High == I->Low) {
1644 // This is just small small case range :) containing exactly 1 case
1645 CC = ISD::SETEQ;
1646 LHS = SV; RHS = I->High; MHS = NULL;
1647 } else {
1648 CC = ISD::SETLE;
1649 LHS = I->Low; MHS = SV; RHS = I->High;
1650 }
1651 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001652
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001653 // If emitting the first comparison, just call visitSwitchCase to emit the
1654 // code into the current block. Otherwise, push the CaseBlock onto the
1655 // vector to be later processed by SDISel, and insert the node's MBB
1656 // before the next MBB.
1657 if (CurBlock == CurMBB)
1658 visitSwitchCase(CB);
1659 else
1660 SwitchCases.push_back(CB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001661
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001662 CurBlock = FallThrough;
1663 }
1664
1665 return true;
1666}
1667
1668static inline bool areJTsAllowed(const TargetLowering &TLI) {
1669 return !DisableJumpTables &&
Dan Gohmanf560ffa2009-01-28 17:46:25 +00001670 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1671 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001672}
Anton Korobeynikov23218582008-12-23 22:25:27 +00001673
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001674static APInt ComputeRange(const APInt &First, const APInt &Last) {
1675 APInt LastExt(Last), FirstExt(First);
1676 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1677 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1678 return (LastExt - FirstExt + 1ULL);
1679}
1680
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001681/// handleJTSwitchCase - Emit jumptable for current switch case range
1682bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1683 CaseRecVector& WorkList,
1684 Value* SV,
1685 MachineBasicBlock* Default) {
1686 Case& FrontCase = *CR.Range.first;
1687 Case& BackCase = *(CR.Range.second-1);
1688
Anton Korobeynikov23218582008-12-23 22:25:27 +00001689 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1690 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001691
Anton Korobeynikov23218582008-12-23 22:25:27 +00001692 size_t TSize = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001693 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1694 I!=E; ++I)
1695 TSize += I->size();
1696
1697 if (!areJTsAllowed(TLI) || TSize <= 3)
1698 return false;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001699
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001700 APInt Range = ComputeRange(First, Last);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001701 double Density = (double)TSize / Range.roundToDouble();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001702 if (Density < 0.4)
1703 return false;
1704
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001705 DEBUG(errs() << "Lowering jump table\n"
1706 << "First entry: " << First << ". Last entry: " << Last << '\n'
1707 << "Range: " << Range
1708 << "Size: " << TSize << ". Density: " << Density << "\n\n");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001709
1710 // Get the MachineFunction which holds the current MBB. This is used when
1711 // inserting any additional MBBs necessary to represent the switch.
1712 MachineFunction *CurMF = CurMBB->getParent();
1713
1714 // Figure out which block is immediately after the current one.
1715 MachineBasicBlock *NextBlock = 0;
1716 MachineFunction::iterator BBI = CR.CaseBB;
1717
1718 if (++BBI != CurMBB->getParent()->end())
1719 NextBlock = BBI;
1720
1721 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1722
1723 // Create a new basic block to hold the code for loading the address
1724 // of the jump table, and jumping to it. Update successor information;
1725 // we will either branch to the default case for the switch, or the jump
1726 // table.
1727 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1728 CurMF->insert(BBI, JumpTableBB);
1729 CR.CaseBB->addSuccessor(Default);
1730 CR.CaseBB->addSuccessor(JumpTableBB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001731
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001732 // Build a vector of destination BBs, corresponding to each target
1733 // of the jump table. If the value of the jump table slot corresponds to
1734 // a case statement, push the case's BB onto the vector, otherwise, push
1735 // the default BB.
1736 std::vector<MachineBasicBlock*> DestBBs;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001737 APInt TEI = First;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001738 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001739 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1740 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1741
1742 if (Low.sle(TEI) && TEI.sle(High)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001743 DestBBs.push_back(I->BB);
1744 if (TEI==High)
1745 ++I;
1746 } else {
1747 DestBBs.push_back(Default);
1748 }
1749 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001750
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001751 // Update successor info. Add one edge to each unique successor.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001752 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1753 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001754 E = DestBBs.end(); I != E; ++I) {
1755 if (!SuccsHandled[(*I)->getNumber()]) {
1756 SuccsHandled[(*I)->getNumber()] = true;
1757 JumpTableBB->addSuccessor(*I);
1758 }
1759 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001760
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001761 // Create a jump table index for this jump table, or return an existing
1762 // one.
1763 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001764
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001765 // Set the jump table information so that we can codegen it as a second
1766 // MachineBasicBlock
1767 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1768 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1769 if (CR.CaseBB == CurMBB)
1770 visitJumpTableHeader(JT, JTH);
Anton Korobeynikov23218582008-12-23 22:25:27 +00001771
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001772 JTCases.push_back(JumpTableBlock(JTH, JT));
1773
1774 return true;
1775}
1776
1777/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1778/// 2 subtrees.
1779bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1780 CaseRecVector& WorkList,
1781 Value* SV,
1782 MachineBasicBlock* Default) {
1783 // Get the MachineFunction which holds the current MBB. This is used when
1784 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001785 MachineFunction *CurMF = CurMBB->getParent();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001786
1787 // Figure out which block is immediately after the current one.
1788 MachineBasicBlock *NextBlock = 0;
1789 MachineFunction::iterator BBI = CR.CaseBB;
1790
1791 if (++BBI != CurMBB->getParent()->end())
1792 NextBlock = BBI;
1793
1794 Case& FrontCase = *CR.Range.first;
1795 Case& BackCase = *(CR.Range.second-1);
1796 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1797
1798 // Size is the number of Cases represented by this range.
1799 unsigned Size = CR.Range.second - CR.Range.first;
1800
Anton Korobeynikov23218582008-12-23 22:25:27 +00001801 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1802 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001803 double FMetric = 0;
1804 CaseItr Pivot = CR.Range.first + Size/2;
1805
1806 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1807 // (heuristically) allow us to emit JumpTable's later.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001808 size_t TSize = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001809 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1810 I!=E; ++I)
1811 TSize += I->size();
1812
Anton Korobeynikov23218582008-12-23 22:25:27 +00001813 size_t LSize = FrontCase.size();
1814 size_t RSize = TSize-LSize;
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001815 DEBUG(errs() << "Selecting best pivot: \n"
1816 << "First: " << First << ", Last: " << Last <<'\n'
1817 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001818 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1819 J!=E; ++I, ++J) {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001820 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1821 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001822 APInt Range = ComputeRange(LEnd, RBegin);
1823 assert((Range - 2ULL).isNonNegative() &&
1824 "Invalid case distance");
Anton Korobeynikov23218582008-12-23 22:25:27 +00001825 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1826 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001827 double Metric = Range.logBase2()*(LDensity+RDensity);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001828 // Should always split in some non-trivial place
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001829 DEBUG(errs() <<"=>Step\n"
1830 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1831 << "LDensity: " << LDensity
1832 << ", RDensity: " << RDensity << '\n'
1833 << "Metric: " << Metric << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001834 if (FMetric < Metric) {
1835 Pivot = J;
1836 FMetric = Metric;
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001837 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001838 }
1839
1840 LSize += J->size();
1841 RSize -= J->size();
1842 }
1843 if (areJTsAllowed(TLI)) {
1844 // If our case is dense we *really* should handle it earlier!
1845 assert((FMetric > 0) && "Should handle dense range earlier!");
1846 } else {
1847 Pivot = CR.Range.first + Size/2;
1848 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001849
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001850 CaseRange LHSR(CR.Range.first, Pivot);
1851 CaseRange RHSR(Pivot, CR.Range.second);
1852 Constant *C = Pivot->Low;
1853 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001854
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001855 // We know that we branch to the LHS if the Value being switched on is
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001856 // less than the Pivot value, C. We use this to optimize our binary
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001857 // tree a bit, by recognizing that if SV is greater than or equal to the
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001858 // LHS's Case Value, and that Case Value is exactly one less than the
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001859 // Pivot's Value, then we can branch directly to the LHS's Target,
1860 // rather than creating a leaf node for it.
1861 if ((LHSR.second - LHSR.first) == 1 &&
1862 LHSR.first->High == CR.GE &&
Anton Korobeynikov23218582008-12-23 22:25:27 +00001863 cast<ConstantInt>(C)->getValue() ==
1864 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001865 TrueBB = LHSR.first->BB;
1866 } else {
1867 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1868 CurMF->insert(BBI, TrueBB);
1869 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1870 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001871
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001872 // Similar to the optimization above, if the Value being switched on is
1873 // known to be less than the Constant CR.LT, and the current Case Value
1874 // is CR.LT - 1, then we can branch directly to the target block for
1875 // the current Case Value, rather than emitting a RHS leaf node for it.
1876 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
Anton Korobeynikov23218582008-12-23 22:25:27 +00001877 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1878 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001879 FalseBB = RHSR.first->BB;
1880 } else {
1881 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1882 CurMF->insert(BBI, FalseBB);
1883 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1884 }
1885
1886 // Create a CaseBlock record representing a conditional branch to
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00001887 // the LHS node if the value being switched on SV is less than C.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001888 // Otherwise, branch to LHS.
1889 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1890
1891 if (CR.CaseBB == CurMBB)
1892 visitSwitchCase(CB);
1893 else
1894 SwitchCases.push_back(CB);
1895
1896 return true;
1897}
1898
1899/// handleBitTestsSwitchCase - if current case range has few destination and
1900/// range span less, than machine word bitwidth, encode case range into series
1901/// of masks and emit bit tests with these masks.
1902bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1903 CaseRecVector& WorkList,
1904 Value* SV,
1905 MachineBasicBlock* Default){
1906 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1907
1908 Case& FrontCase = *CR.Range.first;
1909 Case& BackCase = *(CR.Range.second-1);
1910
1911 // Get the MachineFunction which holds the current MBB. This is used when
1912 // inserting any additional MBBs necessary to represent the switch.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001913 MachineFunction *CurMF = CurMBB->getParent();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001914
Anton Korobeynikov23218582008-12-23 22:25:27 +00001915 size_t numCmps = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001916 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1917 I!=E; ++I) {
1918 // Single case counts one, case range - two.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001919 numCmps += (I->Low == I->High ? 1 : 2);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001920 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001921
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001922 // Count unique destinations
1923 SmallSet<MachineBasicBlock*, 4> Dests;
1924 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1925 Dests.insert(I->BB);
1926 if (Dests.size() > 3)
1927 // Don't bother the code below, if there are too much unique destinations
1928 return false;
1929 }
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001930 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1931 << "Total number of comparisons: " << numCmps << '\n');
Anton Korobeynikov23218582008-12-23 22:25:27 +00001932
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001933 // Compute span of values.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001934 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1935 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00001936 APInt cmpRange = maxValue - minValue;
1937
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001938 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1939 << "Low bound: " << minValue << '\n'
1940 << "High bound: " << maxValue << '\n');
Anton Korobeynikov23218582008-12-23 22:25:27 +00001941
1942 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001943 (!(Dests.size() == 1 && numCmps >= 3) &&
1944 !(Dests.size() == 2 && numCmps >= 5) &&
1945 !(Dests.size() >= 3 && numCmps >= 6)))
1946 return false;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001947
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001948 DEBUG(errs() << "Emitting bit tests\n");
Anton Korobeynikov23218582008-12-23 22:25:27 +00001949 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1950
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001951 // Optimize the case where all the case values fit in a
1952 // word without having to subtract minValue. In this case,
1953 // we can optimize away the subtraction.
Anton Korobeynikov23218582008-12-23 22:25:27 +00001954 if (minValue.isNonNegative() &&
1955 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1956 cmpRange = maxValue;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001957 } else {
Anton Korobeynikov23218582008-12-23 22:25:27 +00001958 lowBound = minValue;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001959 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001960
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001961 CaseBitsVector CasesBits;
1962 unsigned i, count = 0;
1963
1964 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1965 MachineBasicBlock* Dest = I->BB;
1966 for (i = 0; i < count; ++i)
1967 if (Dest == CasesBits[i].BB)
1968 break;
Anton Korobeynikov23218582008-12-23 22:25:27 +00001969
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001970 if (i == count) {
1971 assert((count < 3) && "Too much destinations to test!");
1972 CasesBits.push_back(CaseBits(0, Dest, 0));
1973 count++;
1974 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001975
1976 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1977 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1978
1979 uint64_t lo = (lowValue - lowBound).getZExtValue();
1980 uint64_t hi = (highValue - lowBound).getZExtValue();
1981
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001982 for (uint64_t j = lo; j <= hi; j++) {
1983 CasesBits[i].Mask |= 1ULL << j;
1984 CasesBits[i].Bits++;
1985 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00001986
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001987 }
1988 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
Anton Korobeynikov23218582008-12-23 22:25:27 +00001989
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001990 BitTestInfo BTC;
1991
1992 // Figure out which block is immediately after the current one.
1993 MachineFunction::iterator BBI = CR.CaseBB;
1994 ++BBI;
1995
1996 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1997
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00001998 DEBUG(errs() << "Cases:\n");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00001999 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00002000 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2001 << ", Bits: " << CasesBits[i].Bits
2002 << ", BB: " << CasesBits[i].BB << '\n');
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002003
2004 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2005 CurMF->insert(BBI, CaseBB);
2006 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2007 CaseBB,
2008 CasesBits[i].BB));
2009 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00002010
2011 BitTestBlock BTB(lowBound, cmpRange, SV,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002012 -1U, (CR.CaseBB == CurMBB),
2013 CR.CaseBB, Default, BTC);
2014
2015 if (CR.CaseBB == CurMBB)
2016 visitBitTestHeader(BTB);
Anton Korobeynikov23218582008-12-23 22:25:27 +00002017
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002018 BitTestCases.push_back(BTB);
2019
2020 return true;
2021}
2022
2023
2024/// Clusterify - Transform simple list of Cases into list of CaseRange's
Anton Korobeynikov23218582008-12-23 22:25:27 +00002025size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002026 const SwitchInst& SI) {
Anton Korobeynikov23218582008-12-23 22:25:27 +00002027 size_t numCmps = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002028
2029 // Start with "simple" cases
Anton Korobeynikov23218582008-12-23 22:25:27 +00002030 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002031 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2032 Cases.push_back(Case(SI.getSuccessorValue(i),
2033 SI.getSuccessorValue(i),
2034 SMBB));
2035 }
2036 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2037
2038 // Merge case into clusters
Anton Korobeynikov23218582008-12-23 22:25:27 +00002039 if (Cases.size() >= 2)
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002040 // Must recompute end() each iteration because it may be
2041 // invalidated by erase if we hold on to it
Anton Korobeynikov23218582008-12-23 22:25:27 +00002042 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2043 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2044 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002045 MachineBasicBlock* nextBB = J->BB;
2046 MachineBasicBlock* currentBB = I->BB;
2047
2048 // If the two neighboring cases go to the same destination, merge them
2049 // into a single case.
Anton Korobeynikov23218582008-12-23 22:25:27 +00002050 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002051 I->High = J->High;
2052 J = Cases.erase(J);
2053 } else {
2054 I = J++;
2055 }
2056 }
2057
2058 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2059 if (I->Low != I->High)
2060 // A range counts double, since it requires two compares.
2061 ++numCmps;
2062 }
2063
2064 return numCmps;
2065}
2066
Anton Korobeynikov23218582008-12-23 22:25:27 +00002067void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002068 // Figure out which block is immediately after the current one.
2069 MachineBasicBlock *NextBlock = 0;
2070 MachineFunction::iterator BBI = CurMBB;
2071
2072 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2073
2074 // If there is only the default destination, branch to it if it is not the
2075 // next basic block. Otherwise, just fall through.
2076 if (SI.getNumOperands() == 2) {
2077 // Update machine-CFG edges.
2078
2079 // If this is not a fall-through branch, emit the branch.
2080 CurMBB->addSuccessor(Default);
2081 if (Default != NextBlock)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002082 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002083 MVT::Other, getControlRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002084 DAG.getBasicBlock(Default)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002085 return;
2086 }
Anton Korobeynikov23218582008-12-23 22:25:27 +00002087
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002088 // If there are any non-default case statements, create a vector of Cases
2089 // representing each one, and sort the vector so that we can efficiently
2090 // create a binary search tree from them.
2091 CaseVector Cases;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002092 size_t numCmps = Clusterify(Cases, SI);
Anton Korobeynikov56d245b2008-12-23 22:26:18 +00002093 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2094 << ". Total compares: " << numCmps << '\n');
Devang Patel8a84e442009-01-05 17:31:22 +00002095 numCmps = 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002096
2097 // Get the Value to be switched on and default basic blocks, which will be
2098 // inserted into CaseBlock records, representing basic blocks in the binary
2099 // search tree.
2100 Value *SV = SI.getOperand(0);
2101
2102 // Push the initial CaseRec onto the worklist
2103 CaseRecVector WorkList;
2104 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2105
2106 while (!WorkList.empty()) {
2107 // Grab a record representing a case range to process off the worklist
2108 CaseRec CR = WorkList.back();
2109 WorkList.pop_back();
2110
2111 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2112 continue;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002113
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002114 // If the range has few cases (two or less) emit a series of specific
2115 // tests.
2116 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2117 continue;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002118
Anton Korobeynikove2f95e92008-12-23 22:26:01 +00002119 // If the switch has more than 5 blocks, and at least 40% dense, and the
2120 // target supports indirect branches, then emit a jump table rather than
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002121 // lowering the switch to a binary tree of conditional branches.
2122 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2123 continue;
Anton Korobeynikov23218582008-12-23 22:25:27 +00002124
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002125 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2126 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2127 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2128 }
2129}
2130
2131
2132void SelectionDAGLowering::visitSub(User &I) {
2133 // -0.0 - X --> fneg
2134 const Type *Ty = I.getType();
2135 if (isa<VectorType>(Ty)) {
2136 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2137 const VectorType *DestTy = cast<VectorType>(I.getType());
2138 const Type *ElTy = DestTy->getElementType();
2139 if (ElTy->isFloatingPoint()) {
2140 unsigned VL = DestTy->getNumElements();
2141 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2142 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2143 if (CV == CNZ) {
2144 SDValue Op2 = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002145 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002146 Op2.getValueType(), Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002147 return;
2148 }
2149 }
2150 }
2151 }
2152 if (Ty->isFloatingPoint()) {
2153 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2154 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2155 SDValue Op2 = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002156 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002157 Op2.getValueType(), Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002158 return;
2159 }
2160 }
2161
2162 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2163}
2164
2165void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2166 SDValue Op1 = getValue(I.getOperand(0));
2167 SDValue Op2 = getValue(I.getOperand(1));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002168
Dale Johannesen66978ee2009-01-31 02:22:37 +00002169 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002170 Op1.getValueType(), Op1, Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002171}
2172
2173void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2174 SDValue Op1 = getValue(I.getOperand(0));
2175 SDValue Op2 = getValue(I.getOperand(1));
2176 if (!isa<VectorType>(I.getType())) {
Duncan Sands92abc622009-01-31 15:50:11 +00002177 if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002178 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00002179 TLI.getPointerTy(), Op2);
2180 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002181 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
Duncan Sands92abc622009-01-31 15:50:11 +00002182 TLI.getPointerTy(), Op2);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002183 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002184
Dale Johannesen66978ee2009-01-31 02:22:37 +00002185 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002186 Op1.getValueType(), Op1, Op2));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002187}
2188
2189void SelectionDAGLowering::visitICmp(User &I) {
2190 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2191 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2192 predicate = IC->getPredicate();
2193 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2194 predicate = ICmpInst::Predicate(IC->getPredicate());
2195 SDValue Op1 = getValue(I.getOperand(0));
2196 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002197 ISD::CondCode Opcode = getICmpCondCode(predicate);
Dale Johannesenf5d97892009-02-04 01:48:28 +00002198 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002199}
2200
2201void SelectionDAGLowering::visitFCmp(User &I) {
2202 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2203 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2204 predicate = FC->getPredicate();
2205 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2206 predicate = FCmpInst::Predicate(FC->getPredicate());
2207 SDValue Op1 = getValue(I.getOperand(0));
2208 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002209 ISD::CondCode Condition = getFCmpCondCode(predicate);
Dale Johannesenf5d97892009-02-04 01:48:28 +00002210 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002211}
2212
2213void SelectionDAGLowering::visitVICmp(User &I) {
2214 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2215 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2216 predicate = IC->getPredicate();
2217 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2218 predicate = ICmpInst::Predicate(IC->getPredicate());
2219 SDValue Op1 = getValue(I.getOperand(0));
2220 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002221 ISD::CondCode Opcode = getICmpCondCode(predicate);
Dale Johannesenf5d97892009-02-04 01:48:28 +00002222 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2223 Op1, Op2, Opcode));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002224}
2225
2226void SelectionDAGLowering::visitVFCmp(User &I) {
2227 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2228 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2229 predicate = FC->getPredicate();
2230 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2231 predicate = FCmpInst::Predicate(FC->getPredicate());
2232 SDValue Op1 = getValue(I.getOperand(0));
2233 SDValue Op2 = getValue(I.getOperand(1));
Dan Gohman8c1a6ca2008-10-17 18:18:45 +00002234 ISD::CondCode Condition = getFCmpCondCode(predicate);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002235 MVT DestVT = TLI.getValueType(I.getType());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002236
Dale Johannesenf5d97892009-02-04 01:48:28 +00002237 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002238}
2239
2240void SelectionDAGLowering::visitSelect(User &I) {
Dan Gohman7ea1ca62008-10-21 20:00:42 +00002241 SmallVector<MVT, 4> ValueVTs;
2242 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2243 unsigned NumValues = ValueVTs.size();
2244 if (NumValues != 0) {
2245 SmallVector<SDValue, 4> Values(NumValues);
2246 SDValue Cond = getValue(I.getOperand(0));
2247 SDValue TrueVal = getValue(I.getOperand(1));
2248 SDValue FalseVal = getValue(I.getOperand(2));
2249
2250 for (unsigned i = 0; i != NumValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002251 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002252 TrueVal.getValueType(), Cond,
Dan Gohman7ea1ca62008-10-21 20:00:42 +00002253 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2254 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2255
Dale Johannesen66978ee2009-01-31 02:22:37 +00002256 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002257 DAG.getVTList(&ValueVTs[0], NumValues),
2258 &Values[0], NumValues));
Dan Gohman7ea1ca62008-10-21 20:00:42 +00002259 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002260}
2261
2262
2263void SelectionDAGLowering::visitTrunc(User &I) {
2264 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2265 SDValue N = getValue(I.getOperand(0));
2266 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002267 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002268}
2269
2270void SelectionDAGLowering::visitZExt(User &I) {
2271 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2272 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2273 SDValue N = getValue(I.getOperand(0));
2274 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002275 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002276}
2277
2278void SelectionDAGLowering::visitSExt(User &I) {
2279 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2280 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2281 SDValue N = getValue(I.getOperand(0));
2282 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002283 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002284}
2285
2286void SelectionDAGLowering::visitFPTrunc(User &I) {
2287 // FPTrunc is never a no-op cast, no need to check
2288 SDValue N = getValue(I.getOperand(0));
2289 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002290 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002291 DestVT, N, DAG.getIntPtrConstant(0)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002292}
2293
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002294void SelectionDAGLowering::visitFPExt(User &I){
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002295 // FPTrunc is never a no-op cast, no need to check
2296 SDValue N = getValue(I.getOperand(0));
2297 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002298 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002299}
2300
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002301void SelectionDAGLowering::visitFPToUI(User &I) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002302 // FPToUI is never a no-op cast, no need to check
2303 SDValue N = getValue(I.getOperand(0));
2304 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002305 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002306}
2307
2308void SelectionDAGLowering::visitFPToSI(User &I) {
2309 // FPToSI is never a no-op cast, no need to check
2310 SDValue N = getValue(I.getOperand(0));
2311 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002312 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002313}
2314
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002315void SelectionDAGLowering::visitUIToFP(User &I) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002316 // UIToFP is never a no-op cast, no need to check
2317 SDValue N = getValue(I.getOperand(0));
2318 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002319 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002320}
2321
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002322void SelectionDAGLowering::visitSIToFP(User &I){
Bill Wendling181b6272008-10-19 20:34:04 +00002323 // SIToFP is never a no-op cast, no need to check
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002324 SDValue N = getValue(I.getOperand(0));
2325 MVT DestVT = TLI.getValueType(I.getType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002326 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002327}
2328
2329void SelectionDAGLowering::visitPtrToInt(User &I) {
2330 // What to do depends on the size of the integer and the size of the pointer.
2331 // We can either truncate, zero extend, or no-op, accordingly.
2332 SDValue N = getValue(I.getOperand(0));
2333 MVT SrcVT = N.getValueType();
2334 MVT DestVT = TLI.getValueType(I.getType());
2335 SDValue Result;
2336 if (DestVT.bitsLT(SrcVT))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002337 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002338 else
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002339 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
Dale Johannesen66978ee2009-01-31 02:22:37 +00002340 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002341 setValue(&I, Result);
2342}
2343
2344void SelectionDAGLowering::visitIntToPtr(User &I) {
2345 // What to do depends on the size of the integer and the size of the pointer.
2346 // We can either truncate, zero extend, or no-op, accordingly.
2347 SDValue N = getValue(I.getOperand(0));
2348 MVT SrcVT = N.getValueType();
2349 MVT DestVT = TLI.getValueType(I.getType());
2350 if (DestVT.bitsLT(SrcVT))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002351 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002352 else
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002353 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
Dale Johannesen66978ee2009-01-31 02:22:37 +00002354 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002355 DestVT, N));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002356}
2357
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002358void SelectionDAGLowering::visitBitCast(User &I) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002359 SDValue N = getValue(I.getOperand(0));
2360 MVT DestVT = TLI.getValueType(I.getType());
2361
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002362 // BitCast assures us that source and destination are the same size so this
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002363 // is either a BIT_CONVERT or a no-op.
2364 if (DestVT != N.getValueType())
Dale Johannesen66978ee2009-01-31 02:22:37 +00002365 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002366 DestVT, N)); // convert types
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002367 else
2368 setValue(&I, N); // noop cast.
2369}
2370
2371void SelectionDAGLowering::visitInsertElement(User &I) {
2372 SDValue InVec = getValue(I.getOperand(0));
2373 SDValue InVal = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002374 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002375 TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002376 getValue(I.getOperand(2)));
2377
Dale Johannesen66978ee2009-01-31 02:22:37 +00002378 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002379 TLI.getValueType(I.getType()),
2380 InVec, InVal, InIdx));
2381}
2382
2383void SelectionDAGLowering::visitExtractElement(User &I) {
2384 SDValue InVec = getValue(I.getOperand(0));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002385 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002386 TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002387 getValue(I.getOperand(1)));
Dale Johannesen66978ee2009-01-31 02:22:37 +00002388 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002389 TLI.getValueType(I.getType()), InVec, InIdx));
2390}
2391
Mon P Wangaeb06d22008-11-10 04:46:22 +00002392
2393// Utility for visitShuffleVector - Returns true if the mask is mask starting
2394// from SIndx and increasing to the element length (undefs are allowed).
2395static bool SequentialMask(SDValue Mask, unsigned SIndx) {
Mon P Wangc7849c22008-11-16 05:06:27 +00002396 unsigned MaskNumElts = Mask.getNumOperands();
2397 for (unsigned i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002398 if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
2399 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2400 if (Idx != i + SIndx)
2401 return false;
2402 }
2403 }
2404 return true;
2405}
2406
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002407void SelectionDAGLowering::visitShuffleVector(User &I) {
Mon P Wang230e4fa2008-11-21 04:25:21 +00002408 SDValue Src1 = getValue(I.getOperand(0));
2409 SDValue Src2 = getValue(I.getOperand(1));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002410 SDValue Mask = getValue(I.getOperand(2));
2411
Mon P Wangaeb06d22008-11-10 04:46:22 +00002412 MVT VT = TLI.getValueType(I.getType());
Mon P Wang230e4fa2008-11-21 04:25:21 +00002413 MVT SrcVT = Src1.getValueType();
Mon P Wangc7849c22008-11-16 05:06:27 +00002414 int MaskNumElts = Mask.getNumOperands();
2415 int SrcNumElts = SrcVT.getVectorNumElements();
Mon P Wangaeb06d22008-11-10 04:46:22 +00002416
Mon P Wangc7849c22008-11-16 05:06:27 +00002417 if (SrcNumElts == MaskNumElts) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002418 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002419 VT, Src1, Src2, Mask));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002420 return;
2421 }
2422
2423 // Normalize the shuffle vector since mask and vector length don't match.
Mon P Wangc7849c22008-11-16 05:06:27 +00002424 MVT MaskEltVT = Mask.getValueType().getVectorElementType();
2425
2426 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2427 // Mask is longer than the source vectors and is a multiple of the source
2428 // vectors. We can use concatenate vector to make the mask and vectors
Mon P Wang230e4fa2008-11-21 04:25:21 +00002429 // lengths match.
Mon P Wangc7849c22008-11-16 05:06:27 +00002430 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2431 // The shuffle is concatenating two vectors together.
Dale Johannesen66978ee2009-01-31 02:22:37 +00002432 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002433 VT, Src1, Src2));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002434 return;
2435 }
2436
Mon P Wangc7849c22008-11-16 05:06:27 +00002437 // Pad both vectors with undefs to make them the same length as the mask.
2438 unsigned NumConcat = MaskNumElts / SrcNumElts;
Dale Johannesen66978ee2009-01-31 02:22:37 +00002439 SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
Mon P Wangaeb06d22008-11-10 04:46:22 +00002440
Mon P Wang230e4fa2008-11-21 04:25:21 +00002441 SDValue* MOps1 = new SDValue[NumConcat];
2442 SDValue* MOps2 = new SDValue[NumConcat];
2443 MOps1[0] = Src1;
2444 MOps2[0] = Src2;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002445 for (unsigned i = 1; i != NumConcat; ++i) {
Mon P Wang230e4fa2008-11-21 04:25:21 +00002446 MOps1[i] = UndefVal;
2447 MOps2[i] = UndefVal;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002448 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002449 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002450 VT, MOps1, NumConcat);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002451 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002452 VT, MOps2, NumConcat);
Mon P Wang230e4fa2008-11-21 04:25:21 +00002453
2454 delete [] MOps1;
2455 delete [] MOps2;
2456
Mon P Wangaeb06d22008-11-10 04:46:22 +00002457 // Readjust mask for new input vector length.
2458 SmallVector<SDValue, 8> MappedOps;
Mon P Wangc7849c22008-11-16 05:06:27 +00002459 for (int i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002460 if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
2461 MappedOps.push_back(Mask.getOperand(i));
2462 } else {
Mon P Wangc7849c22008-11-16 05:06:27 +00002463 int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
2464 if (Idx < SrcNumElts)
2465 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
2466 else
2467 MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
2468 MaskEltVT));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002469 }
2470 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002471 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002472 Mask.getValueType(),
Mon P Wangaeb06d22008-11-10 04:46:22 +00002473 &MappedOps[0], MappedOps.size());
2474
Dale Johannesen66978ee2009-01-31 02:22:37 +00002475 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002476 VT, Src1, Src2, Mask));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002477 return;
2478 }
2479
Mon P Wangc7849c22008-11-16 05:06:27 +00002480 if (SrcNumElts > MaskNumElts) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002481 // Resulting vector is shorter than the incoming vector.
Mon P Wangc7849c22008-11-16 05:06:27 +00002482 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002483 // Shuffle extracts 1st vector.
Mon P Wang230e4fa2008-11-21 04:25:21 +00002484 setValue(&I, Src1);
Mon P Wangaeb06d22008-11-10 04:46:22 +00002485 return;
2486 }
2487
Mon P Wangc7849c22008-11-16 05:06:27 +00002488 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002489 // Shuffle extracts 2nd vector.
Mon P Wang230e4fa2008-11-21 04:25:21 +00002490 setValue(&I, Src2);
Mon P Wangaeb06d22008-11-10 04:46:22 +00002491 return;
2492 }
2493
Mon P Wangc7849c22008-11-16 05:06:27 +00002494 // Analyze the access pattern of the vector to see if we can extract
2495 // two subvectors and do the shuffle. The analysis is done by calculating
2496 // the range of elements the mask access on both vectors.
2497 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2498 int MaxRange[2] = {-1, -1};
2499
2500 for (int i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002501 SDValue Arg = Mask.getOperand(i);
2502 if (Arg.getOpcode() != ISD::UNDEF) {
2503 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Mon P Wangc7849c22008-11-16 05:06:27 +00002504 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2505 int Input = 0;
2506 if (Idx >= SrcNumElts) {
2507 Input = 1;
2508 Idx -= SrcNumElts;
2509 }
2510 if (Idx > MaxRange[Input])
2511 MaxRange[Input] = Idx;
2512 if (Idx < MinRange[Input])
2513 MinRange[Input] = Idx;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002514 }
2515 }
Mon P Wangaeb06d22008-11-10 04:46:22 +00002516
Mon P Wangc7849c22008-11-16 05:06:27 +00002517 // Check if the access is smaller than the vector size and can we find
2518 // a reasonable extract index.
Mon P Wang230e4fa2008-11-21 04:25:21 +00002519 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
Mon P Wangc7849c22008-11-16 05:06:27 +00002520 int StartIdx[2]; // StartIdx to extract from
2521 for (int Input=0; Input < 2; ++Input) {
2522 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2523 RangeUse[Input] = 0; // Unused
2524 StartIdx[Input] = 0;
2525 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2526 // Fits within range but we should see if we can find a good
Mon P Wang230e4fa2008-11-21 04:25:21 +00002527 // start index that is a multiple of the mask length.
Mon P Wangc7849c22008-11-16 05:06:27 +00002528 if (MaxRange[Input] < MaskNumElts) {
2529 RangeUse[Input] = 1; // Extract from beginning of the vector
2530 StartIdx[Input] = 0;
2531 } else {
2532 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
Mon P Wang6cce3da2008-11-23 04:35:05 +00002533 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002534 StartIdx[Input] + MaskNumElts < SrcNumElts)
Mon P Wangc7849c22008-11-16 05:06:27 +00002535 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
Mon P Wangc7849c22008-11-16 05:06:27 +00002536 }
Mon P Wang230e4fa2008-11-21 04:25:21 +00002537 }
Mon P Wangc7849c22008-11-16 05:06:27 +00002538 }
2539
2540 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002541 setValue(&I, DAG.getNode(ISD::UNDEF,
Dale Johannesen66978ee2009-01-31 02:22:37 +00002542 getCurDebugLoc(), VT)); // Vectors are not used.
Mon P Wangc7849c22008-11-16 05:06:27 +00002543 return;
2544 }
2545 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2546 // Extract appropriate subvector and generate a vector shuffle
2547 for (int Input=0; Input < 2; ++Input) {
Mon P Wang230e4fa2008-11-21 04:25:21 +00002548 SDValue& Src = Input == 0 ? Src1 : Src2;
Mon P Wangc7849c22008-11-16 05:06:27 +00002549 if (RangeUse[Input] == 0) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002550 Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
Mon P Wangc7849c22008-11-16 05:06:27 +00002551 } else {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002552 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002553 Src, DAG.getIntPtrConstant(StartIdx[Input]));
Mon P Wangc7849c22008-11-16 05:06:27 +00002554 }
Mon P Wangaeb06d22008-11-10 04:46:22 +00002555 }
Mon P Wangc7849c22008-11-16 05:06:27 +00002556 // Calculate new mask.
2557 SmallVector<SDValue, 8> MappedOps;
2558 for (int i = 0; i != MaskNumElts; ++i) {
2559 SDValue Arg = Mask.getOperand(i);
2560 if (Arg.getOpcode() == ISD::UNDEF) {
2561 MappedOps.push_back(Arg);
2562 } else {
2563 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2564 if (Idx < SrcNumElts)
2565 MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
2566 else {
2567 Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
2568 MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002569 }
Mon P Wangc7849c22008-11-16 05:06:27 +00002570 }
2571 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002572 Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002573 Mask.getValueType(),
Mon P Wangc7849c22008-11-16 05:06:27 +00002574 &MappedOps[0], MappedOps.size());
Dale Johannesen66978ee2009-01-31 02:22:37 +00002575 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002576 VT, Src1, Src2, Mask));
Mon P Wangc7849c22008-11-16 05:06:27 +00002577 return;
Mon P Wangaeb06d22008-11-10 04:46:22 +00002578 }
2579 }
2580
Mon P Wangc7849c22008-11-16 05:06:27 +00002581 // We can't use either concat vectors or extract subvectors so fall back to
2582 // replacing the shuffle with extract and build vector.
2583 // to insert and build vector.
Mon P Wangaeb06d22008-11-10 04:46:22 +00002584 MVT EltVT = VT.getVectorElementType();
2585 MVT PtrVT = TLI.getPointerTy();
2586 SmallVector<SDValue,8> Ops;
Mon P Wangc7849c22008-11-16 05:06:27 +00002587 for (int i = 0; i != MaskNumElts; ++i) {
Mon P Wangaeb06d22008-11-10 04:46:22 +00002588 SDValue Arg = Mask.getOperand(i);
2589 if (Arg.getOpcode() == ISD::UNDEF) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002590 Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002591 } else {
2592 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
Mon P Wangc7849c22008-11-16 05:06:27 +00002593 int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2594 if (Idx < SrcNumElts)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002595 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002596 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002597 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00002598 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002599 EltVT, Src2,
Mon P Wangc7849c22008-11-16 05:06:27 +00002600 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
Mon P Wangaeb06d22008-11-10 04:46:22 +00002601 }
2602 }
Dale Johannesen66978ee2009-01-31 02:22:37 +00002603 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002604 VT, &Ops[0], Ops.size()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002605}
2606
2607void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2608 const Value *Op0 = I.getOperand(0);
2609 const Value *Op1 = I.getOperand(1);
2610 const Type *AggTy = I.getType();
2611 const Type *ValTy = Op1->getType();
2612 bool IntoUndef = isa<UndefValue>(Op0);
2613 bool FromUndef = isa<UndefValue>(Op1);
2614
2615 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2616 I.idx_begin(), I.idx_end());
2617
2618 SmallVector<MVT, 4> AggValueVTs;
2619 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2620 SmallVector<MVT, 4> ValValueVTs;
2621 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2622
2623 unsigned NumAggValues = AggValueVTs.size();
2624 unsigned NumValValues = ValValueVTs.size();
2625 SmallVector<SDValue, 4> Values(NumAggValues);
2626
2627 SDValue Agg = getValue(Op0);
2628 SDValue Val = getValue(Op1);
2629 unsigned i = 0;
2630 // Copy the beginning value(s) from the original aggregate.
2631 for (; i != LinearIndex; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002632 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002633 AggValueVTs[i]) :
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002634 SDValue(Agg.getNode(), Agg.getResNo() + i);
2635 // Copy values from the inserted value(s).
2636 for (; i != LinearIndex + NumValValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002637 Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002638 AggValueVTs[i]) :
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002639 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2640 // Copy remaining value(s) from the original aggregate.
2641 for (; i != NumAggValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002642 Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002643 AggValueVTs[i]) :
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002644 SDValue(Agg.getNode(), Agg.getResNo() + i);
2645
Dale Johannesen66978ee2009-01-31 02:22:37 +00002646 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002647 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2648 &Values[0], NumAggValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002649}
2650
2651void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2652 const Value *Op0 = I.getOperand(0);
2653 const Type *AggTy = Op0->getType();
2654 const Type *ValTy = I.getType();
2655 bool OutOfUndef = isa<UndefValue>(Op0);
2656
2657 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2658 I.idx_begin(), I.idx_end());
2659
2660 SmallVector<MVT, 4> ValValueVTs;
2661 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2662
2663 unsigned NumValValues = ValValueVTs.size();
2664 SmallVector<SDValue, 4> Values(NumValValues);
2665
2666 SDValue Agg = getValue(Op0);
2667 // Copy out the selected value(s).
2668 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2669 Values[i - LinearIndex] =
Bill Wendlingf0a2d0c2008-11-20 07:24:30 +00002670 OutOfUndef ?
Dale Johannesen66978ee2009-01-31 02:22:37 +00002671 DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
Bill Wendlingf0a2d0c2008-11-20 07:24:30 +00002672 Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2673 SDValue(Agg.getNode(), Agg.getResNo() + i);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002674
Dale Johannesen66978ee2009-01-31 02:22:37 +00002675 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002676 DAG.getVTList(&ValValueVTs[0], NumValValues),
2677 &Values[0], NumValValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002678}
2679
2680
2681void SelectionDAGLowering::visitGetElementPtr(User &I) {
2682 SDValue N = getValue(I.getOperand(0));
2683 const Type *Ty = I.getOperand(0)->getType();
2684
2685 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2686 OI != E; ++OI) {
2687 Value *Idx = *OI;
2688 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2689 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2690 if (Field) {
2691 // N = N + Offset
2692 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002693 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002694 DAG.getIntPtrConstant(Offset));
2695 }
2696 Ty = StTy->getElementType(Field);
2697 } else {
2698 Ty = cast<SequentialType>(Ty)->getElementType();
2699
2700 // If this is a constant subscript, handle it quickly.
2701 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2702 if (CI->getZExtValue() == 0) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002703 uint64_t Offs =
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00002704 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
Dale Johannesen66978ee2009-01-31 02:22:37 +00002705 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002706 DAG.getIntPtrConstant(Offs));
2707 continue;
2708 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002709
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002710 // N = N + Idx * ElementSize;
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00002711 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002712 SDValue IdxN = getValue(Idx);
2713
2714 // If the index is smaller or larger than intptr_t, truncate or extend
2715 // it.
2716 if (IdxN.getValueType().bitsLT(N.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002717 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002718 N.getValueType(), IdxN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002719 else if (IdxN.getValueType().bitsGT(N.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002720 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002721 N.getValueType(), IdxN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002722
2723 // If this is a multiply by a power of two, turn it into a shl
2724 // immediately. This is a very common case.
2725 if (ElementSize != 1) {
2726 if (isPowerOf2_64(ElementSize)) {
2727 unsigned Amt = Log2_64(ElementSize);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002728 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002729 N.getValueType(), IdxN,
Duncan Sands92abc622009-01-31 15:50:11 +00002730 DAG.getConstant(Amt, TLI.getPointerTy()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002731 } else {
2732 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002733 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002734 N.getValueType(), IdxN, Scale);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002735 }
2736 }
2737
Dale Johannesen66978ee2009-01-31 02:22:37 +00002738 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002739 N.getValueType(), N, IdxN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002740 }
2741 }
2742 setValue(&I, N);
2743}
2744
2745void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2746 // If this is a fixed sized alloca in the entry block of the function,
2747 // allocate it statically on the stack.
2748 if (FuncInfo.StaticAllocaMap.count(&I))
2749 return; // getValue will auto-populate this.
2750
2751 const Type *Ty = I.getAllocatedType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00002752 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002753 unsigned Align =
2754 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2755 I.getAlignment());
2756
2757 SDValue AllocSize = getValue(I.getArraySize());
2758 MVT IntPtr = TLI.getPointerTy();
2759 if (IntPtr.bitsLT(AllocSize.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002760 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002761 IntPtr, AllocSize);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002762 else if (IntPtr.bitsGT(AllocSize.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00002763 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002764 IntPtr, AllocSize);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002765
Dale Johannesen66978ee2009-01-31 02:22:37 +00002766 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002767 DAG.getIntPtrConstant(TySize));
2768
2769 // Handle alignment. If the requested alignment is less than or equal to
2770 // the stack alignment, ignore it. If the size is greater than or equal to
2771 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2772 unsigned StackAlign =
2773 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2774 if (Align <= StackAlign)
2775 Align = 0;
2776
2777 // Round the size of the allocation up to the stack alignment size
2778 // by add SA-1 to the size.
Dale Johannesen66978ee2009-01-31 02:22:37 +00002779 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002780 AllocSize.getValueType(), AllocSize,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002781 DAG.getIntPtrConstant(StackAlign-1));
2782 // Mask out the low bits for alignment purposes.
Dale Johannesen66978ee2009-01-31 02:22:37 +00002783 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002784 AllocSize.getValueType(), AllocSize,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002785 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2786
2787 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2788 const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2789 MVT::Other);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002790 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002791 VTs, 2, Ops, 3);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002792 setValue(&I, DSA);
2793 DAG.setRoot(DSA.getValue(1));
2794
2795 // Inform the Frame Information that we have just allocated a variable-sized
2796 // object.
2797 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2798}
2799
2800void SelectionDAGLowering::visitLoad(LoadInst &I) {
2801 const Value *SV = I.getOperand(0);
2802 SDValue Ptr = getValue(SV);
2803
2804 const Type *Ty = I.getType();
2805 bool isVolatile = I.isVolatile();
2806 unsigned Alignment = I.getAlignment();
2807
2808 SmallVector<MVT, 4> ValueVTs;
2809 SmallVector<uint64_t, 4> Offsets;
2810 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2811 unsigned NumValues = ValueVTs.size();
2812 if (NumValues == 0)
2813 return;
2814
2815 SDValue Root;
2816 bool ConstantMemory = false;
2817 if (I.isVolatile())
2818 // Serialize volatile loads with other side effects.
2819 Root = getRoot();
2820 else if (AA->pointsToConstantMemory(SV)) {
2821 // Do not serialize (non-volatile) loads of constant memory with anything.
2822 Root = DAG.getEntryNode();
2823 ConstantMemory = true;
2824 } else {
2825 // Do not serialize non-volatile loads against each other.
2826 Root = DAG.getRoot();
2827 }
2828
2829 SmallVector<SDValue, 4> Values(NumValues);
2830 SmallVector<SDValue, 4> Chains(NumValues);
2831 MVT PtrVT = Ptr.getValueType();
2832 for (unsigned i = 0; i != NumValues; ++i) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002833 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2834 DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002835 PtrVT, Ptr,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002836 DAG.getConstant(Offsets[i], PtrVT)),
2837 SV, Offsets[i],
2838 isVolatile, Alignment);
2839 Values[i] = L;
2840 Chains[i] = L.getValue(1);
2841 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002842
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002843 if (!ConstantMemory) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00002844 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002845 MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002846 &Chains[0], NumValues);
2847 if (isVolatile)
2848 DAG.setRoot(Chain);
2849 else
2850 PendingLoads.push_back(Chain);
2851 }
2852
Dale Johannesen66978ee2009-01-31 02:22:37 +00002853 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
Duncan Sandsaaffa052008-12-01 11:41:29 +00002854 DAG.getVTList(&ValueVTs[0], NumValues),
2855 &Values[0], NumValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002856}
2857
2858
2859void SelectionDAGLowering::visitStore(StoreInst &I) {
2860 Value *SrcV = I.getOperand(0);
2861 Value *PtrV = I.getOperand(1);
2862
2863 SmallVector<MVT, 4> ValueVTs;
2864 SmallVector<uint64_t, 4> Offsets;
2865 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2866 unsigned NumValues = ValueVTs.size();
2867 if (NumValues == 0)
2868 return;
2869
2870 // Get the lowered operands. Note that we do this after
2871 // checking if NumResults is zero, because with zero results
2872 // the operands won't have values in the map.
2873 SDValue Src = getValue(SrcV);
2874 SDValue Ptr = getValue(PtrV);
2875
2876 SDValue Root = getRoot();
2877 SmallVector<SDValue, 4> Chains(NumValues);
2878 MVT PtrVT = Ptr.getValueType();
2879 bool isVolatile = I.isVolatile();
2880 unsigned Alignment = I.getAlignment();
2881 for (unsigned i = 0; i != NumValues; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002882 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002883 SDValue(Src.getNode(), Src.getResNo() + i),
Dale Johannesen66978ee2009-01-31 02:22:37 +00002884 DAG.getNode(ISD::ADD, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002885 PtrVT, Ptr,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002886 DAG.getConstant(Offsets[i], PtrVT)),
2887 PtrV, Offsets[i],
2888 isVolatile, Alignment);
2889
Dale Johannesen66978ee2009-01-31 02:22:37 +00002890 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002891 MVT::Other, &Chains[0], NumValues));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002892}
2893
2894/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2895/// node.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002896void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002897 unsigned Intrinsic) {
2898 bool HasChain = !I.doesNotAccessMemory();
2899 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2900
2901 // Build the operand list.
2902 SmallVector<SDValue, 8> Ops;
2903 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2904 if (OnlyLoad) {
2905 // We don't need to serialize loads against other loads.
2906 Ops.push_back(DAG.getRoot());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002907 } else {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002908 Ops.push_back(getRoot());
2909 }
2910 }
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002911
2912 // Info is set by getTgtMemInstrinsic
2913 TargetLowering::IntrinsicInfo Info;
2914 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2915
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002916 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002917 if (!IsTgtIntrinsic)
2918 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002919
2920 // Add all operands of the call to the operand list.
2921 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2922 SDValue Op = getValue(I.getOperand(i));
2923 assert(TLI.isTypeLegal(Op.getValueType()) &&
2924 "Intrinsic uses a non-legal type?");
2925 Ops.push_back(Op);
2926 }
2927
2928 std::vector<MVT> VTs;
2929 if (I.getType() != Type::VoidTy) {
2930 MVT VT = TLI.getValueType(I.getType());
2931 if (VT.isVector()) {
2932 const VectorType *DestTy = cast<VectorType>(I.getType());
2933 MVT EltVT = TLI.getValueType(DestTy->getElementType());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002934
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002935 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2936 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2937 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002938
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002939 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2940 VTs.push_back(VT);
2941 }
2942 if (HasChain)
2943 VTs.push_back(MVT::Other);
2944
2945 const MVT *VTList = DAG.getNodeValueTypes(VTs);
2946
2947 // Create the node.
2948 SDValue Result;
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002949 if (IsTgtIntrinsic) {
2950 // This is target intrinsic that touches memory
Dale Johannesen66978ee2009-01-31 02:22:37 +00002951 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002952 VTList, VTs.size(),
Mon P Wang3efcd4a2008-11-01 20:24:53 +00002953 &Ops[0], Ops.size(),
2954 Info.memVT, Info.ptrVal, Info.offset,
2955 Info.align, Info.vol,
2956 Info.readMem, Info.writeMem);
2957 }
2958 else if (!HasChain)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002959 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002960 VTList, VTs.size(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002961 &Ops[0], Ops.size());
2962 else if (I.getType() != Type::VoidTy)
Dale Johannesen66978ee2009-01-31 02:22:37 +00002963 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002964 VTList, VTs.size(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002965 &Ops[0], Ops.size());
2966 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00002967 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00002968 VTList, VTs.size(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002969 &Ops[0], Ops.size());
2970
2971 if (HasChain) {
2972 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2973 if (OnlyLoad)
2974 PendingLoads.push_back(Chain);
2975 else
2976 DAG.setRoot(Chain);
2977 }
2978 if (I.getType() != Type::VoidTy) {
2979 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2980 MVT VT = TLI.getValueType(PTy);
Dale Johannesen66978ee2009-01-31 02:22:37 +00002981 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00002982 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00002983 setValue(&I, Result);
2984 }
2985}
2986
2987/// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2988static GlobalVariable *ExtractTypeInfo(Value *V) {
2989 V = V->stripPointerCasts();
2990 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2991 assert ((GV || isa<ConstantPointerNull>(V)) &&
2992 "TypeInfo must be a global variable or NULL");
2993 return GV;
2994}
2995
2996namespace llvm {
2997
2998/// AddCatchInfo - Extract the personality and type infos from an eh.selector
2999/// call, and add them to the specified machine basic block.
3000void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3001 MachineBasicBlock *MBB) {
3002 // Inform the MachineModuleInfo of the personality for this landing pad.
3003 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3004 assert(CE->getOpcode() == Instruction::BitCast &&
3005 isa<Function>(CE->getOperand(0)) &&
3006 "Personality should be a function");
3007 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3008
3009 // Gather all the type infos for this landing pad and pass them along to
3010 // MachineModuleInfo.
3011 std::vector<GlobalVariable *> TyInfo;
3012 unsigned N = I.getNumOperands();
3013
3014 for (unsigned i = N - 1; i > 2; --i) {
3015 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3016 unsigned FilterLength = CI->getZExtValue();
3017 unsigned FirstCatch = i + FilterLength + !FilterLength;
3018 assert (FirstCatch <= N && "Invalid filter length");
3019
3020 if (FirstCatch < N) {
3021 TyInfo.reserve(N - FirstCatch);
3022 for (unsigned j = FirstCatch; j < N; ++j)
3023 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3024 MMI->addCatchTypeInfo(MBB, TyInfo);
3025 TyInfo.clear();
3026 }
3027
3028 if (!FilterLength) {
3029 // Cleanup.
3030 MMI->addCleanup(MBB);
3031 } else {
3032 // Filter.
3033 TyInfo.reserve(FilterLength - 1);
3034 for (unsigned j = i + 1; j < FirstCatch; ++j)
3035 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3036 MMI->addFilterTypeInfo(MBB, TyInfo);
3037 TyInfo.clear();
3038 }
3039
3040 N = i;
3041 }
3042 }
3043
3044 if (N > 3) {
3045 TyInfo.reserve(N - 3);
3046 for (unsigned j = 3; j < N; ++j)
3047 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3048 MMI->addCatchTypeInfo(MBB, TyInfo);
3049 }
3050}
3051
3052}
3053
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003054/// GetSignificand - Get the significand and build it into a floating-point
3055/// number with exponent of 1:
3056///
3057/// Op = (Op & 0x007fffff) | 0x3f800000;
3058///
3059/// where Op is the hexidecimal representation of floating point value.
Bill Wendling39150252008-09-09 20:39:27 +00003060static SDValue
Dale Johannesen66978ee2009-01-31 02:22:37 +00003061GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3062 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003063 DAG.getConstant(0x007fffff, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003064 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003065 DAG.getConstant(0x3f800000, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003066 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
Bill Wendling39150252008-09-09 20:39:27 +00003067}
3068
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003069/// GetExponent - Get the exponent:
3070///
Bill Wendlinge9a72862009-01-20 21:17:57 +00003071/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003072///
3073/// where Op is the hexidecimal representation of floating point value.
Bill Wendling39150252008-09-09 20:39:27 +00003074static SDValue
Dale Johannesen66978ee2009-01-31 02:22:37 +00003075GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3076 DebugLoc dl) {
3077 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003078 DAG.getConstant(0x7f800000, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003079 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
Duncan Sands92abc622009-01-31 15:50:11 +00003080 DAG.getConstant(23, TLI.getPointerTy()));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003081 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
Bill Wendlinge9a72862009-01-20 21:17:57 +00003082 DAG.getConstant(127, MVT::i32));
Dale Johannesen66978ee2009-01-31 02:22:37 +00003083 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
Bill Wendling39150252008-09-09 20:39:27 +00003084}
3085
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003086/// getF32Constant - Get 32-bit floating point constant.
3087static SDValue
3088getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3089 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3090}
3091
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003092/// Inlined utility function to implement binary input atomic intrinsics for
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003093/// visitIntrinsicCall: I is a call instruction
3094/// Op is the associated NodeType for I
3095const char *
3096SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003097 SDValue Root = getRoot();
Dan Gohman0b1d4a72008-12-23 21:37:04 +00003098 SDValue L =
Dale Johannesen66978ee2009-01-31 02:22:37 +00003099 DAG.getAtomic(Op, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003100 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00003101 Root,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003102 getValue(I.getOperand(1)),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00003103 getValue(I.getOperand(2)),
3104 I.getOperand(1));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003105 setValue(&I, L);
3106 DAG.setRoot(L.getValue(1));
3107 return 0;
3108}
3109
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003110// implVisitAluOverflow - Lower arithmetic overflow instrinsics.
Bill Wendling74c37652008-12-09 22:08:41 +00003111const char *
3112SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003113 SDValue Op1 = getValue(I.getOperand(1));
3114 SDValue Op2 = getValue(I.getOperand(2));
Bill Wendling74c37652008-12-09 22:08:41 +00003115
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003116 MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 };
3117 SDValue Ops[] = { Op1, Op2 };
Bill Wendling74c37652008-12-09 22:08:41 +00003118
Dale Johannesen66978ee2009-01-31 02:22:37 +00003119 SDValue Result = DAG.getNode(Op, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003120 DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
Bill Wendling74c37652008-12-09 22:08:41 +00003121
Bill Wendling2ce4e5c2008-12-10 00:28:22 +00003122 setValue(&I, Result);
3123 return 0;
3124}
Bill Wendling74c37652008-12-09 22:08:41 +00003125
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003126/// visitExp - Lower an exp intrinsic. Handles the special sequences for
3127/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003128void
3129SelectionDAGLowering::visitExp(CallInst &I) {
3130 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003131 DebugLoc dl = getCurDebugLoc();
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003132
3133 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3134 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3135 SDValue Op = getValue(I.getOperand(1));
3136
3137 // Put the exponent in the right bit position for later addition to the
3138 // final result:
3139 //
3140 // #define LOG2OFe 1.4426950f
3141 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003142 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003143 getF32Constant(DAG, 0x3fb8aa3b));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003144 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003145
3146 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003147 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3148 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003149
3150 // IntegerPartOfX <<= 23;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003151 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
Duncan Sands92abc622009-01-31 15:50:11 +00003152 DAG.getConstant(23, TLI.getPointerTy()));
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003153
3154 if (LimitFloatPrecision <= 6) {
3155 // For floating-point precision of 6:
3156 //
3157 // TwoToFractionalPartOfX =
3158 // 0.997535578f +
3159 // (0.735607626f + 0.252464424f * x) * x;
3160 //
3161 // error 0.0144103317, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003162 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003163 getF32Constant(DAG, 0x3e814304));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003164 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003165 getF32Constant(DAG, 0x3f3c50c8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003166 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3167 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003168 getF32Constant(DAG, 0x3f7f5e7e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003169 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003170
3171 // Add the exponent into the result in integer domain.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003172 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003173 TwoToFracPartOfX, IntegerPartOfX);
3174
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003175 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003176 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3177 // For floating-point precision of 12:
3178 //
3179 // TwoToFractionalPartOfX =
3180 // 0.999892986f +
3181 // (0.696457318f +
3182 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3183 //
3184 // 0.000107046256 error, which is 13 to 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003185 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003186 getF32Constant(DAG, 0x3da235e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003187 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003188 getF32Constant(DAG, 0x3e65b8f3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003189 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3190 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003191 getF32Constant(DAG, 0x3f324b07));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003192 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3193 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003194 getF32Constant(DAG, 0x3f7ff8fd));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003195 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003196
3197 // Add the exponent into the result in integer domain.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003198 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003199 TwoToFracPartOfX, IntegerPartOfX);
3200
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003201 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003202 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3203 // For floating-point precision of 18:
3204 //
3205 // TwoToFractionalPartOfX =
3206 // 0.999999982f +
3207 // (0.693148872f +
3208 // (0.240227044f +
3209 // (0.554906021e-1f +
3210 // (0.961591928e-2f +
3211 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3212 //
3213 // error 2.47208000*10^(-7), which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003214 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003215 getF32Constant(DAG, 0x3924b03e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003216 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003217 getF32Constant(DAG, 0x3ab24b87));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003218 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3219 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003220 getF32Constant(DAG, 0x3c1d8c17));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003221 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3222 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003223 getF32Constant(DAG, 0x3d634a1d));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003224 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3225 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003226 getF32Constant(DAG, 0x3e75fe14));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003227 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3228 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003229 getF32Constant(DAG, 0x3f317234));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003230 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3231 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003232 getF32Constant(DAG, 0x3f800000));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003233 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3234 MVT::i32, t13);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003235
3236 // Add the exponent into the result in integer domain.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003237 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003238 TwoToFracPartOfX, IntegerPartOfX);
3239
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003240 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003241 }
3242 } else {
3243 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003244 result = DAG.getNode(ISD::FEXP, dl,
Bill Wendlingb4ec2832008-09-09 22:13:54 +00003245 getValue(I.getOperand(1)).getValueType(),
3246 getValue(I.getOperand(1)));
3247 }
3248
Dale Johannesen59e577f2008-09-05 18:38:42 +00003249 setValue(&I, result);
3250}
3251
Bill Wendling39150252008-09-09 20:39:27 +00003252/// visitLog - Lower a log intrinsic. Handles the special sequences for
3253/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003254void
3255SelectionDAGLowering::visitLog(CallInst &I) {
3256 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003257 DebugLoc dl = getCurDebugLoc();
Bill Wendling39150252008-09-09 20:39:27 +00003258
3259 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3260 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3261 SDValue Op = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003262 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Bill Wendling39150252008-09-09 20:39:27 +00003263
3264 // Scale the exponent by log(2) [0.69314718f].
Dale Johannesen66978ee2009-01-31 02:22:37 +00003265 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003266 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003267 getF32Constant(DAG, 0x3f317218));
Bill Wendling39150252008-09-09 20:39:27 +00003268
3269 // Get the significand and build it into a floating-point number with
3270 // exponent of 1.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003271 SDValue X = GetSignificand(DAG, Op1, dl);
Bill Wendling39150252008-09-09 20:39:27 +00003272
3273 if (LimitFloatPrecision <= 6) {
3274 // For floating-point precision of 6:
3275 //
3276 // LogofMantissa =
3277 // -1.1609546f +
3278 // (1.4034025f - 0.23903021f * x) * x;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003279 //
Bill Wendling39150252008-09-09 20:39:27 +00003280 // error 0.0034276066, which is better than 8 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003281 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003282 getF32Constant(DAG, 0xbe74c456));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003283 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003284 getF32Constant(DAG, 0x3fb3a2b1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003285 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3286 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003287 getF32Constant(DAG, 0x3f949a29));
Bill Wendling39150252008-09-09 20:39:27 +00003288
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003289 result = DAG.getNode(ISD::FADD, dl,
3290 MVT::f32, LogOfExponent, LogOfMantissa);
Bill Wendling39150252008-09-09 20:39:27 +00003291 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3292 // For floating-point precision of 12:
3293 //
3294 // LogOfMantissa =
3295 // -1.7417939f +
3296 // (2.8212026f +
3297 // (-1.4699568f +
3298 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3299 //
3300 // error 0.000061011436, which is 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003301 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003302 getF32Constant(DAG, 0xbd67b6d6));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003303 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003304 getF32Constant(DAG, 0x3ee4f4b8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003305 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3306 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003307 getF32Constant(DAG, 0x3fbc278b));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003308 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3309 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003310 getF32Constant(DAG, 0x40348e95));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003311 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3312 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003313 getF32Constant(DAG, 0x3fdef31a));
Bill Wendling39150252008-09-09 20:39:27 +00003314
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003315 result = DAG.getNode(ISD::FADD, dl,
3316 MVT::f32, LogOfExponent, LogOfMantissa);
Bill Wendling39150252008-09-09 20:39:27 +00003317 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3318 // For floating-point precision of 18:
3319 //
3320 // LogOfMantissa =
3321 // -2.1072184f +
3322 // (4.2372794f +
3323 // (-3.7029485f +
3324 // (2.2781945f +
3325 // (-0.87823314f +
3326 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3327 //
3328 // error 0.0000023660568, which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003330 getF32Constant(DAG, 0xbc91e5ac));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003331 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003332 getF32Constant(DAG, 0x3e4350aa));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3334 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003335 getF32Constant(DAG, 0x3f60d3e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3337 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003338 getF32Constant(DAG, 0x4011cdf0));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003339 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3340 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003341 getF32Constant(DAG, 0x406cfd1c));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003342 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3343 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003344 getF32Constant(DAG, 0x408797cb));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003345 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3346 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003347 getF32Constant(DAG, 0x4006dcab));
Bill Wendling39150252008-09-09 20:39:27 +00003348
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003349 result = DAG.getNode(ISD::FADD, dl,
3350 MVT::f32, LogOfExponent, LogOfMantissa);
Bill Wendling39150252008-09-09 20:39:27 +00003351 }
3352 } else {
3353 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003354 result = DAG.getNode(ISD::FLOG, dl,
Bill Wendling39150252008-09-09 20:39:27 +00003355 getValue(I.getOperand(1)).getValueType(),
3356 getValue(I.getOperand(1)));
3357 }
3358
Dale Johannesen59e577f2008-09-05 18:38:42 +00003359 setValue(&I, result);
3360}
3361
Bill Wendling3eb59402008-09-09 00:28:24 +00003362/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3363/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003364void
3365SelectionDAGLowering::visitLog2(CallInst &I) {
3366 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003367 DebugLoc dl = getCurDebugLoc();
Bill Wendling3eb59402008-09-09 00:28:24 +00003368
Dale Johannesen853244f2008-09-05 23:49:37 +00003369 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
Bill Wendling3eb59402008-09-09 00:28:24 +00003370 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3371 SDValue Op = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003372 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Bill Wendling3eb59402008-09-09 00:28:24 +00003373
Bill Wendling39150252008-09-09 20:39:27 +00003374 // Get the exponent.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003375 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
Bill Wendling3eb59402008-09-09 00:28:24 +00003376
3377 // Get the significand and build it into a floating-point number with
Bill Wendling39150252008-09-09 20:39:27 +00003378 // exponent of 1.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003379 SDValue X = GetSignificand(DAG, Op1, dl);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003380
Bill Wendling3eb59402008-09-09 00:28:24 +00003381 // Different possible minimax approximations of significand in
3382 // floating-point for various degrees of accuracy over [1,2].
3383 if (LimitFloatPrecision <= 6) {
3384 // For floating-point precision of 6:
3385 //
3386 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3387 //
3388 // error 0.0049451742, which is more than 7 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003389 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003390 getF32Constant(DAG, 0xbeb08fe0));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003391 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003392 getF32Constant(DAG, 0x40019463));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003393 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3394 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003395 getF32Constant(DAG, 0x3fd6633d));
Bill Wendling3eb59402008-09-09 00:28:24 +00003396
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003397 result = DAG.getNode(ISD::FADD, dl,
3398 MVT::f32, LogOfExponent, Log2ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003399 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3400 // For floating-point precision of 12:
3401 //
3402 // Log2ofMantissa =
3403 // -2.51285454f +
3404 // (4.07009056f +
3405 // (-2.12067489f +
3406 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003407 //
Bill Wendling3eb59402008-09-09 00:28:24 +00003408 // error 0.0000876136000, which is better than 13 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003409 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003410 getF32Constant(DAG, 0xbda7262e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003411 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003412 getF32Constant(DAG, 0x3f25280b));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003413 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3414 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003415 getF32Constant(DAG, 0x4007b923));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003416 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3417 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003418 getF32Constant(DAG, 0x40823e2f));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003419 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3420 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003421 getF32Constant(DAG, 0x4020d29c));
Bill Wendling3eb59402008-09-09 00:28:24 +00003422
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003423 result = DAG.getNode(ISD::FADD, dl,
3424 MVT::f32, LogOfExponent, Log2ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003425 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3426 // For floating-point precision of 18:
3427 //
3428 // Log2ofMantissa =
3429 // -3.0400495f +
3430 // (6.1129976f +
3431 // (-5.3420409f +
3432 // (3.2865683f +
3433 // (-1.2669343f +
3434 // (0.27515199f -
3435 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3436 //
3437 // error 0.0000018516, which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003438 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003439 getF32Constant(DAG, 0xbcd2769e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003440 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003441 getF32Constant(DAG, 0x3e8ce0b9));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003442 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3443 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003444 getF32Constant(DAG, 0x3fa22ae7));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003445 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3446 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003447 getF32Constant(DAG, 0x40525723));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003448 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3449 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003450 getF32Constant(DAG, 0x40aaf200));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003451 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3452 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003453 getF32Constant(DAG, 0x40c39dad));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003454 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3455 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003456 getF32Constant(DAG, 0x4042902c));
Bill Wendling3eb59402008-09-09 00:28:24 +00003457
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003458 result = DAG.getNode(ISD::FADD, dl,
3459 MVT::f32, LogOfExponent, Log2ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003460 }
Dale Johannesen853244f2008-09-05 23:49:37 +00003461 } else {
Bill Wendling3eb59402008-09-09 00:28:24 +00003462 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003463 result = DAG.getNode(ISD::FLOG2, dl,
Dale Johannesen853244f2008-09-05 23:49:37 +00003464 getValue(I.getOperand(1)).getValueType(),
3465 getValue(I.getOperand(1)));
3466 }
Bill Wendling3eb59402008-09-09 00:28:24 +00003467
Dale Johannesen59e577f2008-09-05 18:38:42 +00003468 setValue(&I, result);
3469}
3470
Bill Wendling3eb59402008-09-09 00:28:24 +00003471/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3472/// limited-precision mode.
Dale Johannesen59e577f2008-09-05 18:38:42 +00003473void
3474SelectionDAGLowering::visitLog10(CallInst &I) {
3475 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003476 DebugLoc dl = getCurDebugLoc();
Bill Wendling181b6272008-10-19 20:34:04 +00003477
Dale Johannesen852680a2008-09-05 21:27:19 +00003478 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
Bill Wendling3eb59402008-09-09 00:28:24 +00003479 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3480 SDValue Op = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003481 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Bill Wendling3eb59402008-09-09 00:28:24 +00003482
Bill Wendling39150252008-09-09 20:39:27 +00003483 // Scale the exponent by log10(2) [0.30102999f].
Dale Johannesen66978ee2009-01-31 02:22:37 +00003484 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003485 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003486 getF32Constant(DAG, 0x3e9a209a));
Bill Wendling3eb59402008-09-09 00:28:24 +00003487
3488 // Get the significand and build it into a floating-point number with
Bill Wendling39150252008-09-09 20:39:27 +00003489 // exponent of 1.
Dale Johannesen66978ee2009-01-31 02:22:37 +00003490 SDValue X = GetSignificand(DAG, Op1, dl);
Bill Wendling3eb59402008-09-09 00:28:24 +00003491
3492 if (LimitFloatPrecision <= 6) {
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003493 // For floating-point precision of 6:
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003494 //
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003495 // Log10ofMantissa =
3496 // -0.50419619f +
3497 // (0.60948995f - 0.10380950f * x) * x;
3498 //
3499 // error 0.0014886165, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003500 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003501 getF32Constant(DAG, 0xbdd49a13));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003502 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003503 getF32Constant(DAG, 0x3f1c0789));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003504 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3505 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003506 getF32Constant(DAG, 0x3f011300));
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003507
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003508 result = DAG.getNode(ISD::FADD, dl,
3509 MVT::f32, LogOfExponent, Log10ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003510 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3511 // For floating-point precision of 12:
3512 //
3513 // Log10ofMantissa =
3514 // -0.64831180f +
3515 // (0.91751397f +
3516 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3517 //
3518 // error 0.00019228036, which is better than 12 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003519 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003520 getF32Constant(DAG, 0x3d431f31));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003521 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003522 getF32Constant(DAG, 0x3ea21fb2));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003523 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3524 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003525 getF32Constant(DAG, 0x3f6ae232));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003526 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3527 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003528 getF32Constant(DAG, 0x3f25f7c3));
Bill Wendling3eb59402008-09-09 00:28:24 +00003529
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003530 result = DAG.getNode(ISD::FADD, dl,
3531 MVT::f32, LogOfExponent, Log10ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003532 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003533 // For floating-point precision of 18:
3534 //
3535 // Log10ofMantissa =
3536 // -0.84299375f +
3537 // (1.5327582f +
3538 // (-1.0688956f +
3539 // (0.49102474f +
3540 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3541 //
3542 // error 0.0000037995730, which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003543 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003544 getF32Constant(DAG, 0x3c5d51ce));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003545 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003546 getF32Constant(DAG, 0x3e00685a));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003547 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3548 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003549 getF32Constant(DAG, 0x3efb6798));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003550 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3551 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003552 getF32Constant(DAG, 0x3f88d192));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003553 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3554 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003555 getF32Constant(DAG, 0x3fc4316c));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003556 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3557 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003558 getF32Constant(DAG, 0x3f57ce70));
Bill Wendlingbd297bc2008-09-09 18:42:23 +00003559
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003560 result = DAG.getNode(ISD::FADD, dl,
3561 MVT::f32, LogOfExponent, Log10ofMantissa);
Bill Wendling3eb59402008-09-09 00:28:24 +00003562 }
Dale Johannesen852680a2008-09-05 21:27:19 +00003563 } else {
Bill Wendling3eb59402008-09-09 00:28:24 +00003564 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003565 result = DAG.getNode(ISD::FLOG10, dl,
Dale Johannesen852680a2008-09-05 21:27:19 +00003566 getValue(I.getOperand(1)).getValueType(),
3567 getValue(I.getOperand(1)));
3568 }
Bill Wendling3eb59402008-09-09 00:28:24 +00003569
Dale Johannesen59e577f2008-09-05 18:38:42 +00003570 setValue(&I, result);
3571}
3572
Bill Wendlinge10c8142008-09-09 22:39:21 +00003573/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3574/// limited-precision mode.
Dale Johannesen601d3c02008-09-05 01:48:15 +00003575void
3576SelectionDAGLowering::visitExp2(CallInst &I) {
3577 SDValue result;
Dale Johannesen66978ee2009-01-31 02:22:37 +00003578 DebugLoc dl = getCurDebugLoc();
Bill Wendlinge10c8142008-09-09 22:39:21 +00003579
Dale Johannesen601d3c02008-09-05 01:48:15 +00003580 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
Bill Wendlinge10c8142008-09-09 22:39:21 +00003581 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3582 SDValue Op = getValue(I.getOperand(1));
3583
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003584 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003585
3586 // FractionalPartOfX = x - (float)IntegerPartOfX;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003587 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3588 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003589
3590 // IntegerPartOfX <<= 23;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003591 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
Duncan Sands92abc622009-01-31 15:50:11 +00003592 DAG.getConstant(23, TLI.getPointerTy()));
Bill Wendlinge10c8142008-09-09 22:39:21 +00003593
3594 if (LimitFloatPrecision <= 6) {
3595 // For floating-point precision of 6:
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003596 //
Bill Wendlinge10c8142008-09-09 22:39:21 +00003597 // TwoToFractionalPartOfX =
3598 // 0.997535578f +
3599 // (0.735607626f + 0.252464424f * x) * x;
3600 //
3601 // error 0.0144103317, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003602 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003603 getF32Constant(DAG, 0x3e814304));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003604 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003605 getF32Constant(DAG, 0x3f3c50c8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003606 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3607 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003608 getF32Constant(DAG, 0x3f7f5e7e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003609 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003610 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003611 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003612
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003613 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3614 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003615 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3616 // For floating-point precision of 12:
3617 //
3618 // TwoToFractionalPartOfX =
3619 // 0.999892986f +
3620 // (0.696457318f +
3621 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3622 //
3623 // error 0.000107046256, which is 13 to 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003624 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003625 getF32Constant(DAG, 0x3da235e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003626 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003627 getF32Constant(DAG, 0x3e65b8f3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003628 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3629 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003630 getF32Constant(DAG, 0x3f324b07));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003631 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3632 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003633 getF32Constant(DAG, 0x3f7ff8fd));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003634 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003635 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003636 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003637
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003638 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3639 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003640 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3641 // For floating-point precision of 18:
3642 //
3643 // TwoToFractionalPartOfX =
3644 // 0.999999982f +
3645 // (0.693148872f +
3646 // (0.240227044f +
3647 // (0.554906021e-1f +
3648 // (0.961591928e-2f +
3649 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3650 // error 2.47208000*10^(-7), which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003651 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003652 getF32Constant(DAG, 0x3924b03e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003653 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003654 getF32Constant(DAG, 0x3ab24b87));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003655 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3656 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003657 getF32Constant(DAG, 0x3c1d8c17));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003658 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3659 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003660 getF32Constant(DAG, 0x3d634a1d));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003661 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3662 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003663 getF32Constant(DAG, 0x3e75fe14));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003664 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3665 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003666 getF32Constant(DAG, 0x3f317234));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003667 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3668 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003669 getF32Constant(DAG, 0x3f800000));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003670 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003671 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003672 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003673
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003674 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3675 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlinge10c8142008-09-09 22:39:21 +00003676 }
Dale Johannesen601d3c02008-09-05 01:48:15 +00003677 } else {
Bill Wendling3eb59402008-09-09 00:28:24 +00003678 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003679 result = DAG.getNode(ISD::FEXP2, dl,
Dale Johannesen601d3c02008-09-05 01:48:15 +00003680 getValue(I.getOperand(1)).getValueType(),
3681 getValue(I.getOperand(1)));
3682 }
Bill Wendlinge10c8142008-09-09 22:39:21 +00003683
Dale Johannesen601d3c02008-09-05 01:48:15 +00003684 setValue(&I, result);
3685}
3686
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003687/// visitPow - Lower a pow intrinsic. Handles the special sequences for
3688/// limited-precision mode with x == 10.0f.
3689void
3690SelectionDAGLowering::visitPow(CallInst &I) {
3691 SDValue result;
3692 Value *Val = I.getOperand(1);
Dale Johannesen66978ee2009-01-31 02:22:37 +00003693 DebugLoc dl = getCurDebugLoc();
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003694 bool IsExp10 = false;
3695
3696 if (getValue(Val).getValueType() == MVT::f32 &&
Bill Wendling277fc242008-09-10 00:24:59 +00003697 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003698 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3699 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3700 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3701 APFloat Ten(10.0f);
3702 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3703 }
3704 }
3705 }
3706
3707 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3708 SDValue Op = getValue(I.getOperand(2));
3709
3710 // Put the exponent in the right bit position for later addition to the
3711 // final result:
3712 //
3713 // #define LOG2OF10 3.3219281f
3714 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003715 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003716 getF32Constant(DAG, 0x40549a78));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003717 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003718
3719 // FractionalPartOfX = x - (float)IntegerPartOfX;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003720 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3721 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003722
3723 // IntegerPartOfX <<= 23;
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003724 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
Duncan Sands92abc622009-01-31 15:50:11 +00003725 DAG.getConstant(23, TLI.getPointerTy()));
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003726
3727 if (LimitFloatPrecision <= 6) {
3728 // For floating-point precision of 6:
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003729 //
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003730 // twoToFractionalPartOfX =
3731 // 0.997535578f +
3732 // (0.735607626f + 0.252464424f * x) * x;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003733 //
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003734 // error 0.0144103317, which is 6 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003735 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003736 getF32Constant(DAG, 0x3e814304));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003737 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003738 getF32Constant(DAG, 0x3f3c50c8));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003739 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3740 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003741 getF32Constant(DAG, 0x3f7f5e7e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003742 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003743 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003744 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003745
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003746 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3747 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003748 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3749 // For floating-point precision of 12:
3750 //
3751 // TwoToFractionalPartOfX =
3752 // 0.999892986f +
3753 // (0.696457318f +
3754 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3755 //
3756 // error 0.000107046256, which is 13 to 14 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003757 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003758 getF32Constant(DAG, 0x3da235e3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003759 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003760 getF32Constant(DAG, 0x3e65b8f3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003761 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3762 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003763 getF32Constant(DAG, 0x3f324b07));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003764 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3765 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003766 getF32Constant(DAG, 0x3f7ff8fd));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003767 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003768 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003769 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003770
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003771 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3772 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003773 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3774 // For floating-point precision of 18:
3775 //
3776 // TwoToFractionalPartOfX =
3777 // 0.999999982f +
3778 // (0.693148872f +
3779 // (0.240227044f +
3780 // (0.554906021e-1f +
3781 // (0.961591928e-2f +
3782 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3783 // error 2.47208000*10^(-7), which is better than 18 bits
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003784 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003785 getF32Constant(DAG, 0x3924b03e));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003786 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003787 getF32Constant(DAG, 0x3ab24b87));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003788 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3789 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003790 getF32Constant(DAG, 0x3c1d8c17));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003791 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3792 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003793 getF32Constant(DAG, 0x3d634a1d));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003794 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3795 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003796 getF32Constant(DAG, 0x3e75fe14));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003797 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3798 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003799 getF32Constant(DAG, 0x3f317234));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003800 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3801 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
Bill Wendlingcd4c73a2008-09-22 00:44:35 +00003802 getF32Constant(DAG, 0x3f800000));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003803 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003804 SDValue TwoToFractionalPartOfX =
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003805 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003806
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003807 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3808 MVT::f32, TwoToFractionalPartOfX);
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003809 }
3810 } else {
3811 // No special expansion.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003812 result = DAG.getNode(ISD::FPOW, dl,
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00003813 getValue(I.getOperand(1)).getValueType(),
3814 getValue(I.getOperand(1)),
3815 getValue(I.getOperand(2)));
3816 }
3817
3818 setValue(&I, result);
3819}
3820
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003821/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3822/// we want to emit this as a call to a named external function, return the name
3823/// otherwise lower it and return null.
3824const char *
3825SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00003826 DebugLoc dl = getCurDebugLoc();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003827 switch (Intrinsic) {
3828 default:
3829 // By default, turn this into a target intrinsic node.
3830 visitTargetIntrinsic(I, Intrinsic);
3831 return 0;
3832 case Intrinsic::vastart: visitVAStart(I); return 0;
3833 case Intrinsic::vaend: visitVAEnd(I); return 0;
3834 case Intrinsic::vacopy: visitVACopy(I); return 0;
3835 case Intrinsic::returnaddress:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003836 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003837 getValue(I.getOperand(1))));
3838 return 0;
Bill Wendlingd5d81912008-09-26 22:10:44 +00003839 case Intrinsic::frameaddress:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003840 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003841 getValue(I.getOperand(1))));
3842 return 0;
3843 case Intrinsic::setjmp:
3844 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3845 break;
3846 case Intrinsic::longjmp:
3847 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3848 break;
Chris Lattner824b9582008-11-21 16:42:48 +00003849 case Intrinsic::memcpy: {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003850 SDValue Op1 = getValue(I.getOperand(1));
3851 SDValue Op2 = getValue(I.getOperand(2));
3852 SDValue Op3 = getValue(I.getOperand(3));
3853 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
Dale Johannesena04b7572009-02-03 23:04:43 +00003854 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003855 I.getOperand(1), 0, I.getOperand(2), 0));
3856 return 0;
3857 }
Chris Lattner824b9582008-11-21 16:42:48 +00003858 case Intrinsic::memset: {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003859 SDValue Op1 = getValue(I.getOperand(1));
3860 SDValue Op2 = getValue(I.getOperand(2));
3861 SDValue Op3 = getValue(I.getOperand(3));
3862 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
Dale Johannesena04b7572009-02-03 23:04:43 +00003863 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003864 I.getOperand(1), 0));
3865 return 0;
3866 }
Chris Lattner824b9582008-11-21 16:42:48 +00003867 case Intrinsic::memmove: {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003868 SDValue Op1 = getValue(I.getOperand(1));
3869 SDValue Op2 = getValue(I.getOperand(2));
3870 SDValue Op3 = getValue(I.getOperand(3));
3871 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3872
3873 // If the source and destination are known to not be aliases, we can
3874 // lower memmove as memcpy.
3875 uint64_t Size = -1ULL;
3876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00003877 Size = C->getZExtValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003878 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3879 AliasAnalysis::NoAlias) {
Dale Johannesena04b7572009-02-03 23:04:43 +00003880 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003881 I.getOperand(1), 0, I.getOperand(2), 0));
3882 return 0;
3883 }
3884
Dale Johannesena04b7572009-02-03 23:04:43 +00003885 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003886 I.getOperand(1), 0, I.getOperand(2), 0));
3887 return 0;
3888 }
3889 case Intrinsic::dbg_stoppoint: {
Devang Patel83489bb2009-01-13 00:35:13 +00003890 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003891 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003892 if (DW && DW->ValidDebugInfo(SPI.getContext())) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003893 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3894 SPI.getLine(),
3895 SPI.getColumn(),
Devang Patel83489bb2009-01-13 00:35:13 +00003896 SPI.getContext()));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003897 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3898 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename());
3899 unsigned idx = DAG.getMachineFunction().
3900 getOrCreateDebugLocID(SrcFile,
3901 SPI.getLine(),
3902 SPI.getColumn());
Dale Johannesen66978ee2009-01-31 02:22:37 +00003903 setCurDebugLoc(DebugLoc::get(idx));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003904 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003905 return 0;
3906 }
3907 case Intrinsic::dbg_region_start: {
Devang Patel83489bb2009-01-13 00:35:13 +00003908 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003909 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
Devang Patelb79b5352009-01-19 23:21:49 +00003910 if (DW && DW->ValidDebugInfo(RSI.getContext())) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003911 unsigned LabelID =
Devang Patel83489bb2009-01-13 00:35:13 +00003912 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
Dale Johannesen8ad9b432009-02-04 01:17:06 +00003913 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3914 getRoot(), LabelID));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003915 }
3916
3917 return 0;
3918 }
3919 case Intrinsic::dbg_region_end: {
Devang Patel83489bb2009-01-13 00:35:13 +00003920 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003921 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
Devang Patelb79b5352009-01-19 23:21:49 +00003922 if (DW && DW->ValidDebugInfo(REI.getContext())) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003923 unsigned LabelID =
Devang Patel83489bb2009-01-13 00:35:13 +00003924 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
Dale Johannesen8ad9b432009-02-04 01:17:06 +00003925 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3926 getRoot(), LabelID));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003927 }
3928
3929 return 0;
3930 }
3931 case Intrinsic::dbg_func_start: {
Devang Patel83489bb2009-01-13 00:35:13 +00003932 DwarfWriter *DW = DAG.getDwarfWriter();
3933 if (!DW) return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003934 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3935 Value *SP = FSI.getSubprogram();
Devang Patelcf3a4482009-01-15 23:41:32 +00003936 if (SP && DW->ValidDebugInfo(SP)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003937 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
3938 // what (most?) gdb expects.
Devang Patel83489bb2009-01-13 00:35:13 +00003939 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3940 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3941 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
3942 CompileUnit.getFilename());
Bill Wendling9bc96a52009-02-03 00:55:04 +00003943
Devang Patel20dd0462008-11-06 00:30:09 +00003944 // Record the source line but does not create a label for the normal
3945 // function start. It will be emitted at asm emission time. However,
3946 // create a label if this is a beginning of inlined function.
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003947 unsigned Line = Subprogram.getLineNumber();
Bill Wendling9bc96a52009-02-03 00:55:04 +00003948 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
3949
Devang Patel83489bb2009-01-13 00:35:13 +00003950 if (DW->getRecordSourceLineCount() != 1)
Dale Johannesen8ad9b432009-02-04 01:17:06 +00003951 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3952 getRoot(), LabelID));
Bill Wendling9bc96a52009-02-03 00:55:04 +00003953
Dale Johannesen66978ee2009-01-31 02:22:37 +00003954 setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003955 getOrCreateDebugLocID(SrcFile, Line, 0)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003956 }
3957
3958 return 0;
3959 }
3960 case Intrinsic::dbg_declare: {
Devang Patel83489bb2009-01-13 00:35:13 +00003961 DwarfWriter *DW = DAG.getDwarfWriter();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003962 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3963 Value *Variable = DI.getVariable();
Devang Patelb79b5352009-01-19 23:21:49 +00003964 if (DW && DW->ValidDebugInfo(Variable))
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003965 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003966 getValue(DI.getAddress()), getValue(Variable)));
3967 return 0;
3968 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003969
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003970 case Intrinsic::eh_exception: {
3971 if (!CurMBB->isLandingPad()) {
3972 // FIXME: Mark exception register as live in. Hack for PR1508.
3973 unsigned Reg = TLI.getExceptionAddressRegister();
3974 if (Reg) CurMBB->addLiveIn(Reg);
3975 }
3976 // Insert the EXCEPTIONADDR instruction.
3977 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3978 SDValue Ops[1];
3979 Ops[0] = DAG.getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00003980 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003981 setValue(&I, Op);
3982 DAG.setRoot(Op.getValue(1));
3983 return 0;
3984 }
3985
3986 case Intrinsic::eh_selector_i32:
3987 case Intrinsic::eh_selector_i64: {
3988 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3989 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3990 MVT::i32 : MVT::i64);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00003991
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00003992 if (MMI) {
3993 if (CurMBB->isLandingPad())
3994 AddCatchInfo(I, MMI, CurMBB);
3995 else {
3996#ifndef NDEBUG
3997 FuncInfo.CatchInfoLost.insert(&I);
3998#endif
3999 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4000 unsigned Reg = TLI.getExceptionSelectorRegister();
4001 if (Reg) CurMBB->addLiveIn(Reg);
4002 }
4003
4004 // Insert the EHSELECTION instruction.
4005 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4006 SDValue Ops[2];
4007 Ops[0] = getValue(I.getOperand(1));
4008 Ops[1] = getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004009 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004010 setValue(&I, Op);
4011 DAG.setRoot(Op.getValue(1));
4012 } else {
4013 setValue(&I, DAG.getConstant(0, VT));
4014 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004015
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004016 return 0;
4017 }
4018
4019 case Intrinsic::eh_typeid_for_i32:
4020 case Intrinsic::eh_typeid_for_i64: {
4021 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4022 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4023 MVT::i32 : MVT::i64);
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004024
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004025 if (MMI) {
4026 // Find the type id for the given typeinfo.
4027 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4028
4029 unsigned TypeID = MMI->getTypeIDFor(GV);
4030 setValue(&I, DAG.getConstant(TypeID, VT));
4031 } else {
4032 // Return something different to eh_selector.
4033 setValue(&I, DAG.getConstant(1, VT));
4034 }
4035
4036 return 0;
4037 }
4038
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004039 case Intrinsic::eh_return_i32:
4040 case Intrinsic::eh_return_i64:
4041 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004042 MMI->setCallsEHReturn(true);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004043 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004044 MVT::Other,
4045 getControlRoot(),
4046 getValue(I.getOperand(1)),
4047 getValue(I.getOperand(2))));
4048 } else {
4049 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4050 }
4051
4052 return 0;
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004053 case Intrinsic::eh_unwind_init:
4054 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4055 MMI->setCallsUnwindInit(true);
4056 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004057
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004058 return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004059
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004060 case Intrinsic::eh_dwarf_cfa: {
4061 MVT VT = getValue(I.getOperand(1)).getValueType();
4062 SDValue CfaArg;
4063 if (VT.bitsGT(TLI.getPointerTy()))
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004064 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004065 TLI.getPointerTy(), getValue(I.getOperand(1)));
4066 else
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004067 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004068 TLI.getPointerTy(), getValue(I.getOperand(1)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004069
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004070 SDValue Offset = DAG.getNode(ISD::ADD, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004071 TLI.getPointerTy(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004072 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004073 TLI.getPointerTy()),
4074 CfaArg);
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004075 setValue(&I, DAG.getNode(ISD::ADD, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004076 TLI.getPointerTy(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004077 DAG.getNode(ISD::FRAMEADDR, dl,
Anton Korobeynikova0e8a1e2008-09-08 21:13:56 +00004078 TLI.getPointerTy(),
4079 DAG.getConstant(0,
4080 TLI.getPointerTy())),
4081 Offset));
4082 return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004083 }
4084
Mon P Wang77cdf302008-11-10 20:54:11 +00004085 case Intrinsic::convertff:
4086 case Intrinsic::convertfsi:
4087 case Intrinsic::convertfui:
4088 case Intrinsic::convertsif:
4089 case Intrinsic::convertuif:
4090 case Intrinsic::convertss:
4091 case Intrinsic::convertsu:
4092 case Intrinsic::convertus:
4093 case Intrinsic::convertuu: {
4094 ISD::CvtCode Code = ISD::CVT_INVALID;
4095 switch (Intrinsic) {
4096 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4097 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4098 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4099 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4100 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4101 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4102 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4103 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4104 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4105 }
4106 MVT DestVT = TLI.getValueType(I.getType());
4107 Value* Op1 = I.getOperand(1);
Dale Johannesena04b7572009-02-03 23:04:43 +00004108 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
Mon P Wang77cdf302008-11-10 20:54:11 +00004109 DAG.getValueType(DestVT),
4110 DAG.getValueType(getValue(Op1).getValueType()),
4111 getValue(I.getOperand(2)),
4112 getValue(I.getOperand(3)),
4113 Code));
4114 return 0;
4115 }
4116
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004117 case Intrinsic::sqrt:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004118 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004119 getValue(I.getOperand(1)).getValueType(),
4120 getValue(I.getOperand(1))));
4121 return 0;
4122 case Intrinsic::powi:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004123 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004124 getValue(I.getOperand(1)).getValueType(),
4125 getValue(I.getOperand(1)),
4126 getValue(I.getOperand(2))));
4127 return 0;
4128 case Intrinsic::sin:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004129 setValue(&I, DAG.getNode(ISD::FSIN, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004130 getValue(I.getOperand(1)).getValueType(),
4131 getValue(I.getOperand(1))));
4132 return 0;
4133 case Intrinsic::cos:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004134 setValue(&I, DAG.getNode(ISD::FCOS, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004135 getValue(I.getOperand(1)).getValueType(),
4136 getValue(I.getOperand(1))));
4137 return 0;
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004138 case Intrinsic::log:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004139 visitLog(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004140 return 0;
4141 case Intrinsic::log2:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004142 visitLog2(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004143 return 0;
4144 case Intrinsic::log10:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004145 visitLog10(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004146 return 0;
4147 case Intrinsic::exp:
Dale Johannesen59e577f2008-09-05 18:38:42 +00004148 visitExp(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004149 return 0;
4150 case Intrinsic::exp2:
Dale Johannesen601d3c02008-09-05 01:48:15 +00004151 visitExp2(I);
Dale Johannesen7794f2a2008-09-04 00:47:13 +00004152 return 0;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004153 case Intrinsic::pow:
Bill Wendlingaeb5c7b2008-09-10 00:20:20 +00004154 visitPow(I);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004155 return 0;
4156 case Intrinsic::pcmarker: {
4157 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004158 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004159 return 0;
4160 }
4161 case Intrinsic::readcyclecounter: {
4162 SDValue Op = getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004163 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004164 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
4165 &Op, 1);
4166 setValue(&I, Tmp);
4167 DAG.setRoot(Tmp.getValue(1));
4168 return 0;
4169 }
4170 case Intrinsic::part_select: {
4171 // Currently not implemented: just abort
4172 assert(0 && "part_select intrinsic not implemented");
4173 abort();
4174 }
4175 case Intrinsic::part_set: {
4176 // Currently not implemented: just abort
4177 assert(0 && "part_set intrinsic not implemented");
4178 abort();
4179 }
4180 case Intrinsic::bswap:
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004181 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004182 getValue(I.getOperand(1)).getValueType(),
4183 getValue(I.getOperand(1))));
4184 return 0;
4185 case Intrinsic::cttz: {
4186 SDValue Arg = getValue(I.getOperand(1));
4187 MVT Ty = Arg.getValueType();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004188 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004189 setValue(&I, result);
4190 return 0;
4191 }
4192 case Intrinsic::ctlz: {
4193 SDValue Arg = getValue(I.getOperand(1));
4194 MVT Ty = Arg.getValueType();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004195 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004196 setValue(&I, result);
4197 return 0;
4198 }
4199 case Intrinsic::ctpop: {
4200 SDValue Arg = getValue(I.getOperand(1));
4201 MVT Ty = Arg.getValueType();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004202 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004203 setValue(&I, result);
4204 return 0;
4205 }
4206 case Intrinsic::stacksave: {
4207 SDValue Op = getRoot();
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004208 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004209 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
4210 setValue(&I, Tmp);
4211 DAG.setRoot(Tmp.getValue(1));
4212 return 0;
4213 }
4214 case Intrinsic::stackrestore: {
4215 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004216 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004217 return 0;
4218 }
Bill Wendling57344502008-11-18 11:01:33 +00004219 case Intrinsic::stackprotector: {
Bill Wendlingb2a42982008-11-06 02:29:10 +00004220 // Emit code into the DAG to store the stack guard onto the stack.
4221 MachineFunction &MF = DAG.getMachineFunction();
4222 MachineFrameInfo *MFI = MF.getFrameInfo();
4223 MVT PtrTy = TLI.getPointerTy();
4224
Bill Wendlingb7c6ebc2008-11-07 01:23:58 +00004225 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4226 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
Bill Wendlingb2a42982008-11-06 02:29:10 +00004227
Bill Wendlingb7c6ebc2008-11-07 01:23:58 +00004228 int FI = FuncInfo.StaticAllocaMap[Slot];
Bill Wendlingb2a42982008-11-06 02:29:10 +00004229 MFI->setStackProtectorIndex(FI);
4230
4231 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4232
4233 // Store the stack protector onto the stack.
Dale Johannesen66978ee2009-01-31 02:22:37 +00004234 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
Bill Wendlingb2a42982008-11-06 02:29:10 +00004235 PseudoSourceValue::getFixedStack(FI),
4236 0, true);
4237 setValue(&I, Result);
4238 DAG.setRoot(Result);
4239 return 0;
4240 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004241 case Intrinsic::var_annotation:
4242 // Discard annotate attributes
4243 return 0;
4244
4245 case Intrinsic::init_trampoline: {
4246 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4247
4248 SDValue Ops[6];
4249 Ops[0] = getRoot();
4250 Ops[1] = getValue(I.getOperand(1));
4251 Ops[2] = getValue(I.getOperand(2));
4252 Ops[3] = getValue(I.getOperand(3));
4253 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4254 Ops[5] = DAG.getSrcValue(F);
4255
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004256 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004257 DAG.getNodeValueTypes(TLI.getPointerTy(),
4258 MVT::Other), 2,
4259 Ops, 6);
4260
4261 setValue(&I, Tmp);
4262 DAG.setRoot(Tmp.getValue(1));
4263 return 0;
4264 }
4265
4266 case Intrinsic::gcroot:
4267 if (GFI) {
4268 Value *Alloca = I.getOperand(1);
4269 Constant *TypeMap = cast<Constant>(I.getOperand(2));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004270
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004271 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4272 GFI->addStackRoot(FI->getIndex(), TypeMap);
4273 }
4274 return 0;
4275
4276 case Intrinsic::gcread:
4277 case Intrinsic::gcwrite:
4278 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4279 return 0;
4280
4281 case Intrinsic::flt_rounds: {
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004282 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004283 return 0;
4284 }
4285
4286 case Intrinsic::trap: {
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004287 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004288 return 0;
4289 }
Bill Wendling7cdc3c82008-11-21 02:03:52 +00004290
Bill Wendlingef375462008-11-21 02:38:44 +00004291 case Intrinsic::uadd_with_overflow:
Bill Wendling74c37652008-12-09 22:08:41 +00004292 return implVisitAluOverflow(I, ISD::UADDO);
4293 case Intrinsic::sadd_with_overflow:
4294 return implVisitAluOverflow(I, ISD::SADDO);
4295 case Intrinsic::usub_with_overflow:
4296 return implVisitAluOverflow(I, ISD::USUBO);
4297 case Intrinsic::ssub_with_overflow:
4298 return implVisitAluOverflow(I, ISD::SSUBO);
4299 case Intrinsic::umul_with_overflow:
4300 return implVisitAluOverflow(I, ISD::UMULO);
4301 case Intrinsic::smul_with_overflow:
4302 return implVisitAluOverflow(I, ISD::SMULO);
Bill Wendling7cdc3c82008-11-21 02:03:52 +00004303
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004304 case Intrinsic::prefetch: {
4305 SDValue Ops[4];
4306 Ops[0] = getRoot();
4307 Ops[1] = getValue(I.getOperand(1));
4308 Ops[2] = getValue(I.getOperand(2));
4309 Ops[3] = getValue(I.getOperand(3));
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004310 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004311 return 0;
4312 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004313
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004314 case Intrinsic::memory_barrier: {
4315 SDValue Ops[6];
4316 Ops[0] = getRoot();
4317 for (int x = 1; x < 6; ++x)
4318 Ops[x] = getValue(I.getOperand(x));
4319
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004320 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004321 return 0;
4322 }
4323 case Intrinsic::atomic_cmp_swap: {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004324 SDValue Root = getRoot();
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004325 SDValue L =
Dale Johannesen66978ee2009-01-31 02:22:37 +00004326 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004327 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4328 Root,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004329 getValue(I.getOperand(1)),
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004330 getValue(I.getOperand(2)),
4331 getValue(I.getOperand(3)),
4332 I.getOperand(1));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004333 setValue(&I, L);
4334 DAG.setRoot(L.getValue(1));
4335 return 0;
4336 }
4337 case Intrinsic::atomic_load_add:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004338 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004339 case Intrinsic::atomic_load_sub:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004340 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004341 case Intrinsic::atomic_load_or:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004342 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004343 case Intrinsic::atomic_load_xor:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004344 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004345 case Intrinsic::atomic_load_and:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004346 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004347 case Intrinsic::atomic_load_nand:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004348 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004349 case Intrinsic::atomic_load_max:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004350 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004351 case Intrinsic::atomic_load_min:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004352 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004353 case Intrinsic::atomic_load_umin:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004354 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004355 case Intrinsic::atomic_load_umax:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004356 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004357 case Intrinsic::atomic_swap:
Dan Gohman0b1d4a72008-12-23 21:37:04 +00004358 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004359 }
4360}
4361
4362
4363void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4364 bool IsTailCall,
4365 MachineBasicBlock *LandingPad) {
4366 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4367 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4368 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4369 unsigned BeginLabel = 0, EndLabel = 0;
4370
4371 TargetLowering::ArgListTy Args;
4372 TargetLowering::ArgListEntry Entry;
4373 Args.reserve(CS.arg_size());
4374 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4375 i != e; ++i) {
4376 SDValue ArgNode = getValue(*i);
4377 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4378
4379 unsigned attrInd = i - CS.arg_begin() + 1;
Devang Patel05988662008-09-25 21:00:45 +00004380 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4381 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4382 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4383 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4384 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4385 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004386 Entry.Alignment = CS.getParamAlignment(attrInd);
4387 Args.push_back(Entry);
4388 }
4389
4390 if (LandingPad && MMI) {
4391 // Insert a label before the invoke call to mark the try range. This can be
4392 // used to detect deletion of the invoke via the MachineModuleInfo.
4393 BeginLabel = MMI->NextLabelID();
4394 // Both PendingLoads and PendingExports must be flushed here;
4395 // this call might not return.
4396 (void)getRoot();
Dale Johannesen8ad9b432009-02-04 01:17:06 +00004397 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4398 getControlRoot(), BeginLabel));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004399 }
4400
4401 std::pair<SDValue,SDValue> Result =
4402 TLI.LowerCallTo(getRoot(), CS.getType(),
Devang Patel05988662008-09-25 21:00:45 +00004403 CS.paramHasAttr(0, Attribute::SExt),
Dale Johannesen86098bd2008-09-26 19:31:26 +00004404 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4405 CS.paramHasAttr(0, Attribute::InReg),
4406 CS.getCallingConv(),
Dan Gohman1937e2f2008-09-16 01:42:28 +00004407 IsTailCall && PerformTailCallOpt,
Dale Johannesen66978ee2009-01-31 02:22:37 +00004408 Callee, Args, DAG, getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004409 if (CS.getType() != Type::VoidTy)
4410 setValue(CS.getInstruction(), Result.first);
4411 DAG.setRoot(Result.second);
4412
4413 if (LandingPad && MMI) {
4414 // Insert a label at the end of the invoke call to mark the try range. This
4415 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4416 EndLabel = MMI->NextLabelID();
Dale Johannesen8ad9b432009-02-04 01:17:06 +00004417 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4418 getRoot(), EndLabel));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004419
4420 // Inform MachineModuleInfo of range.
4421 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4422 }
4423}
4424
4425
4426void SelectionDAGLowering::visitCall(CallInst &I) {
4427 const char *RenameFn = 0;
4428 if (Function *F = I.getCalledFunction()) {
4429 if (F->isDeclaration()) {
4430 if (unsigned IID = F->getIntrinsicID()) {
4431 RenameFn = visitIntrinsicCall(I, IID);
4432 if (!RenameFn)
4433 return;
4434 }
4435 }
4436
4437 // Check for well-known libc/libm calls. If the function is internal, it
4438 // can't be a library call.
4439 unsigned NameLen = F->getNameLen();
Rafael Espindolabb46f522009-01-15 20:18:42 +00004440 if (!F->hasLocalLinkage() && NameLen) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004441 const char *NameStr = F->getNameStart();
4442 if (NameStr[0] == 'c' &&
4443 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4444 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4445 if (I.getNumOperands() == 3 && // Basic sanity checks.
4446 I.getOperand(1)->getType()->isFloatingPoint() &&
4447 I.getType() == I.getOperand(1)->getType() &&
4448 I.getType() == I.getOperand(2)->getType()) {
4449 SDValue LHS = getValue(I.getOperand(1));
4450 SDValue RHS = getValue(I.getOperand(2));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004451 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004452 LHS.getValueType(), LHS, RHS));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004453 return;
4454 }
4455 } else if (NameStr[0] == 'f' &&
4456 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4457 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4458 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4459 if (I.getNumOperands() == 2 && // Basic sanity checks.
4460 I.getOperand(1)->getType()->isFloatingPoint() &&
4461 I.getType() == I.getOperand(1)->getType()) {
4462 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004463 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004464 Tmp.getValueType(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004465 return;
4466 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004467 } else if (NameStr[0] == 's' &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004468 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4469 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4470 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4471 if (I.getNumOperands() == 2 && // Basic sanity checks.
4472 I.getOperand(1)->getType()->isFloatingPoint() &&
4473 I.getType() == I.getOperand(1)->getType()) {
4474 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004475 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004476 Tmp.getValueType(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004477 return;
4478 }
4479 } else if (NameStr[0] == 'c' &&
4480 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4481 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4482 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4483 if (I.getNumOperands() == 2 && // Basic sanity checks.
4484 I.getOperand(1)->getType()->isFloatingPoint() &&
4485 I.getType() == I.getOperand(1)->getType()) {
4486 SDValue Tmp = getValue(I.getOperand(1));
Dale Johannesen66978ee2009-01-31 02:22:37 +00004487 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004488 Tmp.getValueType(), Tmp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004489 return;
4490 }
4491 }
4492 }
4493 } else if (isa<InlineAsm>(I.getOperand(0))) {
4494 visitInlineAsm(&I);
4495 return;
4496 }
4497
4498 SDValue Callee;
4499 if (!RenameFn)
4500 Callee = getValue(I.getOperand(0));
4501 else
Bill Wendling056292f2008-09-16 21:48:12 +00004502 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004503
4504 LowerCallTo(&I, Callee, I.isTailCall());
4505}
4506
4507
4508/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004509/// this value and returns the result as a ValueVT value. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004510/// Chain/Flag as the input and updates them for the output Chain/Flag.
4511/// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +00004512SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004513 SDValue &Chain,
4514 SDValue *Flag) const {
4515 // Assemble the legal parts into the final values.
4516 SmallVector<SDValue, 4> Values(ValueVTs.size());
4517 SmallVector<SDValue, 8> Parts;
4518 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4519 // Copy the legal parts from the registers.
4520 MVT ValueVT = ValueVTs[Value];
4521 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4522 MVT RegisterVT = RegVTs[Value];
4523
4524 Parts.resize(NumRegs);
4525 for (unsigned i = 0; i != NumRegs; ++i) {
4526 SDValue P;
4527 if (Flag == 0)
Dale Johannesena04b7572009-02-03 23:04:43 +00004528 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004529 else {
Dale Johannesena04b7572009-02-03 23:04:43 +00004530 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004531 *Flag = P.getValue(2);
4532 }
4533 Chain = P.getValue(1);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004534
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004535 // If the source register was virtual and if we know something about it,
4536 // add an assert node.
4537 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4538 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4539 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4540 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4541 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4542 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004543
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004544 unsigned RegSize = RegisterVT.getSizeInBits();
4545 unsigned NumSignBits = LOI.NumSignBits;
4546 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004547
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004548 // FIXME: We capture more information than the dag can represent. For
4549 // now, just use the tightest assertzext/assertsext possible.
4550 bool isSExt = true;
4551 MVT FromVT(MVT::Other);
4552 if (NumSignBits == RegSize)
4553 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4554 else if (NumZeroBits >= RegSize-1)
4555 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4556 else if (NumSignBits > RegSize-8)
4557 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4558 else if (NumZeroBits >= RegSize-9)
4559 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4560 else if (NumSignBits > RegSize-16)
Bill Wendling181b6272008-10-19 20:34:04 +00004561 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004562 else if (NumZeroBits >= RegSize-17)
Bill Wendling181b6272008-10-19 20:34:04 +00004563 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004564 else if (NumSignBits > RegSize-32)
Bill Wendling181b6272008-10-19 20:34:04 +00004565 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004566 else if (NumZeroBits >= RegSize-33)
Bill Wendling181b6272008-10-19 20:34:04 +00004567 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004568
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004569 if (FromVT != MVT::Other) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00004570 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004571 RegisterVT, P, DAG.getValueType(FromVT));
4572
4573 }
4574 }
4575 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004576
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004577 Parts[i] = P;
4578 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004579
Dale Johannesen66978ee2009-01-31 02:22:37 +00004580 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4581 NumRegs, RegisterVT, ValueVT);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004582 Part += NumRegs;
4583 Parts.clear();
4584 }
4585
Dale Johannesen66978ee2009-01-31 02:22:37 +00004586 return DAG.getNode(ISD::MERGE_VALUES, dl,
Duncan Sandsaaffa052008-12-01 11:41:29 +00004587 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4588 &Values[0], ValueVTs.size());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004589}
4590
4591/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004592/// specified value into the registers specified by this object. This uses
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004593/// Chain/Flag as the input and updates them for the output Chain/Flag.
4594/// If the Flag pointer is NULL, no flag is used.
Dale Johannesen66978ee2009-01-31 02:22:37 +00004595void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004596 SDValue &Chain, SDValue *Flag) const {
4597 // Get the list of the values's legal parts.
4598 unsigned NumRegs = Regs.size();
4599 SmallVector<SDValue, 8> Parts(NumRegs);
4600 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4601 MVT ValueVT = ValueVTs[Value];
4602 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4603 MVT RegisterVT = RegVTs[Value];
4604
Dale Johannesen66978ee2009-01-31 02:22:37 +00004605 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004606 &Parts[Part], NumParts, RegisterVT);
4607 Part += NumParts;
4608 }
4609
4610 // Copy the parts into the registers.
4611 SmallVector<SDValue, 8> Chains(NumRegs);
4612 for (unsigned i = 0; i != NumRegs; ++i) {
4613 SDValue Part;
4614 if (Flag == 0)
Dale Johannesena04b7572009-02-03 23:04:43 +00004615 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004616 else {
Dale Johannesena04b7572009-02-03 23:04:43 +00004617 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004618 *Flag = Part.getValue(1);
4619 }
4620 Chains[i] = Part.getValue(0);
4621 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004622
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004623 if (NumRegs == 1 || Flag)
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004624 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004625 // flagged to it. That is the CopyToReg nodes and the user are considered
4626 // a single scheduling unit. If we create a TokenFactor and return it as
4627 // chain, then the TokenFactor is both a predecessor (operand) of the
4628 // user as well as a successor (the TF operands are flagged to the user).
4629 // c1, f1 = CopyToReg
4630 // c2, f2 = CopyToReg
4631 // c3 = TokenFactor c1, c2
4632 // ...
4633 // = op c3, ..., f2
4634 Chain = Chains[NumRegs-1];
4635 else
Dale Johannesen66978ee2009-01-31 02:22:37 +00004636 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004637}
4638
4639/// AddInlineAsmOperands - Add this value to the specified inlineasm node
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004640/// operand list. This adds the code marker and includes the number of
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004641/// values added into it.
4642void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
4643 std::vector<SDValue> &Ops) const {
4644 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4645 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
4646 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4647 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4648 MVT RegisterVT = RegVTs[Value];
Chris Lattner58f15c42008-10-17 16:21:11 +00004649 for (unsigned i = 0; i != NumRegs; ++i) {
4650 assert(Reg < Regs.size() && "Mismatch in # registers expected");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004651 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
Chris Lattner58f15c42008-10-17 16:21:11 +00004652 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004653 }
4654}
4655
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004656/// isAllocatableRegister - If the specified register is safe to allocate,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004657/// i.e. it isn't a stack pointer or some other special register, return the
4658/// register class for the register. Otherwise, return null.
4659static const TargetRegisterClass *
4660isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4661 const TargetLowering &TLI,
4662 const TargetRegisterInfo *TRI) {
4663 MVT FoundVT = MVT::Other;
4664 const TargetRegisterClass *FoundRC = 0;
4665 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4666 E = TRI->regclass_end(); RCI != E; ++RCI) {
4667 MVT ThisVT = MVT::Other;
4668
4669 const TargetRegisterClass *RC = *RCI;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004670 // If none of the the value types for this register class are valid, we
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004671 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4672 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4673 I != E; ++I) {
4674 if (TLI.isTypeLegal(*I)) {
4675 // If we have already found this register in a different register class,
4676 // choose the one with the largest VT specified. For example, on
4677 // PowerPC, we favor f64 register classes over f32.
4678 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4679 ThisVT = *I;
4680 break;
4681 }
4682 }
4683 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004684
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004685 if (ThisVT == MVT::Other) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004686
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004687 // NOTE: This isn't ideal. In particular, this might allocate the
4688 // frame pointer in functions that need it (due to them not being taken
4689 // out of allocation, because a variable sized allocation hasn't been seen
4690 // yet). This is a slight code pessimization, but should still work.
4691 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4692 E = RC->allocation_order_end(MF); I != E; ++I)
4693 if (*I == Reg) {
4694 // We found a matching register class. Keep looking at others in case
4695 // we find one with larger registers that this physreg is also in.
4696 FoundRC = RC;
4697 FoundVT = ThisVT;
4698 break;
4699 }
4700 }
4701 return FoundRC;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004702}
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004703
4704
4705namespace llvm {
4706/// AsmOperandInfo - This contains information for each constraint that we are
4707/// lowering.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004708struct VISIBILITY_HIDDEN SDISelAsmOperandInfo :
Daniel Dunbarc0c3b9a2008-09-10 04:16:29 +00004709 public TargetLowering::AsmOperandInfo {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004710 /// CallOperand - If this is the result output operand or a clobber
4711 /// this is null, otherwise it is the incoming operand to the CallInst.
4712 /// This gets modified as the asm is processed.
4713 SDValue CallOperand;
4714
4715 /// AssignedRegs - If this is a register or register class operand, this
4716 /// contains the set of register corresponding to the operand.
4717 RegsForValue AssignedRegs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004718
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004719 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4720 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4721 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004722
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004723 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4724 /// busy in OutputRegs/InputRegs.
4725 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004726 std::set<unsigned> &OutputRegs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004727 std::set<unsigned> &InputRegs,
4728 const TargetRegisterInfo &TRI) const {
4729 if (isOutReg) {
4730 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4731 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4732 }
4733 if (isInReg) {
4734 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4735 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4736 }
4737 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004738
Chris Lattner81249c92008-10-17 17:05:25 +00004739 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4740 /// corresponds to. If there is no Value* for this operand, it returns
4741 /// MVT::Other.
4742 MVT getCallOperandValMVT(const TargetLowering &TLI,
4743 const TargetData *TD) const {
4744 if (CallOperandVal == 0) return MVT::Other;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004745
Chris Lattner81249c92008-10-17 17:05:25 +00004746 if (isa<BasicBlock>(CallOperandVal))
4747 return TLI.getPointerTy();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004748
Chris Lattner81249c92008-10-17 17:05:25 +00004749 const llvm::Type *OpTy = CallOperandVal->getType();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004750
Chris Lattner81249c92008-10-17 17:05:25 +00004751 // If this is an indirect operand, the operand is a pointer to the
4752 // accessed type.
4753 if (isIndirect)
4754 OpTy = cast<PointerType>(OpTy)->getElementType();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004755
Chris Lattner81249c92008-10-17 17:05:25 +00004756 // If OpTy is not a single value, it may be a struct/union that we
4757 // can tile with integers.
4758 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4759 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4760 switch (BitSize) {
4761 default: break;
4762 case 1:
4763 case 8:
4764 case 16:
4765 case 32:
4766 case 64:
Chris Lattnercfc14c12008-10-17 19:59:51 +00004767 case 128:
Chris Lattner81249c92008-10-17 17:05:25 +00004768 OpTy = IntegerType::get(BitSize);
4769 break;
4770 }
4771 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004772
Chris Lattner81249c92008-10-17 17:05:25 +00004773 return TLI.getValueType(OpTy, true);
4774 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004775
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004776private:
4777 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4778 /// specified set.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004779 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004780 const TargetRegisterInfo &TRI) {
4781 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4782 Regs.insert(Reg);
4783 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4784 for (; *Aliases; ++Aliases)
4785 Regs.insert(*Aliases);
4786 }
4787};
4788} // end llvm namespace.
4789
4790
4791/// GetRegistersForValue - Assign registers (virtual or physical) for the
4792/// specified operand. We prefer to assign virtual registers, to allow the
4793/// register allocator handle the assignment process. However, if the asm uses
4794/// features that we can't model on machineinstrs, we have SDISel do the
4795/// allocation. This produces generally horrible, but correct, code.
4796///
4797/// OpInfo describes the operand.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004798/// Input and OutputRegs are the set of already allocated physical registers.
4799///
4800void SelectionDAGLowering::
Dale Johannesen8e3455b2008-09-24 23:13:09 +00004801GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004802 std::set<unsigned> &OutputRegs,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004803 std::set<unsigned> &InputRegs) {
4804 // Compute whether this value requires an input register, an output register,
4805 // or both.
4806 bool isOutReg = false;
4807 bool isInReg = false;
4808 switch (OpInfo.Type) {
4809 case InlineAsm::isOutput:
4810 isOutReg = true;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004811
4812 // If there is an input constraint that matches this, we need to reserve
Dale Johannesen8e3455b2008-09-24 23:13:09 +00004813 // the input register so no other inputs allocate to it.
Chris Lattner6bdcda32008-10-17 16:47:46 +00004814 isInReg = OpInfo.hasMatchingInput();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004815 break;
4816 case InlineAsm::isInput:
4817 isInReg = true;
4818 isOutReg = false;
4819 break;
4820 case InlineAsm::isClobber:
4821 isOutReg = true;
4822 isInReg = true;
4823 break;
4824 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004825
4826
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004827 MachineFunction &MF = DAG.getMachineFunction();
4828 SmallVector<unsigned, 4> Regs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004829
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004830 // If this is a constraint for a single physreg, or a constraint for a
4831 // register class, find it.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004832 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004833 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4834 OpInfo.ConstraintVT);
4835
4836 unsigned NumRegs = 1;
Chris Lattner01426e12008-10-21 00:45:36 +00004837 if (OpInfo.ConstraintVT != MVT::Other) {
4838 // If this is a FP input in an integer register (or visa versa) insert a bit
4839 // cast of the input value. More generally, handle any case where the input
4840 // value disagrees with the register class we plan to stick this in.
4841 if (OpInfo.Type == InlineAsm::isInput &&
4842 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4843 // Try to convert to the first MVT that the reg class contains. If the
4844 // types are identical size, use a bitcast to convert (e.g. two differing
4845 // vector types).
4846 MVT RegVT = *PhysReg.second->vt_begin();
4847 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00004848 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004849 RegVT, OpInfo.CallOperand);
Chris Lattner01426e12008-10-21 00:45:36 +00004850 OpInfo.ConstraintVT = RegVT;
4851 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4852 // If the input is a FP value and we want it in FP registers, do a
4853 // bitcast to the corresponding integer type. This turns an f64 value
4854 // into i64, which can be passed with two i32 values on a 32-bit
4855 // machine.
4856 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
Dale Johannesen66978ee2009-01-31 02:22:37 +00004857 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00004858 RegVT, OpInfo.CallOperand);
Chris Lattner01426e12008-10-21 00:45:36 +00004859 OpInfo.ConstraintVT = RegVT;
4860 }
4861 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004862
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004863 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
Chris Lattner01426e12008-10-21 00:45:36 +00004864 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004865
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004866 MVT RegVT;
4867 MVT ValueVT = OpInfo.ConstraintVT;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004868
4869 // If this is a constraint for a specific physical register, like {r17},
4870 // assign it now.
4871 if (PhysReg.first) {
4872 if (OpInfo.ConstraintVT == MVT::Other)
4873 ValueVT = *PhysReg.second->vt_begin();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004874
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004875 // Get the actual register value type. This is important, because the user
4876 // may have asked for (e.g.) the AX register in i32 type. We need to
4877 // remember that AX is actually i16 to get the right extension.
4878 RegVT = *PhysReg.second->vt_begin();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004879
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004880 // This is a explicit reference to a physical register.
4881 Regs.push_back(PhysReg.first);
4882
4883 // If this is an expanded reference, add the rest of the regs to Regs.
4884 if (NumRegs != 1) {
4885 TargetRegisterClass::iterator I = PhysReg.second->begin();
4886 for (; *I != PhysReg.first; ++I)
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004887 assert(I != PhysReg.second->end() && "Didn't find reg!");
4888
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004889 // Already added the first reg.
4890 --NumRegs; ++I;
4891 for (; NumRegs; --NumRegs, ++I) {
4892 assert(I != PhysReg.second->end() && "Ran out of registers to allocate!");
4893 Regs.push_back(*I);
4894 }
4895 }
4896 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4897 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4898 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4899 return;
4900 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004901
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004902 // Otherwise, if this was a reference to an LLVM register class, create vregs
4903 // for this reference.
4904 std::vector<unsigned> RegClassRegs;
4905 const TargetRegisterClass *RC = PhysReg.second;
4906 if (RC) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004907 // If this is a tied register, our regalloc doesn't know how to maintain
Chris Lattner58f15c42008-10-17 16:21:11 +00004908 // the constraint, so we have to pick a register to pin the input/output to.
4909 // If it isn't a matched constraint, go ahead and create vreg and let the
4910 // regalloc do its thing.
Chris Lattner6bdcda32008-10-17 16:47:46 +00004911 if (!OpInfo.hasMatchingInput()) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004912 RegVT = *PhysReg.second->vt_begin();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004913 if (OpInfo.ConstraintVT == MVT::Other)
4914 ValueVT = RegVT;
4915
4916 // Create the appropriate number of virtual registers.
4917 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4918 for (; NumRegs; --NumRegs)
4919 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004920
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004921 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4922 return;
4923 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004924
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004925 // Otherwise, we can't allocate it. Let the code below figure out how to
4926 // maintain these constraints.
4927 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004928
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004929 } else {
4930 // This is a reference to a register class that doesn't directly correspond
4931 // to an LLVM register class. Allocate NumRegs consecutive, available,
4932 // registers from the class.
4933 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4934 OpInfo.ConstraintVT);
4935 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004936
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004937 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4938 unsigned NumAllocated = 0;
4939 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4940 unsigned Reg = RegClassRegs[i];
4941 // See if this register is available.
4942 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4943 (isInReg && InputRegs.count(Reg))) { // Already used.
4944 // Make sure we find consecutive registers.
4945 NumAllocated = 0;
4946 continue;
4947 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004948
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004949 // Check to see if this register is allocatable (i.e. don't give out the
4950 // stack pointer).
4951 if (RC == 0) {
4952 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4953 if (!RC) { // Couldn't allocate this register.
4954 // Reset NumAllocated to make sure we return consecutive registers.
4955 NumAllocated = 0;
4956 continue;
4957 }
4958 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004959
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004960 // Okay, this register is good, we can use it.
4961 ++NumAllocated;
4962
4963 // If we allocated enough consecutive registers, succeed.
4964 if (NumAllocated == NumRegs) {
4965 unsigned RegStart = (i-NumAllocated)+1;
4966 unsigned RegEnd = i+1;
4967 // Mark all of the allocated registers used.
4968 for (unsigned i = RegStart; i != RegEnd; ++i)
4969 Regs.push_back(RegClassRegs[i]);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004970
4971 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004972 OpInfo.ConstraintVT);
4973 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4974 return;
4975 }
4976 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00004977
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004978 // Otherwise, we couldn't allocate enough registers for this.
4979}
4980
Evan Chengda43bcf2008-09-24 00:05:32 +00004981/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4982/// processed uses a memory 'm' constraint.
4983static bool
4984hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
Dan Gohmane9530ec2009-01-15 16:58:17 +00004985 const TargetLowering &TLI) {
Evan Chengda43bcf2008-09-24 00:05:32 +00004986 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4987 InlineAsm::ConstraintInfo &CI = CInfos[i];
4988 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4989 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4990 if (CType == TargetLowering::C_Memory)
4991 return true;
4992 }
4993 }
4994
4995 return false;
4996}
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00004997
4998/// visitInlineAsm - Handle a call to an InlineAsm object.
4999///
5000void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5001 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5002
5003 /// ConstraintOperands - Information about all of the constraints.
5004 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005005
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005006 SDValue Chain = getRoot();
5007 SDValue Flag;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005008
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005009 std::set<unsigned> OutputRegs, InputRegs;
5010
5011 // Do a prepass over the constraints, canonicalizing them, and building up the
5012 // ConstraintOperands list.
5013 std::vector<InlineAsm::ConstraintInfo>
5014 ConstraintInfos = IA->ParseConstraints();
5015
Evan Chengda43bcf2008-09-24 00:05:32 +00005016 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005017
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005018 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5019 unsigned ResNo = 0; // ResNo - The result number of the next output.
5020 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5021 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5022 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005023
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005024 MVT OpVT = MVT::Other;
5025
5026 // Compute the value type for each operand.
5027 switch (OpInfo.Type) {
5028 case InlineAsm::isOutput:
5029 // Indirect outputs just consume an argument.
5030 if (OpInfo.isIndirect) {
5031 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5032 break;
5033 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005034
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005035 // The return value of the call is this value. As such, there is no
5036 // corresponding argument.
5037 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5038 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5039 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5040 } else {
5041 assert(ResNo == 0 && "Asm only has one result!");
5042 OpVT = TLI.getValueType(CS.getType());
5043 }
5044 ++ResNo;
5045 break;
5046 case InlineAsm::isInput:
5047 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5048 break;
5049 case InlineAsm::isClobber:
5050 // Nothing to do.
5051 break;
5052 }
5053
5054 // If this is an input or an indirect output, process the call argument.
5055 // BasicBlocks are labels, currently appearing only in asm's.
5056 if (OpInfo.CallOperandVal) {
Chris Lattner81249c92008-10-17 17:05:25 +00005057 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005058 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
Chris Lattner81249c92008-10-17 17:05:25 +00005059 } else {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005060 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005061 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005062
Chris Lattner81249c92008-10-17 17:05:25 +00005063 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005064 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005065
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005066 OpInfo.ConstraintVT = OpVT;
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005067 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005068
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005069 // Second pass over the constraints: compute which constraint option to use
5070 // and assign registers to constraints that want a specific physreg.
5071 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5072 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005073
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005074 // If this is an output operand with a matching input operand, look up the
Evan Cheng09dc9c02008-12-16 18:21:39 +00005075 // matching input. If their types mismatch, e.g. one is an integer, the
5076 // other is floating point, or their sizes are different, flag it as an
5077 // error.
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005078 if (OpInfo.hasMatchingInput()) {
5079 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5080 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Evan Cheng09dc9c02008-12-16 18:21:39 +00005081 if ((OpInfo.ConstraintVT.isInteger() !=
5082 Input.ConstraintVT.isInteger()) ||
5083 (OpInfo.ConstraintVT.getSizeInBits() !=
5084 Input.ConstraintVT.getSizeInBits())) {
5085 cerr << "Unsupported asm: input constraint with a matching output "
5086 << "constraint of incompatible type!\n";
5087 exit(1);
5088 }
5089 Input.ConstraintVT = OpInfo.ConstraintVT;
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005090 }
5091 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005092
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005093 // Compute the constraint code and ConstraintType to use.
Evan Chengda43bcf2008-09-24 00:05:32 +00005094 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005095
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005096 // If this is a memory input, and if the operand is not indirect, do what we
5097 // need to to provide an address for the memory input.
5098 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5099 !OpInfo.isIndirect) {
5100 assert(OpInfo.Type == InlineAsm::isInput &&
5101 "Can only indirectify direct input operands!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005102
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005103 // Memory operands really want the address of the value. If we don't have
5104 // an indirect input, put it in the constpool if we can, otherwise spill
5105 // it to a stack slot.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005106
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005107 // If the operand is a float, integer, or vector constant, spill to a
5108 // constant pool entry to get its address.
5109 Value *OpVal = OpInfo.CallOperandVal;
5110 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5111 isa<ConstantVector>(OpVal)) {
5112 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5113 TLI.getPointerTy());
5114 } else {
5115 // Otherwise, create a stack slot and emit a store to it before the
5116 // asm.
5117 const Type *Ty = OpVal->getType();
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005118 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005119 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5120 MachineFunction &MF = DAG.getMachineFunction();
5121 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5122 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
Dale Johannesen66978ee2009-01-31 02:22:37 +00005123 Chain = DAG.getStore(Chain, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005124 OpInfo.CallOperand, StackSlot, NULL, 0);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005125 OpInfo.CallOperand = StackSlot;
5126 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005127
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005128 // There is no longer a Value* corresponding to this operand.
5129 OpInfo.CallOperandVal = 0;
5130 // It is now an indirect operand.
5131 OpInfo.isIndirect = true;
5132 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005133
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005134 // If this constraint is for a specific register, allocate it before
5135 // anything else.
5136 if (OpInfo.ConstraintType == TargetLowering::C_Register)
Dale Johannesen8e3455b2008-09-24 23:13:09 +00005137 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005138 }
5139 ConstraintInfos.clear();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005140
5141
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005142 // Second pass - Loop over all of the operands, assigning virtual or physregs
Chris Lattner58f15c42008-10-17 16:21:11 +00005143 // to register class operands.
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005144 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5145 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005146
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005147 // C_Register operands have already been allocated, Other/Memory don't need
5148 // to be.
5149 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
Dale Johannesen8e3455b2008-09-24 23:13:09 +00005150 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005151 }
5152
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005153 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5154 std::vector<SDValue> AsmNodeOperands;
5155 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5156 AsmNodeOperands.push_back(
Bill Wendling056292f2008-09-16 21:48:12 +00005157 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005158
5159
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005160 // Loop over all of the inputs, copying the operand values into the
5161 // appropriate registers and processing the output regs.
5162 RegsForValue RetValRegs;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005163
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005164 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5165 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005166
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005167 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5168 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5169
5170 switch (OpInfo.Type) {
5171 case InlineAsm::isOutput: {
5172 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5173 OpInfo.ConstraintType != TargetLowering::C_Register) {
5174 // Memory output, or 'other' output (e.g. 'X' constraint).
5175 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5176
5177 // Add information to the INLINEASM node to know about this output.
Dale Johannesen86b49f82008-09-24 01:07:17 +00005178 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5179 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005180 TLI.getPointerTy()));
5181 AsmNodeOperands.push_back(OpInfo.CallOperand);
5182 break;
5183 }
5184
5185 // Otherwise, this is a register or register class output.
5186
5187 // Copy the output from the appropriate register. Find a register that
5188 // we can use.
5189 if (OpInfo.AssignedRegs.Regs.empty()) {
5190 cerr << "Couldn't allocate output reg for constraint '"
5191 << OpInfo.ConstraintCode << "'!\n";
5192 exit(1);
5193 }
5194
5195 // If this is an indirect operand, store through the pointer after the
5196 // asm.
5197 if (OpInfo.isIndirect) {
5198 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5199 OpInfo.CallOperandVal));
5200 } else {
5201 // This is the result value of the call.
5202 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5203 // Concatenate this output onto the outputs list.
5204 RetValRegs.append(OpInfo.AssignedRegs);
5205 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005206
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005207 // Add information to the INLINEASM node to know that this register is
5208 // set.
Dale Johannesen913d3df2008-09-12 17:49:03 +00005209 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5210 6 /* EARLYCLOBBER REGDEF */ :
5211 2 /* REGDEF */ ,
5212 DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005213 break;
5214 }
5215 case InlineAsm::isInput: {
5216 SDValue InOperandVal = OpInfo.CallOperand;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005217
Chris Lattner6bdcda32008-10-17 16:47:46 +00005218 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005219 // If this is required to match an output register we have already set,
5220 // just use its register.
Chris Lattner58f15c42008-10-17 16:21:11 +00005221 unsigned OperandNo = OpInfo.getMatchedOperand();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005222
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005223 // Scan until we find the definition we already emitted of this operand.
5224 // When we find it, create a RegsForValue operand.
5225 unsigned CurOp = 2; // The first operand.
5226 for (; OperandNo; --OperandNo) {
5227 // Advance to the next operand.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005228 unsigned NumOps =
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005229 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005230 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
Dale Johannesen913d3df2008-09-12 17:49:03 +00005231 (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
Dale Johannesen86b49f82008-09-24 01:07:17 +00005232 (NumOps & 7) == 4 /*MEM*/) &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005233 "Skipped past definitions?");
5234 CurOp += (NumOps>>3)+1;
5235 }
5236
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005237 unsigned NumOps =
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00005238 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005239 if ((NumOps & 7) == 2 /*REGDEF*/
Dale Johannesen913d3df2008-09-12 17:49:03 +00005240 || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005241 // Add NumOps>>3 registers to MatchedRegs.
5242 RegsForValue MatchedRegs;
5243 MatchedRegs.TLI = &TLI;
5244 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5245 MatchedRegs.RegVTs.push_back(AsmNodeOperands[CurOp+1].getValueType());
5246 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
5247 unsigned Reg =
5248 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
5249 MatchedRegs.Regs.push_back(Reg);
5250 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005251
5252 // Use the produced MatchedRegs object to
Dale Johannesen66978ee2009-01-31 02:22:37 +00005253 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5254 Chain, &Flag);
Dale Johannesen86b49f82008-09-24 01:07:17 +00005255 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005256 break;
5257 } else {
Dale Johannesen86b49f82008-09-24 01:07:17 +00005258 assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005259 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005260 // Add information to the INLINEASM node to know about this input.
Dale Johannesen91aac102008-09-17 21:13:11 +00005261 AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005262 TLI.getPointerTy()));
5263 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5264 break;
5265 }
5266 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005267
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005268 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005269 assert(!OpInfo.isIndirect &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005270 "Don't know how to handle indirect other inputs yet!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005271
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005272 std::vector<SDValue> Ops;
5273 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
Evan Chengda43bcf2008-09-24 00:05:32 +00005274 hasMemory, Ops, DAG);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005275 if (Ops.empty()) {
5276 cerr << "Invalid operand for inline asm constraint '"
5277 << OpInfo.ConstraintCode << "'!\n";
5278 exit(1);
5279 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005280
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005281 // Add information to the INLINEASM node to know about this input.
5282 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005283 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005284 TLI.getPointerTy()));
5285 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5286 break;
5287 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5288 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5289 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5290 "Memory operands expect pointer values");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005291
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005292 // Add information to the INLINEASM node to know about this input.
Dale Johannesen86b49f82008-09-24 01:07:17 +00005293 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5294 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005295 TLI.getPointerTy()));
5296 AsmNodeOperands.push_back(InOperandVal);
5297 break;
5298 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005299
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005300 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5301 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5302 "Unknown constraint type!");
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005303 assert(!OpInfo.isIndirect &&
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005304 "Don't know how to handle indirect register inputs yet!");
5305
5306 // Copy the input into the appropriate registers.
Evan Chengaa765b82008-09-25 00:14:04 +00005307 if (OpInfo.AssignedRegs.Regs.empty()) {
5308 cerr << "Couldn't allocate output reg for constraint '"
5309 << OpInfo.ConstraintCode << "'!\n";
5310 exit(1);
5311 }
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005312
Dale Johannesen66978ee2009-01-31 02:22:37 +00005313 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5314 Chain, &Flag);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005315
Dale Johannesen86b49f82008-09-24 01:07:17 +00005316 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
5317 DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005318 break;
5319 }
5320 case InlineAsm::isClobber: {
5321 // Add the clobbered value to the operand list, so that the register
5322 // allocator is aware that the physreg got clobbered.
5323 if (!OpInfo.AssignedRegs.Regs.empty())
Dale Johannesen91aac102008-09-17 21:13:11 +00005324 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5325 DAG, AsmNodeOperands);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005326 break;
5327 }
5328 }
5329 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005330
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005331 // Finish up input operands.
5332 AsmNodeOperands[0] = Chain;
5333 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005334
Dale Johannesen66978ee2009-01-31 02:22:37 +00005335 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005336 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
5337 &AsmNodeOperands[0], AsmNodeOperands.size());
5338 Flag = Chain.getValue(1);
5339
5340 // If this asm returns a register value, copy the result from that register
5341 // and set it as the value of the call.
5342 if (!RetValRegs.Regs.empty()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005343 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5344 Chain, &Flag);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005345
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005346 // FIXME: Why don't we do this for inline asms with MRVs?
5347 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5348 MVT ResultType = TLI.getValueType(CS.getType());
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005349
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005350 // If any of the results of the inline asm is a vector, it may have the
5351 // wrong width/num elts. This can happen for register classes that can
5352 // contain multiple different value types. The preg or vreg allocated may
5353 // not have the same VT as was expected. Convert it to the right type
5354 // with bit_convert.
5355 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005356 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005357 ResultType, Val);
Dan Gohman95915732008-10-18 01:03:45 +00005358
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005359 } else if (ResultType != Val.getValueType() &&
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005360 ResultType.isInteger() && Val.getValueType().isInteger()) {
5361 // If a result value was tied to an input value, the computed result may
5362 // have a wider width than the expected result. Extract the relevant
5363 // portion.
Dale Johannesen66978ee2009-01-31 02:22:37 +00005364 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
Dan Gohman95915732008-10-18 01:03:45 +00005365 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005366
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005367 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
Chris Lattner0c526442008-10-17 17:52:49 +00005368 }
Dan Gohman95915732008-10-18 01:03:45 +00005369
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005370 setValue(CS.getInstruction(), Val);
5371 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005372
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005373 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005374
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005375 // Process indirect outputs, first output all of the flagged copies out of
5376 // physregs.
5377 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5378 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5379 Value *Ptr = IndirectStoresToEmit[i].second;
Dale Johannesen66978ee2009-01-31 02:22:37 +00005380 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5381 Chain, &Flag);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005382 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5383 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005384
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005385 // Emit the non-flagged stores from the physregs.
5386 SmallVector<SDValue, 8> OutChains;
5387 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
Dale Johannesen66978ee2009-01-31 02:22:37 +00005388 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005389 StoresToEmit[i].first,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005390 getValue(StoresToEmit[i].second),
5391 StoresToEmit[i].second, 0));
5392 if (!OutChains.empty())
Dale Johannesen66978ee2009-01-31 02:22:37 +00005393 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005394 &OutChains[0], OutChains.size());
5395 DAG.setRoot(Chain);
5396}
5397
5398
5399void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5400 SDValue Src = getValue(I.getOperand(0));
5401
5402 MVT IntPtr = TLI.getPointerTy();
5403
5404 if (IntPtr.bitsLT(Src.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00005405 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005406 else if (IntPtr.bitsGT(Src.getValueType()))
Dale Johannesen66978ee2009-01-31 02:22:37 +00005407 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005408
5409 // Scale the source by the type size.
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005410 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
Dale Johannesen66978ee2009-01-31 02:22:37 +00005411 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005412 Src, DAG.getIntPtrConstant(ElementSize));
5413
5414 TargetLowering::ArgListTy Args;
5415 TargetLowering::ArgListEntry Entry;
5416 Entry.Node = Src;
5417 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5418 Args.push_back(Entry);
5419
5420 std::pair<SDValue,SDValue> Result =
Dale Johannesen86098bd2008-09-26 19:31:26 +00005421 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005422 CallingConv::C, PerformTailCallOpt,
Dale Johannesen86098bd2008-09-26 19:31:26 +00005423 DAG.getExternalSymbol("malloc", IntPtr),
Dale Johannesen66978ee2009-01-31 02:22:37 +00005424 Args, DAG, getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005425 setValue(&I, Result.first); // Pointers always fit in registers
5426 DAG.setRoot(Result.second);
5427}
5428
5429void SelectionDAGLowering::visitFree(FreeInst &I) {
5430 TargetLowering::ArgListTy Args;
5431 TargetLowering::ArgListEntry Entry;
5432 Entry.Node = getValue(I.getOperand(0));
5433 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5434 Args.push_back(Entry);
5435 MVT IntPtr = TLI.getPointerTy();
5436 std::pair<SDValue,SDValue> Result =
Dale Johannesen86098bd2008-09-26 19:31:26 +00005437 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
Dan Gohman1937e2f2008-09-16 01:42:28 +00005438 CallingConv::C, PerformTailCallOpt,
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005439 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
Dale Johannesen66978ee2009-01-31 02:22:37 +00005440 getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005441 DAG.setRoot(Result.second);
5442}
5443
5444void SelectionDAGLowering::visitVAStart(CallInst &I) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005445 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005446 MVT::Other, getRoot(),
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005447 getValue(I.getOperand(1)),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005448 DAG.getSrcValue(I.getOperand(1))));
5449}
5450
5451void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
Dale Johannesena04b7572009-02-03 23:04:43 +00005452 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5453 getRoot(), getValue(I.getOperand(0)),
5454 DAG.getSrcValue(I.getOperand(0)));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005455 setValue(&I, V);
5456 DAG.setRoot(V.getValue(1));
5457}
5458
5459void SelectionDAGLowering::visitVAEnd(CallInst &I) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005460 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005461 MVT::Other, getRoot(),
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005462 getValue(I.getOperand(1)),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005463 DAG.getSrcValue(I.getOperand(1))));
5464}
5465
5466void SelectionDAGLowering::visitVACopy(CallInst &I) {
Dale Johannesen66978ee2009-01-31 02:22:37 +00005467 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005468 MVT::Other, getRoot(),
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005469 getValue(I.getOperand(1)),
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005470 getValue(I.getOperand(2)),
5471 DAG.getSrcValue(I.getOperand(1)),
5472 DAG.getSrcValue(I.getOperand(2))));
5473}
5474
5475/// TargetLowering::LowerArguments - This is the default LowerArguments
5476/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005477/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005478/// integrated into SDISel.
5479void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005480 SmallVectorImpl<SDValue> &ArgValues,
5481 DebugLoc dl) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005482 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5483 SmallVector<SDValue, 3+16> Ops;
5484 Ops.push_back(DAG.getRoot());
5485 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5486 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5487
5488 // Add one result value for each formal argument.
5489 SmallVector<MVT, 16> RetVals;
5490 unsigned j = 1;
5491 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5492 I != E; ++I, ++j) {
5493 SmallVector<MVT, 4> ValueVTs;
5494 ComputeValueVTs(*this, I->getType(), ValueVTs);
5495 for (unsigned Value = 0, NumValues = ValueVTs.size();
5496 Value != NumValues; ++Value) {
5497 MVT VT = ValueVTs[Value];
5498 const Type *ArgTy = VT.getTypeForMVT();
5499 ISD::ArgFlagsTy Flags;
5500 unsigned OriginalAlignment =
5501 getTargetData()->getABITypeAlignment(ArgTy);
5502
Devang Patel05988662008-09-25 21:00:45 +00005503 if (F.paramHasAttr(j, Attribute::ZExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005504 Flags.setZExt();
Devang Patel05988662008-09-25 21:00:45 +00005505 if (F.paramHasAttr(j, Attribute::SExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005506 Flags.setSExt();
Devang Patel05988662008-09-25 21:00:45 +00005507 if (F.paramHasAttr(j, Attribute::InReg))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005508 Flags.setInReg();
Devang Patel05988662008-09-25 21:00:45 +00005509 if (F.paramHasAttr(j, Attribute::StructRet))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005510 Flags.setSRet();
Devang Patel05988662008-09-25 21:00:45 +00005511 if (F.paramHasAttr(j, Attribute::ByVal)) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005512 Flags.setByVal();
5513 const PointerType *Ty = cast<PointerType>(I->getType());
5514 const Type *ElementTy = Ty->getElementType();
5515 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005516 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005517 // For ByVal, alignment should be passed from FE. BE will guess if
5518 // this info is not there but there are cases it cannot get right.
5519 if (F.getParamAlignment(j))
5520 FrameAlign = F.getParamAlignment(j);
5521 Flags.setByValAlign(FrameAlign);
5522 Flags.setByValSize(FrameSize);
5523 }
Devang Patel05988662008-09-25 21:00:45 +00005524 if (F.paramHasAttr(j, Attribute::Nest))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005525 Flags.setNest();
5526 Flags.setOrigAlign(OriginalAlignment);
5527
5528 MVT RegisterVT = getRegisterType(VT);
5529 unsigned NumRegs = getNumRegisters(VT);
5530 for (unsigned i = 0; i != NumRegs; ++i) {
5531 RetVals.push_back(RegisterVT);
5532 ISD::ArgFlagsTy MyFlags = Flags;
5533 if (NumRegs > 1 && i == 0)
5534 MyFlags.setSplit();
5535 // if it isn't first piece, alignment must be 1
5536 else if (i > 0)
5537 MyFlags.setOrigAlign(1);
5538 Ops.push_back(DAG.getArgFlags(MyFlags));
5539 }
5540 }
5541 }
5542
5543 RetVals.push_back(MVT::Other);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005544
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005545 // Create the node.
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005546 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005547 DAG.getVTList(&RetVals[0], RetVals.size()),
5548 &Ops[0], Ops.size()).getNode();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005549
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005550 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5551 // allows exposing the loads that may be part of the argument access to the
5552 // first DAGCombiner pass.
5553 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005554
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005555 // The number of results should match up, except that the lowered one may have
5556 // an extra flag result.
5557 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5558 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5559 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5560 && "Lowering produced unexpected number of results!");
5561
5562 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5563 if (Result != TmpRes.getNode() && Result->use_empty()) {
5564 HandleSDNode Dummy(DAG.getRoot());
5565 DAG.RemoveDeadNode(Result);
5566 }
5567
5568 Result = TmpRes.getNode();
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005569
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005570 unsigned NumArgRegs = Result->getNumValues() - 1;
5571 DAG.setRoot(SDValue(Result, NumArgRegs));
5572
5573 // Set up the return result vector.
5574 unsigned i = 0;
5575 unsigned Idx = 1;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005576 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005577 ++I, ++Idx) {
5578 SmallVector<MVT, 4> ValueVTs;
5579 ComputeValueVTs(*this, I->getType(), ValueVTs);
5580 for (unsigned Value = 0, NumValues = ValueVTs.size();
5581 Value != NumValues; ++Value) {
5582 MVT VT = ValueVTs[Value];
5583 MVT PartVT = getRegisterType(VT);
5584
5585 unsigned NumParts = getNumRegisters(VT);
5586 SmallVector<SDValue, 4> Parts(NumParts);
5587 for (unsigned j = 0; j != NumParts; ++j)
5588 Parts[j] = SDValue(Result, i++);
5589
5590 ISD::NodeType AssertOp = ISD::DELETED_NODE;
Devang Patel05988662008-09-25 21:00:45 +00005591 if (F.paramHasAttr(Idx, Attribute::SExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005592 AssertOp = ISD::AssertSext;
Devang Patel05988662008-09-25 21:00:45 +00005593 else if (F.paramHasAttr(Idx, Attribute::ZExt))
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005594 AssertOp = ISD::AssertZext;
5595
Dale Johannesen66978ee2009-01-31 02:22:37 +00005596 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5597 PartVT, VT, AssertOp));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005598 }
5599 }
5600 assert(i == NumArgRegs && "Argument register count mismatch!");
5601}
5602
5603
5604/// TargetLowering::LowerCallTo - This is the default LowerCallTo
5605/// implementation, which just inserts an ISD::CALL node, which is later custom
5606/// lowered by the target to something concrete. FIXME: When all targets are
5607/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5608std::pair<SDValue, SDValue>
5609TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5610 bool RetSExt, bool RetZExt, bool isVarArg,
Dale Johannesen86098bd2008-09-26 19:31:26 +00005611 bool isInreg,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005612 unsigned CallingConv, bool isTailCall,
5613 SDValue Callee,
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005614 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
Dan Gohman1937e2f2008-09-16 01:42:28 +00005615 assert((!isTailCall || PerformTailCallOpt) &&
5616 "isTailCall set when tail-call optimizations are disabled!");
5617
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005618 SmallVector<SDValue, 32> Ops;
5619 Ops.push_back(Chain); // Op#0 - Chain
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005620 Ops.push_back(Callee);
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005621
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005622 // Handle all of the outgoing arguments.
5623 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5624 SmallVector<MVT, 4> ValueVTs;
5625 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5626 for (unsigned Value = 0, NumValues = ValueVTs.size();
5627 Value != NumValues; ++Value) {
5628 MVT VT = ValueVTs[Value];
5629 const Type *ArgTy = VT.getTypeForMVT();
Chris Lattner2a0b96c2008-10-18 18:49:30 +00005630 SDValue Op = SDValue(Args[i].Node.getNode(),
5631 Args[i].Node.getResNo() + Value);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005632 ISD::ArgFlagsTy Flags;
5633 unsigned OriginalAlignment =
5634 getTargetData()->getABITypeAlignment(ArgTy);
5635
5636 if (Args[i].isZExt)
5637 Flags.setZExt();
5638 if (Args[i].isSExt)
5639 Flags.setSExt();
5640 if (Args[i].isInReg)
5641 Flags.setInReg();
5642 if (Args[i].isSRet)
5643 Flags.setSRet();
5644 if (Args[i].isByVal) {
5645 Flags.setByVal();
5646 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5647 const Type *ElementTy = Ty->getElementType();
5648 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
Duncan Sandsceb4d1a2009-01-12 20:38:59 +00005649 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005650 // For ByVal, alignment should come from FE. BE will guess if this
5651 // info is not there but there are cases it cannot get right.
5652 if (Args[i].Alignment)
5653 FrameAlign = Args[i].Alignment;
5654 Flags.setByValAlign(FrameAlign);
5655 Flags.setByValSize(FrameSize);
5656 }
5657 if (Args[i].isNest)
5658 Flags.setNest();
5659 Flags.setOrigAlign(OriginalAlignment);
5660
5661 MVT PartVT = getRegisterType(VT);
5662 unsigned NumParts = getNumRegisters(VT);
5663 SmallVector<SDValue, 4> Parts(NumParts);
5664 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5665
5666 if (Args[i].isSExt)
5667 ExtendKind = ISD::SIGN_EXTEND;
5668 else if (Args[i].isZExt)
5669 ExtendKind = ISD::ZERO_EXTEND;
5670
Dale Johannesen66978ee2009-01-31 02:22:37 +00005671 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005672
5673 for (unsigned i = 0; i != NumParts; ++i) {
5674 // if it isn't first piece, alignment must be 1
5675 ISD::ArgFlagsTy MyFlags = Flags;
5676 if (NumParts > 1 && i == 0)
5677 MyFlags.setSplit();
5678 else if (i != 0)
5679 MyFlags.setOrigAlign(1);
5680
5681 Ops.push_back(Parts[i]);
5682 Ops.push_back(DAG.getArgFlags(MyFlags));
5683 }
5684 }
5685 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005686
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005687 // Figure out the result value types. We start by making a list of
5688 // the potentially illegal return value types.
5689 SmallVector<MVT, 4> LoweredRetTys;
5690 SmallVector<MVT, 4> RetTys;
5691 ComputeValueVTs(*this, RetTy, RetTys);
5692
5693 // Then we translate that to a list of legal types.
5694 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5695 MVT VT = RetTys[I];
5696 MVT RegisterVT = getRegisterType(VT);
5697 unsigned NumRegs = getNumRegisters(VT);
5698 for (unsigned i = 0; i != NumRegs; ++i)
5699 LoweredRetTys.push_back(RegisterVT);
5700 }
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005701
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005702 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005703
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005704 // Create the CALL node.
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005705 SDValue Res = DAG.getCall(CallingConv, dl,
Dale Johannesenfa42dea2009-01-30 01:34:22 +00005706 isVarArg, isTailCall, isInreg,
Dan Gohman095cc292008-09-13 01:54:27 +00005707 DAG.getVTList(&LoweredRetTys[0],
5708 LoweredRetTys.size()),
Dale Johannesen86098bd2008-09-26 19:31:26 +00005709 &Ops[0], Ops.size()
5710 );
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005711 Chain = Res.getValue(LoweredRetTys.size() - 1);
5712
5713 // Gather up the call result into a single value.
Dan Gohmanb5cc34d2008-10-07 00:12:37 +00005714 if (RetTy != Type::VoidTy && !RetTys.empty()) {
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005715 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5716
5717 if (RetSExt)
5718 AssertOp = ISD::AssertSext;
5719 else if (RetZExt)
5720 AssertOp = ISD::AssertZext;
5721
5722 SmallVector<SDValue, 4> ReturnValues;
5723 unsigned RegNo = 0;
5724 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5725 MVT VT = RetTys[I];
5726 MVT RegisterVT = getRegisterType(VT);
5727 unsigned NumRegs = getNumRegisters(VT);
5728 unsigned RegNoEnd = NumRegs + RegNo;
5729 SmallVector<SDValue, 4> Results;
5730 for (; RegNo != RegNoEnd; ++RegNo)
5731 Results.push_back(Res.getValue(RegNo));
5732 SDValue ReturnValue =
Dale Johannesen66978ee2009-01-31 02:22:37 +00005733 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005734 AssertOp);
5735 ReturnValues.push_back(ReturnValue);
5736 }
Dale Johannesen7d2ad622009-01-30 23:10:59 +00005737 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
Duncan Sandsaaffa052008-12-01 11:41:29 +00005738 DAG.getVTList(&RetTys[0], RetTys.size()),
5739 &ReturnValues[0], ReturnValues.size());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005740 }
5741
5742 return std::make_pair(Res, Chain);
5743}
5744
Duncan Sands9fbc7e22009-01-21 09:00:29 +00005745void TargetLowering::LowerOperationWrapper(SDNode *N,
5746 SmallVectorImpl<SDValue> &Results,
5747 SelectionDAG &DAG) {
5748 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
Sanjiv Guptabb326bb2009-01-21 04:48:39 +00005749 if (Res.getNode())
5750 Results.push_back(Res);
5751}
5752
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005753SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5754 assert(0 && "LowerOperation not implemented for this target!");
5755 abort();
5756 return SDValue();
5757}
5758
5759
5760void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5761 SDValue Op = getValue(V);
5762 assert((Op.getOpcode() != ISD::CopyFromReg ||
5763 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5764 "Copy from a reg to the same reg!");
5765 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5766
5767 RegsForValue RFV(TLI, Reg, V->getType());
5768 SDValue Chain = DAG.getEntryNode();
Dale Johannesen66978ee2009-01-31 02:22:37 +00005769 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005770 PendingExports.push_back(Chain);
5771}
5772
5773#include "llvm/CodeGen/SelectionDAGISel.h"
5774
5775void SelectionDAGISel::
5776LowerArguments(BasicBlock *LLVMBB) {
5777 // If this is the entry block, emit arguments.
5778 Function &F = *LLVMBB->getParent();
5779 SDValue OldRoot = SDL->DAG.getRoot();
5780 SmallVector<SDValue, 16> Args;
Dale Johannesen66978ee2009-01-31 02:22:37 +00005781 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005782
5783 unsigned a = 0;
5784 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5785 AI != E; ++AI) {
5786 SmallVector<MVT, 4> ValueVTs;
5787 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5788 unsigned NumValues = ValueVTs.size();
5789 if (!AI->use_empty()) {
Dale Johannesen4be0bdf2009-02-05 00:20:09 +00005790 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5791 SDL->getCurDebugLoc()));
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005792 // If this argument is live outside of the entry block, insert a copy from
5793 // whereever we got it to the vreg that other BB's will reference it as.
5794 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
5795 if (VMI != FuncInfo->ValueMap.end()) {
5796 SDL->CopyValueToVirtualRegister(AI, VMI->second);
5797 }
5798 }
5799 a += NumValues;
5800 }
5801
5802 // Finally, if the target has anything special to do, allow it to do so.
5803 // FIXME: this should insert code into the DAG!
5804 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5805}
5806
5807/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5808/// ensure constants are generated when needed. Remember the virtual registers
5809/// that need to be added to the Machine PHI nodes as input. We cannot just
5810/// directly add them, because expansion might result in multiple MBB's for one
5811/// BB. As such, the start of the BB might correspond to a different MBB than
5812/// the end.
5813///
5814void
5815SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5816 TerminatorInst *TI = LLVMBB->getTerminator();
5817
5818 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5819
5820 // Check successor nodes' PHI nodes that expect a constant to be available
5821 // from this block.
5822 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5823 BasicBlock *SuccBB = TI->getSuccessor(succ);
5824 if (!isa<PHINode>(SuccBB->begin())) continue;
5825 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005826
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005827 // If this terminator has multiple identical successors (common for
5828 // switches), only handle each succ once.
5829 if (!SuccsHandled.insert(SuccMBB)) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005830
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005831 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5832 PHINode *PN;
5833
5834 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5835 // nodes and Machine PHI nodes, but the incoming operands have not been
5836 // emitted yet.
5837 for (BasicBlock::iterator I = SuccBB->begin();
5838 (PN = dyn_cast<PHINode>(I)); ++I) {
5839 // Ignore dead phi's.
5840 if (PN->use_empty()) continue;
5841
5842 unsigned Reg;
5843 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5844
5845 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5846 unsigned &RegOut = SDL->ConstantsOut[C];
5847 if (RegOut == 0) {
5848 RegOut = FuncInfo->CreateRegForValue(C);
5849 SDL->CopyValueToVirtualRegister(C, RegOut);
5850 }
5851 Reg = RegOut;
5852 } else {
5853 Reg = FuncInfo->ValueMap[PHIOp];
5854 if (Reg == 0) {
5855 assert(isa<AllocaInst>(PHIOp) &&
5856 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5857 "Didn't codegen value into a register!??");
5858 Reg = FuncInfo->CreateRegForValue(PHIOp);
5859 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5860 }
5861 }
5862
5863 // Remember that this register needs to added to the machine PHI node as
5864 // the input for this MBB.
5865 SmallVector<MVT, 4> ValueVTs;
5866 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5867 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5868 MVT VT = ValueVTs[vti];
5869 unsigned NumRegisters = TLI.getNumRegisters(VT);
5870 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5871 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5872 Reg += NumRegisters;
5873 }
5874 }
5875 }
5876 SDL->ConstantsOut.clear();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005877}
5878
Dan Gohman3df24e62008-09-03 23:12:08 +00005879/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5880/// supports legal types, and it emits MachineInstrs directly instead of
5881/// creating SelectionDAG nodes.
5882///
5883bool
5884SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5885 FastISel *F) {
5886 TerminatorInst *TI = LLVMBB->getTerminator();
Dan Gohmanf0cbcd42008-09-03 16:12:24 +00005887
Dan Gohman3df24e62008-09-03 23:12:08 +00005888 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5889 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5890
5891 // Check successor nodes' PHI nodes that expect a constant to be available
5892 // from this block.
5893 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5894 BasicBlock *SuccBB = TI->getSuccessor(succ);
5895 if (!isa<PHINode>(SuccBB->begin())) continue;
5896 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005897
Dan Gohman3df24e62008-09-03 23:12:08 +00005898 // If this terminator has multiple identical successors (common for
5899 // switches), only handle each succ once.
5900 if (!SuccsHandled.insert(SuccMBB)) continue;
Mikhail Glushenkov5c1799b2009-01-16 06:53:46 +00005901
Dan Gohman3df24e62008-09-03 23:12:08 +00005902 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5903 PHINode *PN;
5904
5905 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5906 // nodes and Machine PHI nodes, but the incoming operands have not been
5907 // emitted yet.
5908 for (BasicBlock::iterator I = SuccBB->begin();
5909 (PN = dyn_cast<PHINode>(I)); ++I) {
5910 // Ignore dead phi's.
5911 if (PN->use_empty()) continue;
5912
5913 // Only handle legal types. Two interesting things to note here. First,
5914 // by bailing out early, we may leave behind some dead instructions,
5915 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5916 // own moves. Second, this check is necessary becuase FastISel doesn't
5917 // use CreateRegForValue to create registers, so it always creates
5918 // exactly one register for each non-void instruction.
5919 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5920 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
Dan Gohman74321ab2008-09-10 21:01:31 +00005921 // Promote MVT::i1.
5922 if (VT == MVT::i1)
5923 VT = TLI.getTypeToTransformTo(VT);
5924 else {
5925 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5926 return false;
5927 }
Dan Gohman3df24e62008-09-03 23:12:08 +00005928 }
5929
5930 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5931
5932 unsigned Reg = F->getRegForValue(PHIOp);
5933 if (Reg == 0) {
5934 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5935 return false;
5936 }
5937 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
5938 }
5939 }
5940
5941 return true;
5942}