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Andrew Trick14e8d712010-10-22 23:09:15 +00001//===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// LiveIntervalUnion is a union of live segments across multiple live virtual
11// registers. This may be used during coalescing to represent a congruence
12// class, or during register allocation to model liveness of a physical
13// register.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_LIVEINTERVALUNION
18#define LLVM_CODEGEN_LIVEINTERVALUNION
19
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000020#include "llvm/ADT/IntervalMap.h"
Andrew Trick14e8d712010-10-22 23:09:15 +000021#include "llvm/CodeGen/LiveInterval.h"
Andrew Trick14e8d712010-10-22 23:09:15 +000022
23namespace llvm {
24
Jakob Stoklund Olesenff2e9b42010-12-17 04:09:47 +000025class MachineLoopRange;
Jakob Stoklund Olesen4a84cce2010-12-14 18:53:47 +000026class TargetRegisterInfo;
27
Andrew Trick071d1c02010-11-09 21:04:34 +000028#ifndef NDEBUG
29// forward declaration
30template <unsigned Element> class SparseBitVector;
Andrew Trick18c57a82010-11-30 23:18:47 +000031typedef SparseBitVector<128> LiveVirtRegBitSet;
Andrew Trick071d1c02010-11-09 21:04:34 +000032#endif
33
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000034/// Compare a live virtual register segment to a LiveIntervalUnion segment.
35inline bool
36overlap(const LiveRange &VRSeg,
37 const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
38 return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
39}
40
Andrew Trick14e8d712010-10-22 23:09:15 +000041/// Union of live intervals that are strong candidates for coalescing into a
42/// single register (either physical or virtual depending on the context). We
43/// expect the constituent live intervals to be disjoint, although we may
44/// eventually make exceptions to handle value-based interference.
45class LiveIntervalUnion {
46 // A set of live virtual register segments that supports fast insertion,
Andrew Trick18c57a82010-11-30 23:18:47 +000047 // intersection, and removal.
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000048 // Mapping SlotIndex intervals to virtual register numbers.
49 typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
Andrew Trick14e8d712010-10-22 23:09:15 +000050
Andrew Trick14e8d712010-10-22 23:09:15 +000051public:
52 // SegmentIter can advance to the next segment ordered by starting position
53 // which may belong to a different live virtual register. We also must be able
54 // to reach the current segment's containing virtual register.
55 typedef LiveSegments::iterator SegmentIter;
56
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000057 // LiveIntervalUnions share an external allocator.
58 typedef LiveSegments::Allocator Allocator;
59
Andrew Trick14e8d712010-10-22 23:09:15 +000060 class Query;
61
62private:
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000063 const unsigned RepReg; // representative register number
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +000064 unsigned Tag; // unique tag for current contents.
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000065 LiveSegments Segments; // union of virtual reg segments
Andrew Trick14e8d712010-10-22 23:09:15 +000066
67public:
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +000068 LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Tag(0), Segments(a)
69 {}
Andrew Trick14e8d712010-10-22 23:09:15 +000070
Andrew Tricke16eecc2010-10-26 18:34:01 +000071 // Iterate over all segments in the union of live virtual registers ordered
72 // by their starting position.
Andrew Trick18c57a82010-11-30 23:18:47 +000073 SegmentIter begin() { return Segments.begin(); }
74 SegmentIter end() { return Segments.end(); }
Jakob Stoklund Olesena35cce12010-12-09 01:06:52 +000075 SegmentIter find(SlotIndex x) { return Segments.find(x); }
Jakob Stoklund Olesenbfce6782010-12-14 19:38:49 +000076 bool empty() const { return Segments.empty(); }
77 SlotIndex startIndex() const { return Segments.start(); }
Andrew Trick14e8d712010-10-22 23:09:15 +000078
Jakob Stoklund Olesenff2e9b42010-12-17 04:09:47 +000079 // Provide public access to the underlying map to allow overlap iteration.
80 typedef LiveSegments Map;
81 const Map &getMap() { return Segments; }
82
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +000083 /// getTag - Return an opaque tag representing the current state of the union.
84 unsigned getTag() const { return Tag; }
85
86 /// changedSince - Return true if the union change since getTag returned tag.
87 bool changedSince(unsigned tag) const { return tag != Tag; }
88
Andrew Tricke16eecc2010-10-26 18:34:01 +000089 // Add a live virtual register to this union and merge its segments.
Andrew Trick18c57a82010-11-30 23:18:47 +000090 void unify(LiveInterval &VirtReg);
Andrew Trick14e8d712010-10-22 23:09:15 +000091
Andrew Tricke141a492010-11-08 18:02:08 +000092 // Remove a live virtual register's segments from this union.
Jakob Stoklund Olesen953af2c2010-12-07 23:18:47 +000093 void extract(LiveInterval &VirtReg);
Andrew Trick14e8d712010-10-22 23:09:15 +000094
Jakob Stoklund Olesen560ab9e2011-04-11 23:57:14 +000095 // Remove all inserted virtual registers.
96 void clear() { Segments.clear(); ++Tag; }
97
Jakob Stoklund Olesen4a84cce2010-12-14 18:53:47 +000098 // Print union, using TRI to translate register names
99 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
Andrew Trick18c57a82010-11-30 23:18:47 +0000100
Andrew Trick071d1c02010-11-09 21:04:34 +0000101#ifndef NDEBUG
102 // Verify the live intervals in this union and add them to the visited set.
Andrew Trick18c57a82010-11-30 23:18:47 +0000103 void verify(LiveVirtRegBitSet& VisitedVRegs);
Andrew Trick071d1c02010-11-09 21:04:34 +0000104#endif
105
Andrew Trick14e8d712010-10-22 23:09:15 +0000106 /// Query interferences between a single live virtual register and a live
107 /// interval union.
108 class Query {
Andrew Trick18c57a82010-11-30 23:18:47 +0000109 LiveIntervalUnion *LiveUnion;
110 LiveInterval *VirtReg;
Jakob Stoklund Olesenfe026e1822011-08-11 22:46:04 +0000111 LiveInterval::iterator VirtRegI; // current position in VirtReg
112 SegmentIter LiveUnionI; // current position in LiveUnion
Andrew Trick18c57a82010-11-30 23:18:47 +0000113 SmallVector<LiveInterval*,4> InterferingVRegs;
Jakob Stoklund Olesena35cce12010-12-09 01:06:52 +0000114 bool CheckedFirstInterference;
Andrew Trick18c57a82010-11-30 23:18:47 +0000115 bool SeenAllInterferences;
116 bool SeenUnspillableVReg;
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000117 unsigned Tag, UserTag;
Andrew Trick14e8d712010-10-22 23:09:15 +0000118
119 public:
Jakob Stoklund Olesen314a3ef2011-03-31 15:14:11 +0000120 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
Andrew Trick14e8d712010-10-22 23:09:15 +0000121
Andrew Trick18c57a82010-11-30 23:18:47 +0000122 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
Jakob Stoklund Olesena0382c62010-12-09 21:20:44 +0000123 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
124 SeenAllInterferences(false), SeenUnspillableVReg(false)
Andrew Trick18c57a82010-11-30 23:18:47 +0000125 {}
Andrew Tricke141a492010-11-08 18:02:08 +0000126
127 void clear() {
Andrew Trick18c57a82010-11-30 23:18:47 +0000128 LiveUnion = NULL;
129 VirtReg = NULL;
Andrew Trick18c57a82010-11-30 23:18:47 +0000130 InterferingVRegs.clear();
Jakob Stoklund Olesena35cce12010-12-09 01:06:52 +0000131 CheckedFirstInterference = false;
Andrew Trick18c57a82010-11-30 23:18:47 +0000132 SeenAllInterferences = false;
133 SeenUnspillableVReg = false;
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +0000134 Tag = 0;
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000135 UserTag = 0;
Andrew Tricke141a492010-11-08 18:02:08 +0000136 }
Andrew Trick18c57a82010-11-30 23:18:47 +0000137
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000138 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) {
Jakob Stoklund Olesena0382c62010-12-09 21:20:44 +0000139 assert(VReg && LIU && "Invalid arguments");
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000140 if (UserTag == UTag && VirtReg == VReg &&
141 LiveUnion == LIU && !LIU->changedSince(Tag)) {
Andrew Tricke141a492010-11-08 18:02:08 +0000142 // Retain cached results, e.g. firstInterference.
143 return;
144 }
Andrew Trick18c57a82010-11-30 23:18:47 +0000145 clear();
146 LiveUnion = LIU;
147 VirtReg = VReg;
Jakob Stoklund Olesen4f6364f2011-02-09 21:52:03 +0000148 Tag = LIU->getTag();
Jakob Stoklund Olesen29267332011-03-16 22:56:11 +0000149 UserTag = UTag;
Andrew Tricke141a492010-11-08 18:02:08 +0000150 }
151
Andrew Trick18c57a82010-11-30 23:18:47 +0000152 LiveInterval &virtReg() const {
153 assert(VirtReg && "uninitialized");
154 return *VirtReg;
155 }
Andrew Trick14e8d712010-10-22 23:09:15 +0000156
Andrew Trick18c57a82010-11-30 23:18:47 +0000157 // Does this live virtual register interfere with the union?
Jakob Stoklund Olesen9942ba92011-08-11 21:18:34 +0000158 bool checkInterference() { return collectInterferingVRegs(1); }
Andrew Trick14e8d712010-10-22 23:09:15 +0000159
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000160 // Count the virtual registers in this union that interfere with this
161 // query's live virtual register, up to maxInterferingRegs.
Jakob Stoklund Olesen51458ed2011-07-08 20:46:18 +0000162 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000163
164 // Was this virtual register visited during collectInterferingVRegs?
Andrew Trick18c57a82010-11-30 23:18:47 +0000165 bool isSeenInterference(LiveInterval *VReg) const;
166
167 // Did collectInterferingVRegs collect all interferences?
168 bool seenAllInterferences() const { return SeenAllInterferences; }
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000169
170 // Did collectInterferingVRegs encounter an unspillable vreg?
Andrew Trick18c57a82010-11-30 23:18:47 +0000171 bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000172
173 // Vector generated by collectInterferingVRegs.
174 const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
Andrew Trick18c57a82010-11-30 23:18:47 +0000175 return InterferingVRegs;
Andrew Trickf4baeaf2010-11-10 19:18:47 +0000176 }
Andrew Trick18c57a82010-11-30 23:18:47 +0000177
Jakob Stoklund Olesenff2e9b42010-12-17 04:09:47 +0000178 /// checkLoopInterference - Return true if there is interference overlapping
179 /// Loop.
180 bool checkLoopInterference(MachineLoopRange*);
181
Andrew Trick14e8d712010-10-22 23:09:15 +0000182 private:
Andrew Trick8a83d542010-11-11 17:46:29 +0000183 Query(const Query&); // DO NOT IMPLEMENT
184 void operator=(const Query&); // DO NOT IMPLEMENT
Andrew Trick14e8d712010-10-22 23:09:15 +0000185 };
186};
187
188} // end namespace llvm
189
190#endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)