Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 1 | ///===-- FastISel.cpp - Implementation of the FastISel class --------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the implementation of the FastISel class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 14 | #include "llvm/Instructions.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/FastISel.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetData.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 19 | #include "llvm/Target/TargetInstrInfo.h" |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetLowering.h" |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetMachine.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 22 | using namespace llvm; |
| 23 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 24 | unsigned FastISel::getRegForValue(Value *V) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 25 | // Look up the value to see if we already have a register for it. We |
| 26 | // cache values defined by Instructions across blocks, and other values |
| 27 | // only locally. This is because Instructions already have the SSA |
| 28 | // def-dominatess-use requirement enforced. |
Owen Anderson | 99aaf10 | 2008-09-03 17:37:03 +0000 | [diff] [blame] | 29 | if (ValueMap.count(V)) |
| 30 | return ValueMap[V]; |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 31 | unsigned Reg = LocalValueMap[V]; |
| 32 | if (Reg != 0) |
| 33 | return Reg; |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 34 | |
| 35 | MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT(); |
Dan Gohman | 8211648 | 2008-09-10 21:01:08 +0000 | [diff] [blame] | 36 | |
| 37 | // Ignore illegal types. |
| 38 | if (!TLI.isTypeLegal(VT)) { |
| 39 | // Promote MVT::i1 to a legal type though, because it's common and easy. |
| 40 | if (VT == MVT::i1) |
| 41 | VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); |
| 42 | else |
| 43 | return 0; |
| 44 | } |
| 45 | |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 46 | if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { |
Dan Gohman | 2ff7fd1 | 2008-09-19 22:16:54 +0000 | [diff] [blame^] | 47 | if (CI->getValue().getActiveBits() <= 64) |
| 48 | Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); |
Dan Gohman | 0586d91 | 2008-09-10 20:11:02 +0000 | [diff] [blame] | 49 | } else if (isa<AllocaInst>(V)) { |
Dan Gohman | 2ff7fd1 | 2008-09-19 22:16:54 +0000 | [diff] [blame^] | 50 | Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); |
Dan Gohman | 205d925 | 2008-08-28 21:19:07 +0000 | [diff] [blame] | 51 | } else if (isa<ConstantPointerNull>(V)) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 52 | Reg = FastEmit_i(VT, VT, ISD::Constant, 0); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 53 | } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 54 | Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 55 | |
| 56 | if (!Reg) { |
| 57 | const APFloat &Flt = CF->getValueAPF(); |
| 58 | MVT IntVT = TLI.getPointerTy(); |
| 59 | |
| 60 | uint64_t x[2]; |
| 61 | uint32_t IntBitWidth = IntVT.getSizeInBits(); |
Dan Gohman | 2ff7fd1 | 2008-09-19 22:16:54 +0000 | [diff] [blame^] | 62 | if (!Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, |
| 63 | APFloat::rmTowardZero) != APFloat::opOK) { |
| 64 | APInt IntVal(IntBitWidth, 2, x); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 65 | |
Dan Gohman | 2ff7fd1 | 2008-09-19 22:16:54 +0000 | [diff] [blame^] | 66 | unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), |
| 67 | ISD::Constant, IntVal.getZExtValue()); |
| 68 | if (IntegerReg != 0) |
| 69 | Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); |
| 70 | } |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 71 | } |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 72 | } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { |
| 73 | if (!SelectOperator(CE, CE->getOpcode())) return 0; |
| 74 | Reg = LocalValueMap[CE]; |
Dan Gohman | 205d925 | 2008-08-28 21:19:07 +0000 | [diff] [blame] | 75 | } else if (isa<UndefValue>(V)) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 76 | Reg = createResultReg(TLI.getRegClassFor(VT)); |
Dan Gohman | 205d925 | 2008-08-28 21:19:07 +0000 | [diff] [blame] | 77 | BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 78 | } else { |
| 79 | return 0; |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 80 | } |
Owen Anderson | d5d81a4 | 2008-09-03 17:51:57 +0000 | [diff] [blame] | 81 | |
Owen Anderson | 6e60745 | 2008-09-05 23:36:01 +0000 | [diff] [blame] | 82 | if (!Reg && isa<Constant>(V)) |
Dan Gohman | 2ff7fd1 | 2008-09-19 22:16:54 +0000 | [diff] [blame^] | 83 | Reg = TargetMaterializeConstant(cast<Constant>(V)); |
Owen Anderson | 6e60745 | 2008-09-05 23:36:01 +0000 | [diff] [blame] | 84 | |
Dan Gohman | 2ff7fd1 | 2008-09-19 22:16:54 +0000 | [diff] [blame^] | 85 | // Don't cache constant materializations in the general ValueMap. |
| 86 | // To do so would require tracking what uses they dominate. |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 87 | LocalValueMap[V] = Reg; |
| 88 | return Reg; |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 89 | } |
| 90 | |
Evan Cheng | 59fbc80 | 2008-09-09 01:26:59 +0000 | [diff] [blame] | 91 | unsigned FastISel::lookUpRegForValue(Value *V) { |
| 92 | // Look up the value to see if we already have a register for it. We |
| 93 | // cache values defined by Instructions across blocks, and other values |
| 94 | // only locally. This is because Instructions already have the SSA |
| 95 | // def-dominatess-use requirement enforced. |
| 96 | if (ValueMap.count(V)) |
| 97 | return ValueMap[V]; |
| 98 | return LocalValueMap[V]; |
| 99 | } |
| 100 | |
Owen Anderson | cc54e76 | 2008-08-30 00:38:46 +0000 | [diff] [blame] | 101 | /// UpdateValueMap - Update the value map to include the new mapping for this |
| 102 | /// instruction, or insert an extra copy to get the result in a previous |
| 103 | /// determined register. |
| 104 | /// NOTE: This is only necessary because we might select a block that uses |
| 105 | /// a value before we select the block that defines the value. It might be |
| 106 | /// possible to fix this by selecting blocks in reverse postorder. |
Owen Anderson | 95267a1 | 2008-09-05 00:06:23 +0000 | [diff] [blame] | 107 | void FastISel::UpdateValueMap(Value* I, unsigned Reg) { |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 108 | if (!isa<Instruction>(I)) { |
| 109 | LocalValueMap[I] = Reg; |
| 110 | return; |
| 111 | } |
Owen Anderson | cc54e76 | 2008-08-30 00:38:46 +0000 | [diff] [blame] | 112 | if (!ValueMap.count(I)) |
| 113 | ValueMap[I] = Reg; |
| 114 | else |
Evan Cheng | f099178 | 2008-09-07 09:04:52 +0000 | [diff] [blame] | 115 | TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I], |
| 116 | Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg)); |
Owen Anderson | cc54e76 | 2008-08-30 00:38:46 +0000 | [diff] [blame] | 117 | } |
| 118 | |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 119 | /// SelectBinaryOp - Select and emit code for a binary operator instruction, |
| 120 | /// which has an opcode which directly corresponds to the given ISD opcode. |
| 121 | /// |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 122 | bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 123 | MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); |
| 124 | if (VT == MVT::Other || !VT.isSimple()) |
| 125 | // Unhandled type. Halt "fast" selection and bail. |
| 126 | return false; |
Dan Gohman | 638c683 | 2008-09-05 18:44:22 +0000 | [diff] [blame] | 127 | |
Dan Gohman | b71fea2 | 2008-08-26 20:52:40 +0000 | [diff] [blame] | 128 | // We only handle legal types. For example, on x86-32 the instruction |
| 129 | // selector contains all of the 64-bit instructions from x86-64, |
| 130 | // under the assumption that i64 won't be used if the target doesn't |
| 131 | // support it. |
Dan Gohman | 638c683 | 2008-09-05 18:44:22 +0000 | [diff] [blame] | 132 | if (!TLI.isTypeLegal(VT)) { |
| 133 | // MVT::i1 is special. Allow AND and OR (but not XOR) because they |
| 134 | // don't require additional zeroing, which makes them easy. |
| 135 | if (VT == MVT::i1 && |
| 136 | (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR)) |
| 137 | VT = TLI.getTypeToTransformTo(VT); |
| 138 | else |
| 139 | return false; |
| 140 | } |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 141 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 142 | unsigned Op0 = getRegForValue(I->getOperand(0)); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 143 | if (Op0 == 0) |
| 144 | // Unhandled operand. Halt "fast" selection and bail. |
| 145 | return false; |
| 146 | |
| 147 | // Check if the second operand is a constant and handle it appropriately. |
| 148 | if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 149 | unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), |
| 150 | ISDOpcode, Op0, CI->getZExtValue()); |
| 151 | if (ResultReg != 0) { |
| 152 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 153 | UpdateValueMap(I, ResultReg); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 154 | return true; |
| 155 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 158 | // Check if the second operand is a constant float. |
| 159 | if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 160 | unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), |
| 161 | ISDOpcode, Op0, CF); |
| 162 | if (ResultReg != 0) { |
| 163 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 164 | UpdateValueMap(I, ResultReg); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 165 | return true; |
| 166 | } |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 167 | } |
| 168 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 169 | unsigned Op1 = getRegForValue(I->getOperand(1)); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 170 | if (Op1 == 0) |
| 171 | // Unhandled operand. Halt "fast" selection and bail. |
| 172 | return false; |
| 173 | |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 174 | // Now we have both operands in registers. Emit the instruction. |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 175 | unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), |
| 176 | ISDOpcode, Op0, Op1); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 177 | if (ResultReg == 0) |
| 178 | // Target-specific code wasn't able to find a machine opcode for |
| 179 | // the given ISD opcode and type. Halt "fast" selection and bail. |
| 180 | return false; |
| 181 | |
Dan Gohman | 8014e86 | 2008-08-20 00:23:20 +0000 | [diff] [blame] | 182 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 183 | UpdateValueMap(I, ResultReg); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 184 | return true; |
| 185 | } |
| 186 | |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 187 | bool FastISel::SelectGetElementPtr(User *I) { |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 188 | unsigned N = getRegForValue(I->getOperand(0)); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 189 | if (N == 0) |
| 190 | // Unhandled operand. Halt "fast" selection and bail. |
| 191 | return false; |
| 192 | |
| 193 | const Type *Ty = I->getOperand(0)->getType(); |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 194 | MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 195 | for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); |
| 196 | OI != E; ++OI) { |
| 197 | Value *Idx = *OI; |
| 198 | if (const StructType *StTy = dyn_cast<StructType>(Ty)) { |
| 199 | unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); |
| 200 | if (Field) { |
| 201 | // N = N + Offset |
| 202 | uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); |
| 203 | // FIXME: This can be optimized by combining the add with a |
| 204 | // subsequent one. |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 205 | N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 206 | if (N == 0) |
| 207 | // Unhandled operand. Halt "fast" selection and bail. |
| 208 | return false; |
| 209 | } |
| 210 | Ty = StTy->getElementType(Field); |
| 211 | } else { |
| 212 | Ty = cast<SequentialType>(Ty)->getElementType(); |
| 213 | |
| 214 | // If this is a constant subscript, handle it quickly. |
| 215 | if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { |
| 216 | if (CI->getZExtValue() == 0) continue; |
| 217 | uint64_t Offs = |
| 218 | TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 219 | N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 220 | if (N == 0) |
| 221 | // Unhandled operand. Halt "fast" selection and bail. |
| 222 | return false; |
| 223 | continue; |
| 224 | } |
| 225 | |
| 226 | // N = N + Idx * ElementSize; |
| 227 | uint64_t ElementSize = TD.getABITypeSize(Ty); |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 228 | unsigned IdxN = getRegForValue(Idx); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 229 | if (IdxN == 0) |
| 230 | // Unhandled operand. Halt "fast" selection and bail. |
| 231 | return false; |
| 232 | |
| 233 | // If the index is smaller or larger than intptr_t, truncate or extend |
| 234 | // it. |
Evan Cheng | 2076aa8 | 2008-08-21 01:19:11 +0000 | [diff] [blame] | 235 | MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 236 | if (IdxVT.bitsLT(VT)) |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 237 | IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 238 | else if (IdxVT.bitsGT(VT)) |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 239 | IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 240 | if (IdxN == 0) |
| 241 | // Unhandled operand. Halt "fast" selection and bail. |
| 242 | return false; |
| 243 | |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 244 | if (ElementSize != 1) { |
Dan Gohman | f93cf79 | 2008-08-21 17:37:05 +0000 | [diff] [blame] | 245 | IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 246 | if (IdxN == 0) |
| 247 | // Unhandled operand. Halt "fast" selection and bail. |
| 248 | return false; |
| 249 | } |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 250 | N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 251 | if (N == 0) |
| 252 | // Unhandled operand. Halt "fast" selection and bail. |
| 253 | return false; |
| 254 | } |
| 255 | } |
| 256 | |
| 257 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 258 | UpdateValueMap(I, N); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 259 | return true; |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 260 | } |
| 261 | |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 262 | bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { |
Owen Anderson | 6336b70 | 2008-08-27 18:58:30 +0000 | [diff] [blame] | 263 | MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); |
| 264 | MVT DstVT = TLI.getValueType(I->getType()); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 265 | |
| 266 | if (SrcVT == MVT::Other || !SrcVT.isSimple() || |
| 267 | DstVT == MVT::Other || !DstVT.isSimple() || |
| 268 | !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) |
| 269 | // Unhandled type. Halt "fast" selection and bail. |
| 270 | return false; |
| 271 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 272 | unsigned InputReg = getRegForValue(I->getOperand(0)); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 273 | if (!InputReg) |
| 274 | // Unhandled operand. Halt "fast" selection and bail. |
| 275 | return false; |
| 276 | |
| 277 | unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), |
| 278 | DstVT.getSimpleVT(), |
| 279 | Opcode, |
| 280 | InputReg); |
| 281 | if (!ResultReg) |
| 282 | return false; |
| 283 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 284 | UpdateValueMap(I, ResultReg); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 285 | return true; |
| 286 | } |
| 287 | |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 288 | bool FastISel::SelectBitCast(User *I) { |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 289 | // If the bitcast doesn't change the type, just use the operand value. |
| 290 | if (I->getType() == I->getOperand(0)->getType()) { |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 291 | unsigned Reg = getRegForValue(I->getOperand(0)); |
Dan Gohman | a318dab | 2008-08-27 20:41:38 +0000 | [diff] [blame] | 292 | if (Reg == 0) |
| 293 | return false; |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 294 | UpdateValueMap(I, Reg); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 295 | return true; |
| 296 | } |
| 297 | |
| 298 | // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. |
Owen Anderson | 6336b70 | 2008-08-27 18:58:30 +0000 | [diff] [blame] | 299 | MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); |
| 300 | MVT DstVT = TLI.getValueType(I->getType()); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 301 | |
| 302 | if (SrcVT == MVT::Other || !SrcVT.isSimple() || |
| 303 | DstVT == MVT::Other || !DstVT.isSimple() || |
| 304 | !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) |
| 305 | // Unhandled type. Halt "fast" selection and bail. |
| 306 | return false; |
| 307 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 308 | unsigned Op0 = getRegForValue(I->getOperand(0)); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 309 | if (Op0 == 0) |
| 310 | // Unhandled operand. Halt "fast" selection and bail. |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 311 | return false; |
| 312 | |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 313 | // First, try to perform the bitcast by inserting a reg-reg copy. |
| 314 | unsigned ResultReg = 0; |
| 315 | if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { |
| 316 | TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); |
| 317 | TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); |
| 318 | ResultReg = createResultReg(DstClass); |
| 319 | |
| 320 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 321 | Op0, DstClass, SrcClass); |
| 322 | if (!InsertedCopy) |
| 323 | ResultReg = 0; |
| 324 | } |
| 325 | |
| 326 | // If the reg-reg copy failed, select a BIT_CONVERT opcode. |
| 327 | if (!ResultReg) |
| 328 | ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), |
| 329 | ISD::BIT_CONVERT, Op0); |
| 330 | |
| 331 | if (!ResultReg) |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 332 | return false; |
| 333 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 334 | UpdateValueMap(I, ResultReg); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 335 | return true; |
| 336 | } |
| 337 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 338 | bool |
| 339 | FastISel::SelectInstruction(Instruction *I) { |
Dan Gohman | 40b189e | 2008-09-05 18:18:20 +0000 | [diff] [blame] | 340 | return SelectOperator(I, I->getOpcode()); |
| 341 | } |
| 342 | |
| 343 | bool |
| 344 | FastISel::SelectOperator(User *I, unsigned Opcode) { |
| 345 | switch (Opcode) { |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 346 | case Instruction::Add: { |
| 347 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; |
| 348 | return SelectBinaryOp(I, Opc); |
| 349 | } |
| 350 | case Instruction::Sub: { |
| 351 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; |
| 352 | return SelectBinaryOp(I, Opc); |
| 353 | } |
| 354 | case Instruction::Mul: { |
| 355 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; |
| 356 | return SelectBinaryOp(I, Opc); |
| 357 | } |
| 358 | case Instruction::SDiv: |
| 359 | return SelectBinaryOp(I, ISD::SDIV); |
| 360 | case Instruction::UDiv: |
| 361 | return SelectBinaryOp(I, ISD::UDIV); |
| 362 | case Instruction::FDiv: |
| 363 | return SelectBinaryOp(I, ISD::FDIV); |
| 364 | case Instruction::SRem: |
| 365 | return SelectBinaryOp(I, ISD::SREM); |
| 366 | case Instruction::URem: |
| 367 | return SelectBinaryOp(I, ISD::UREM); |
| 368 | case Instruction::FRem: |
| 369 | return SelectBinaryOp(I, ISD::FREM); |
| 370 | case Instruction::Shl: |
| 371 | return SelectBinaryOp(I, ISD::SHL); |
| 372 | case Instruction::LShr: |
| 373 | return SelectBinaryOp(I, ISD::SRL); |
| 374 | case Instruction::AShr: |
| 375 | return SelectBinaryOp(I, ISD::SRA); |
| 376 | case Instruction::And: |
| 377 | return SelectBinaryOp(I, ISD::AND); |
| 378 | case Instruction::Or: |
| 379 | return SelectBinaryOp(I, ISD::OR); |
| 380 | case Instruction::Xor: |
| 381 | return SelectBinaryOp(I, ISD::XOR); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 382 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 383 | case Instruction::GetElementPtr: |
| 384 | return SelectGetElementPtr(I); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 385 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 386 | case Instruction::Br: { |
| 387 | BranchInst *BI = cast<BranchInst>(I); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 388 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 389 | if (BI->isUnconditional()) { |
| 390 | MachineFunction::iterator NextMBB = |
| 391 | next(MachineFunction::iterator(MBB)); |
| 392 | BasicBlock *LLVMSucc = BI->getSuccessor(0); |
| 393 | MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 394 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 395 | if (NextMBB != MF.end() && MSucc == NextMBB) { |
| 396 | // The unconditional fall-through case, which needs no instructions. |
Owen Anderson | 9d5b416 | 2008-08-27 00:31:01 +0000 | [diff] [blame] | 397 | } else { |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 398 | // The unconditional branch case. |
| 399 | TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); |
Owen Anderson | 9d5b416 | 2008-08-27 00:31:01 +0000 | [diff] [blame] | 400 | } |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 401 | MBB->addSuccessor(MSucc); |
| 402 | return true; |
Owen Anderson | 9d5b416 | 2008-08-27 00:31:01 +0000 | [diff] [blame] | 403 | } |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 404 | |
| 405 | // Conditional branches are not handed yet. |
| 406 | // Halt "fast" selection and bail. |
| 407 | return false; |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 408 | } |
| 409 | |
Dan Gohman | 087c850 | 2008-09-05 01:08:41 +0000 | [diff] [blame] | 410 | case Instruction::Unreachable: |
| 411 | // Nothing to emit. |
| 412 | return true; |
| 413 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 414 | case Instruction::PHI: |
| 415 | // PHI nodes are already emitted. |
| 416 | return true; |
Dan Gohman | 0586d91 | 2008-09-10 20:11:02 +0000 | [diff] [blame] | 417 | |
| 418 | case Instruction::Alloca: |
| 419 | // FunctionLowering has the static-sized case covered. |
| 420 | if (StaticAllocaMap.count(cast<AllocaInst>(I))) |
| 421 | return true; |
| 422 | |
| 423 | // Dynamic-sized alloca is not handled yet. |
| 424 | return false; |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 425 | |
| 426 | case Instruction::BitCast: |
| 427 | return SelectBitCast(I); |
| 428 | |
| 429 | case Instruction::FPToSI: |
| 430 | return SelectCast(I, ISD::FP_TO_SINT); |
| 431 | case Instruction::ZExt: |
| 432 | return SelectCast(I, ISD::ZERO_EXTEND); |
| 433 | case Instruction::SExt: |
| 434 | return SelectCast(I, ISD::SIGN_EXTEND); |
| 435 | case Instruction::Trunc: |
| 436 | return SelectCast(I, ISD::TRUNCATE); |
| 437 | case Instruction::SIToFP: |
| 438 | return SelectCast(I, ISD::SINT_TO_FP); |
| 439 | |
| 440 | case Instruction::IntToPtr: // Deliberate fall-through. |
| 441 | case Instruction::PtrToInt: { |
| 442 | MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); |
| 443 | MVT DstVT = TLI.getValueType(I->getType()); |
| 444 | if (DstVT.bitsGT(SrcVT)) |
| 445 | return SelectCast(I, ISD::ZERO_EXTEND); |
| 446 | if (DstVT.bitsLT(SrcVT)) |
| 447 | return SelectCast(I, ISD::TRUNCATE); |
| 448 | unsigned Reg = getRegForValue(I->getOperand(0)); |
| 449 | if (Reg == 0) return false; |
| 450 | UpdateValueMap(I, Reg); |
| 451 | return true; |
| 452 | } |
| 453 | |
| 454 | default: |
| 455 | // Unhandled instruction. Halt "fast" selection and bail. |
| 456 | return false; |
| 457 | } |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 458 | } |
| 459 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 460 | FastISel::FastISel(MachineFunction &mf, |
| 461 | DenseMap<const Value *, unsigned> &vm, |
Dan Gohman | 0586d91 | 2008-09-10 20:11:02 +0000 | [diff] [blame] | 462 | DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, |
| 463 | DenseMap<const AllocaInst *, int> &am) |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 464 | : MBB(0), |
| 465 | ValueMap(vm), |
| 466 | MBBMap(bm), |
Dan Gohman | 0586d91 | 2008-09-10 20:11:02 +0000 | [diff] [blame] | 467 | StaticAllocaMap(am), |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 468 | MF(mf), |
| 469 | MRI(MF.getRegInfo()), |
Dan Gohman | 0586d91 | 2008-09-10 20:11:02 +0000 | [diff] [blame] | 470 | MFI(*MF.getFrameInfo()), |
| 471 | MCP(*MF.getConstantPool()), |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 472 | TM(MF.getTarget()), |
Dan Gohman | 22bb311 | 2008-08-22 00:20:26 +0000 | [diff] [blame] | 473 | TD(*TM.getTargetData()), |
| 474 | TII(*TM.getInstrInfo()), |
| 475 | TLI(*TM.getTargetLowering()) { |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 476 | } |
| 477 | |
Dan Gohman | e285a74 | 2008-08-14 21:51:29 +0000 | [diff] [blame] | 478 | FastISel::~FastISel() {} |
| 479 | |
Evan Cheng | 36fd941 | 2008-09-02 21:59:13 +0000 | [diff] [blame] | 480 | unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, |
| 481 | ISD::NodeType) { |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 482 | return 0; |
| 483 | } |
| 484 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 485 | unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, |
| 486 | ISD::NodeType, unsigned /*Op0*/) { |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 487 | return 0; |
| 488 | } |
| 489 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 490 | unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, |
| 491 | ISD::NodeType, unsigned /*Op0*/, |
| 492 | unsigned /*Op0*/) { |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 493 | return 0; |
| 494 | } |
| 495 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 496 | unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, |
| 497 | ISD::NodeType, uint64_t /*Imm*/) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 498 | return 0; |
| 499 | } |
| 500 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 501 | unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, |
| 502 | ISD::NodeType, ConstantFP * /*FPImm*/) { |
| 503 | return 0; |
| 504 | } |
| 505 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 506 | unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, |
| 507 | ISD::NodeType, unsigned /*Op0*/, |
| 508 | uint64_t /*Imm*/) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 509 | return 0; |
| 510 | } |
| 511 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 512 | unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, |
| 513 | ISD::NodeType, unsigned /*Op0*/, |
| 514 | ConstantFP * /*FPImm*/) { |
| 515 | return 0; |
| 516 | } |
| 517 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 518 | unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, |
| 519 | ISD::NodeType, |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 520 | unsigned /*Op0*/, unsigned /*Op1*/, |
| 521 | uint64_t /*Imm*/) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 522 | return 0; |
| 523 | } |
| 524 | |
| 525 | /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries |
| 526 | /// to emit an instruction with an immediate operand using FastEmit_ri. |
| 527 | /// If that fails, it materializes the immediate into a register and try |
| 528 | /// FastEmit_rr instead. |
| 529 | unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 530 | unsigned Op0, uint64_t Imm, |
| 531 | MVT::SimpleValueType ImmType) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 532 | // First check if immediate type is legal. If not, we can't use the ri form. |
Dan Gohman | 151ed61 | 2008-08-27 18:15:05 +0000 | [diff] [blame] | 533 | unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 534 | if (ResultReg != 0) |
| 535 | return ResultReg; |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 536 | unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 537 | if (MaterialReg == 0) |
| 538 | return 0; |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 539 | return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 540 | } |
| 541 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 542 | /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries |
| 543 | /// to emit an instruction with a floating-point immediate operand using |
| 544 | /// FastEmit_rf. If that fails, it materializes the immediate into a register |
| 545 | /// and try FastEmit_rr instead. |
| 546 | unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, |
| 547 | unsigned Op0, ConstantFP *FPImm, |
| 548 | MVT::SimpleValueType ImmType) { |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 549 | // First check if immediate type is legal. If not, we can't use the rf form. |
Dan Gohman | 151ed61 | 2008-08-27 18:15:05 +0000 | [diff] [blame] | 550 | unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 551 | if (ResultReg != 0) |
| 552 | return ResultReg; |
| 553 | |
| 554 | // Materialize the constant in a register. |
| 555 | unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); |
| 556 | if (MaterialReg == 0) { |
Dan Gohman | 96a9999 | 2008-08-27 18:01:42 +0000 | [diff] [blame] | 557 | // If the target doesn't have a way to directly enter a floating-point |
| 558 | // value into a register, use an alternate approach. |
| 559 | // TODO: The current approach only supports floating-point constants |
| 560 | // that can be constructed by conversion from integer values. This should |
| 561 | // be replaced by code that creates a load from a constant-pool entry, |
| 562 | // which will require some target-specific work. |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 563 | const APFloat &Flt = FPImm->getValueAPF(); |
| 564 | MVT IntVT = TLI.getPointerTy(); |
| 565 | |
| 566 | uint64_t x[2]; |
| 567 | uint32_t IntBitWidth = IntVT.getSizeInBits(); |
| 568 | if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, |
| 569 | APFloat::rmTowardZero) != APFloat::opOK) |
| 570 | return 0; |
| 571 | APInt IntVal(IntBitWidth, 2, x); |
| 572 | |
| 573 | unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), |
| 574 | ISD::Constant, IntVal.getZExtValue()); |
| 575 | if (IntegerReg == 0) |
| 576 | return 0; |
| 577 | MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, |
| 578 | ISD::SINT_TO_FP, IntegerReg); |
| 579 | if (MaterialReg == 0) |
| 580 | return 0; |
| 581 | } |
| 582 | return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); |
| 583 | } |
| 584 | |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 585 | unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { |
| 586 | return MRI.createVirtualRegister(RC); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 587 | } |
| 588 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 589 | unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, |
Dan Gohman | 77ad796 | 2008-08-20 18:09:38 +0000 | [diff] [blame] | 590 | const TargetRegisterClass* RC) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 591 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 592 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 593 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 594 | BuildMI(MBB, II, ResultReg); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 595 | return ResultReg; |
| 596 | } |
| 597 | |
| 598 | unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, |
| 599 | const TargetRegisterClass *RC, |
| 600 | unsigned Op0) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 601 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 602 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 603 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 604 | if (II.getNumDefs() >= 1) |
| 605 | BuildMI(MBB, II, ResultReg).addReg(Op0); |
| 606 | else { |
| 607 | BuildMI(MBB, II).addReg(Op0); |
| 608 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 609 | II.ImplicitDefs[0], RC, RC); |
| 610 | if (!InsertedCopy) |
| 611 | ResultReg = 0; |
| 612 | } |
| 613 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 614 | return ResultReg; |
| 615 | } |
| 616 | |
| 617 | unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, |
| 618 | const TargetRegisterClass *RC, |
| 619 | unsigned Op0, unsigned Op1) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 620 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 621 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 622 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 623 | if (II.getNumDefs() >= 1) |
| 624 | BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1); |
| 625 | else { |
| 626 | BuildMI(MBB, II).addReg(Op0).addReg(Op1); |
| 627 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 628 | II.ImplicitDefs[0], RC, RC); |
| 629 | if (!InsertedCopy) |
| 630 | ResultReg = 0; |
| 631 | } |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 632 | return ResultReg; |
| 633 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 634 | |
| 635 | unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, |
| 636 | const TargetRegisterClass *RC, |
| 637 | unsigned Op0, uint64_t Imm) { |
| 638 | unsigned ResultReg = createResultReg(RC); |
| 639 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 640 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 641 | if (II.getNumDefs() >= 1) |
| 642 | BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm); |
| 643 | else { |
| 644 | BuildMI(MBB, II).addReg(Op0).addImm(Imm); |
| 645 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 646 | II.ImplicitDefs[0], RC, RC); |
| 647 | if (!InsertedCopy) |
| 648 | ResultReg = 0; |
| 649 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 650 | return ResultReg; |
| 651 | } |
| 652 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 653 | unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, |
| 654 | const TargetRegisterClass *RC, |
| 655 | unsigned Op0, ConstantFP *FPImm) { |
| 656 | unsigned ResultReg = createResultReg(RC); |
| 657 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 658 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 659 | if (II.getNumDefs() >= 1) |
| 660 | BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm); |
| 661 | else { |
| 662 | BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm); |
| 663 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 664 | II.ImplicitDefs[0], RC, RC); |
| 665 | if (!InsertedCopy) |
| 666 | ResultReg = 0; |
| 667 | } |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 668 | return ResultReg; |
| 669 | } |
| 670 | |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 671 | unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, |
| 672 | const TargetRegisterClass *RC, |
| 673 | unsigned Op0, unsigned Op1, uint64_t Imm) { |
| 674 | unsigned ResultReg = createResultReg(RC); |
| 675 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 676 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 677 | if (II.getNumDefs() >= 1) |
| 678 | BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); |
| 679 | else { |
| 680 | BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm); |
| 681 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 682 | II.ImplicitDefs[0], RC, RC); |
| 683 | if (!InsertedCopy) |
| 684 | ResultReg = 0; |
| 685 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 686 | return ResultReg; |
| 687 | } |
Owen Anderson | 6d0c25e | 2008-08-25 20:20:32 +0000 | [diff] [blame] | 688 | |
| 689 | unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, |
| 690 | const TargetRegisterClass *RC, |
| 691 | uint64_t Imm) { |
| 692 | unsigned ResultReg = createResultReg(RC); |
| 693 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 694 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 695 | if (II.getNumDefs() >= 1) |
| 696 | BuildMI(MBB, II, ResultReg).addImm(Imm); |
| 697 | else { |
| 698 | BuildMI(MBB, II).addImm(Imm); |
| 699 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 700 | II.ImplicitDefs[0], RC, RC); |
| 701 | if (!InsertedCopy) |
| 702 | ResultReg = 0; |
| 703 | } |
Owen Anderson | 6d0c25e | 2008-08-25 20:20:32 +0000 | [diff] [blame] | 704 | return ResultReg; |
Evan Cheng | b41aec5 | 2008-08-25 22:20:39 +0000 | [diff] [blame] | 705 | } |
Owen Anderson | 8970f00 | 2008-08-27 22:30:02 +0000 | [diff] [blame] | 706 | |
Owen Anderson | 40a468f | 2008-08-28 17:47:37 +0000 | [diff] [blame] | 707 | unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) { |
| 708 | const TargetRegisterClass* RC = MRI.getRegClass(Op0); |
Owen Anderson | 8970f00 | 2008-08-27 22:30:02 +0000 | [diff] [blame] | 709 | const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1); |
| 710 | |
| 711 | unsigned ResultReg = createResultReg(SRC); |
| 712 | const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); |
| 713 | |
Evan Cheng | 5960e4e | 2008-09-08 08:38:20 +0000 | [diff] [blame] | 714 | if (II.getNumDefs() >= 1) |
| 715 | BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx); |
| 716 | else { |
| 717 | BuildMI(MBB, II).addReg(Op0).addImm(Idx); |
| 718 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 719 | II.ImplicitDefs[0], RC, RC); |
| 720 | if (!InsertedCopy) |
| 721 | ResultReg = 0; |
| 722 | } |
Owen Anderson | 8970f00 | 2008-08-27 22:30:02 +0000 | [diff] [blame] | 723 | return ResultReg; |
| 724 | } |