Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 301aaf5364b0e64e779165ec12b217c546a1506e / . / lib / Target / X86 / X86.td
blob: 6d08b36be44d8b802739dffecedef89e2112d00e [file] [log] [blame]
Arnold Schwaighofer373e8652007-10-12 21:30:57 +0000[diff] [blame]1//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, refered to
11// here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
Evan Cheng301aaf52008-11-24 07:34:46 +0000[diff] [blame^]17include "llvm/Target/Target.td"
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget features.
21//===----------------------------------------------------------------------===//
22
23def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
24 "Enable MMX instructions">;
25def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
26 "Enable SSE instructions",
27 [FeatureMMX]>;
28def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
29 "Enable SSE2 instructions",
30 [FeatureSSE1]>;
31def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
32 "Enable SSE3 instructions",
33 [FeatureSSE2]>;
34def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
35 "Enable SSSE3 instructions",
36 [FeatureSSE3]>;
Nate Begemanb2975562008-02-03 07:18:54 +0000[diff] [blame]37def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
38 "Enable SSE 4.1 instructions",
39 [FeatureSSSE3]>;
40def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
41 "Enable SSE 4.2 instructions",
42 [FeatureSSE41]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]43def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
44 "Enable 3DNow! instructions">;
45def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
46 "Enable 3DNow! Athlon instructions",
47 [Feature3DNow]>;
48def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
49 "Support 64-bit instructions",
50 [FeatureSSE2]>;
51
52//===----------------------------------------------------------------------===//
53// X86 processors supported.
54//===----------------------------------------------------------------------===//
55
56class Proc<string Name, list<SubtargetFeature> Features>
57 : Processor<Name, NoItineraries, Features>;
58
59def : Proc<"generic", []>;
60def : Proc<"i386", []>;
61def : Proc<"i486", []>;
Dale Johannesen68a99ca2008-10-14 22:06:33 +0000[diff] [blame]62def : Proc<"i586", []>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]63def : Proc<"pentium", []>;
64def : Proc<"pentium-mmx", [FeatureMMX]>;
65def : Proc<"i686", []>;
66def : Proc<"pentiumpro", []>;
67def : Proc<"pentium2", [FeatureMMX]>;
68def : Proc<"pentium3", [FeatureSSE1]>;
69def : Proc<"pentium-m", [FeatureSSE2]>;
70def : Proc<"pentium4", [FeatureSSE2]>;
71def : Proc<"x86-64", [Feature64Bit]>;
72def : Proc<"yonah", [FeatureSSE3]>;
73def : Proc<"prescott", [FeatureSSE3]>;
Dale Johannesena5b0c082008-02-15 01:22:41 +0000[diff] [blame]74def : Proc<"nocona", [FeatureSSE3, Feature64Bit]>;
75def : Proc<"core2", [FeatureSSSE3, Feature64Bit]>;
76def : Proc<"penryn", [FeatureSSE41, Feature64Bit]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]77
78def : Proc<"k6", [FeatureMMX]>;
79def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
80def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
81def : Proc<"athlon", [FeatureMMX, Feature3DNowA]>;
82def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA]>;
83def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA]>;
84def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA]>;
85def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA]>;
86def : Proc<"k8", [Feature3DNowA, Feature64Bit]>;
87def : Proc<"opteron", [Feature3DNowA, Feature64Bit]>;
88def : Proc<"athlon64", [Feature3DNowA, Feature64Bit]>;
89def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit]>;
90
91def : Proc<"winchip-c6", [FeatureMMX]>;
92def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
93def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
94def : Proc<"c3-2", [FeatureSSE1]>;
95
96//===----------------------------------------------------------------------===//
97// Register File Description
98//===----------------------------------------------------------------------===//
99
100include "X86RegisterInfo.td"
101
102//===----------------------------------------------------------------------===//
103// Instruction Descriptions
104//===----------------------------------------------------------------------===//
105
106include "X86InstrInfo.td"
107
108def X86InstrInfo : InstrInfo {
109
110 // Define how we want to layout our TargetSpecific information field... This
111 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
112 let TSFlagsFields = ["FormBits",
113 "hasOpSizePrefix",
114 "hasAdSizePrefix",
115 "Prefix",
116 "hasREX_WPrefix",
117 "ImmTypeBits",
118 "FPFormBits",
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +0000[diff] [blame]119 "hasLockPrefix",
Anton Korobeynikov975e1472008-10-11 19:09:15 +0000[diff] [blame]120 "SegOvrBits",
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]121 "Opcode"];
122 let TSFlagsShifts = [0,
123 6,
124 7,
125 8,
126 12,
127 13,
128 16,
Andrew Lenharth7a5a4b22008-03-01 13:37:02 +0000[diff] [blame]129 19,
Anton Korobeynikov975e1472008-10-11 19:09:15 +0000[diff] [blame]130 20,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]131 24];
132}
133
134//===----------------------------------------------------------------------===//
135// Calling Conventions
136//===----------------------------------------------------------------------===//
137
138include "X86CallingConv.td"
139
140
141//===----------------------------------------------------------------------===//
142// Assembly Printers
143//===----------------------------------------------------------------------===//
144
145// The X86 target supports two different syntaxes for emitting machine code.
146// This is controlled by the -x86-asm-syntax={att|intel}
147def ATTAsmWriter : AsmWriter {
148 string AsmWriterClassName = "ATTAsmPrinter";
149 int Variant = 0;
150}
151def IntelAsmWriter : AsmWriter {
152 string AsmWriterClassName = "IntelAsmPrinter";
153 int Variant = 1;
154}
155
156
157def X86 : Target {
158 // Information about the instructions...
159 let InstructionSet = X86InstrInfo;
160
161 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
162}