Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 1 | //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the base ARM implementation of TargetRegisterInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARM.h" |
| 15 | #include "ARMAddressingModes.h" |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 16 | #include "ARMBaseInstrInfo.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 17 | #include "ARMBaseRegisterInfo.h" |
| 18 | #include "ARMInstrInfo.h" |
| 19 | #include "ARMMachineFunctionInfo.h" |
| 20 | #include "ARMSubtarget.h" |
| 21 | #include "llvm/Constants.h" |
| 22 | #include "llvm/DerivedTypes.h" |
Owen Anderson | 9adc0ab | 2009-07-14 23:09:55 +0000 | [diff] [blame] | 23 | #include "llvm/Function.h" |
| 24 | #include "llvm/LLVMContext.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineConstantPool.h" |
| 26 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 27 | #include "llvm/CodeGen/MachineFunction.h" |
| 28 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 29 | #include "llvm/CodeGen/MachineLocation.h" |
| 30 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 31 | #include "llvm/CodeGen/RegisterScavenging.h" |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 32 | #include "llvm/Support/Debug.h" |
Torok Edwin | ab7c09b | 2009-07-08 18:01:40 +0000 | [diff] [blame] | 33 | #include "llvm/Support/ErrorHandling.h" |
Torok Edwin | dac237e | 2009-07-08 20:53:28 +0000 | [diff] [blame] | 34 | #include "llvm/Support/raw_ostream.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 35 | #include "llvm/Target/TargetFrameInfo.h" |
| 36 | #include "llvm/Target/TargetMachine.h" |
| 37 | #include "llvm/Target/TargetOptions.h" |
| 38 | #include "llvm/ADT/BitVector.h" |
| 39 | #include "llvm/ADT/SmallVector.h" |
Jim Grosbach | 18ed9c9 | 2009-10-20 20:19:50 +0000 | [diff] [blame] | 40 | #include "llvm/Support/CommandLine.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 41 | |
Dan Gohman | 8c407d4 | 2010-04-15 17:34:58 +0000 | [diff] [blame] | 42 | namespace llvm { |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 43 | static cl::opt<bool> |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 44 | ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 45 | cl::desc("Force use of virtual base registers for stack load/store")); |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 46 | static cl::opt<bool> |
Jim Grosbach | ae47c6d | 2010-08-26 00:58:06 +0000 | [diff] [blame] | 47 | EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 48 | cl::desc("Enable pre-regalloc stack frame index allocation")); |
Dan Gohman | 8c407d4 | 2010-04-15 17:34:58 +0000 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | using namespace llvm; |
Jim Grosbach | 18ed9c9 | 2009-10-20 20:19:50 +0000 | [diff] [blame] | 52 | |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 53 | static cl::opt<bool> |
Jim Grosbach | e1e6d18 | 2010-09-08 02:00:34 +0000 | [diff] [blame] | 54 | EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(false), |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 55 | cl::desc("Enable use of a base pointer for complex stack frames")); |
| 56 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 57 | unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 58 | bool *isSPVFP) { |
| 59 | if (isSPVFP) |
| 60 | *isSPVFP = false; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 61 | |
| 62 | using namespace ARM; |
| 63 | switch (RegEnum) { |
| 64 | default: |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 65 | llvm_unreachable("Unknown ARM register!"); |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 66 | case R0: case D0: case Q0: return 0; |
| 67 | case R1: case D1: case Q1: return 1; |
| 68 | case R2: case D2: case Q2: return 2; |
| 69 | case R3: case D3: case Q3: return 3; |
| 70 | case R4: case D4: case Q4: return 4; |
| 71 | case R5: case D5: case Q5: return 5; |
| 72 | case R6: case D6: case Q6: return 6; |
| 73 | case R7: case D7: case Q7: return 7; |
| 74 | case R8: case D8: case Q8: return 8; |
| 75 | case R9: case D9: case Q9: return 9; |
| 76 | case R10: case D10: case Q10: return 10; |
| 77 | case R11: case D11: case Q11: return 11; |
| 78 | case R12: case D12: case Q12: return 12; |
| 79 | case SP: case D13: case Q13: return 13; |
| 80 | case LR: case D14: case Q14: return 14; |
| 81 | case PC: case D15: case Q15: return 15; |
| 82 | |
| 83 | case D16: return 16; |
| 84 | case D17: return 17; |
| 85 | case D18: return 18; |
| 86 | case D19: return 19; |
| 87 | case D20: return 20; |
| 88 | case D21: return 21; |
| 89 | case D22: return 22; |
| 90 | case D23: return 23; |
| 91 | case D24: return 24; |
| 92 | case D25: return 25; |
Bob Wilson | 98330ff | 2010-03-20 06:05:13 +0000 | [diff] [blame] | 93 | case D26: return 26; |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 94 | case D27: return 27; |
| 95 | case D28: return 28; |
| 96 | case D29: return 29; |
| 97 | case D30: return 30; |
| 98 | case D31: return 31; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 99 | |
| 100 | case S0: case S1: case S2: case S3: |
| 101 | case S4: case S5: case S6: case S7: |
| 102 | case S8: case S9: case S10: case S11: |
| 103 | case S12: case S13: case S14: case S15: |
| 104 | case S16: case S17: case S18: case S19: |
| 105 | case S20: case S21: case S22: case S23: |
| 106 | case S24: case S25: case S26: case S27: |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 107 | case S28: case S29: case S30: case S31: { |
| 108 | if (isSPVFP) |
| 109 | *isSPVFP = true; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 110 | switch (RegEnum) { |
| 111 | default: return 0; // Avoid compile time warning. |
| 112 | case S0: return 0; |
| 113 | case S1: return 1; |
| 114 | case S2: return 2; |
| 115 | case S3: return 3; |
| 116 | case S4: return 4; |
| 117 | case S5: return 5; |
| 118 | case S6: return 6; |
| 119 | case S7: return 7; |
| 120 | case S8: return 8; |
| 121 | case S9: return 9; |
| 122 | case S10: return 10; |
| 123 | case S11: return 11; |
| 124 | case S12: return 12; |
| 125 | case S13: return 13; |
| 126 | case S14: return 14; |
| 127 | case S15: return 15; |
| 128 | case S16: return 16; |
| 129 | case S17: return 17; |
| 130 | case S18: return 18; |
| 131 | case S19: return 19; |
| 132 | case S20: return 20; |
| 133 | case S21: return 21; |
| 134 | case S22: return 22; |
| 135 | case S23: return 23; |
| 136 | case S24: return 24; |
| 137 | case S25: return 25; |
| 138 | case S26: return 26; |
| 139 | case S27: return 27; |
| 140 | case S28: return 28; |
| 141 | case S29: return 29; |
| 142 | case S30: return 30; |
| 143 | case S31: return 31; |
| 144 | } |
| 145 | } |
| 146 | } |
| 147 | } |
| 148 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 149 | ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 150 | const ARMSubtarget &sti) |
| 151 | : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), |
| 152 | TII(tii), STI(sti), |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 153 | FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), |
| 154 | BasePtr(ARM::R6) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | const unsigned* |
| 158 | ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
| 159 | static const unsigned CalleeSavedRegs[] = { |
| 160 | ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, |
| 161 | ARM::R7, ARM::R6, ARM::R5, ARM::R4, |
| 162 | |
| 163 | ARM::D15, ARM::D14, ARM::D13, ARM::D12, |
| 164 | ARM::D11, ARM::D10, ARM::D9, ARM::D8, |
| 165 | 0 |
| 166 | }; |
| 167 | |
| 168 | static const unsigned DarwinCalleeSavedRegs[] = { |
| 169 | // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved |
| 170 | // register. |
| 171 | ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, |
| 172 | ARM::R11, ARM::R10, ARM::R8, |
| 173 | |
| 174 | ARM::D15, ARM::D14, ARM::D13, ARM::D12, |
| 175 | ARM::D11, ARM::D10, ARM::D9, ARM::D8, |
| 176 | 0 |
| 177 | }; |
| 178 | return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; |
| 179 | } |
| 180 | |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 181 | BitVector ARMBaseRegisterInfo:: |
| 182 | getReservedRegs(const MachineFunction &MF) const { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 183 | // FIXME: avoid re-calculating this everytime. |
| 184 | BitVector Reserved(getNumRegs()); |
| 185 | Reserved.set(ARM::SP); |
| 186 | Reserved.set(ARM::PC); |
Nate Begeman | d1fb583 | 2010-08-03 21:31:55 +0000 | [diff] [blame] | 187 | Reserved.set(ARM::FPSCR); |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 188 | if (hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 189 | Reserved.set(FramePtr); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 190 | if (hasBasePointer(MF)) |
| 191 | Reserved.set(BasePtr); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 192 | // Some targets reserve R9. |
| 193 | if (STI.isR9Reserved()) |
| 194 | Reserved.set(ARM::R9); |
| 195 | return Reserved; |
| 196 | } |
| 197 | |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 198 | bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, |
| 199 | unsigned Reg) const { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 200 | switch (Reg) { |
| 201 | default: break; |
| 202 | case ARM::SP: |
| 203 | case ARM::PC: |
| 204 | return true; |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 205 | case ARM::R6: |
| 206 | if (hasBasePointer(MF)) |
| 207 | return true; |
| 208 | break; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 209 | case ARM::R7: |
| 210 | case ARM::R11: |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 211 | if (FramePtr == Reg && hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 212 | return true; |
| 213 | break; |
| 214 | case ARM::R9: |
| 215 | return STI.isR9Reserved(); |
| 216 | } |
| 217 | |
| 218 | return false; |
| 219 | } |
| 220 | |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 221 | const TargetRegisterClass * |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 222 | ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, |
| 223 | const TargetRegisterClass *B, |
| 224 | unsigned SubIdx) const { |
| 225 | switch (SubIdx) { |
| 226 | default: return 0; |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 227 | case ARM::ssub_0: |
| 228 | case ARM::ssub_1: |
| 229 | case ARM::ssub_2: |
| 230 | case ARM::ssub_3: { |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 231 | // S sub-registers. |
| 232 | if (A->getSize() == 8) { |
Evan Cheng | ba90864 | 2009-11-03 05:52:54 +0000 | [diff] [blame] | 233 | if (B == &ARM::SPR_8RegClass) |
| 234 | return &ARM::DPR_8RegClass; |
| 235 | assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 236 | if (A == &ARM::DPR_8RegClass) |
| 237 | return A; |
| 238 | return &ARM::DPR_VFP2RegClass; |
| 239 | } |
| 240 | |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 241 | if (A->getSize() == 16) { |
| 242 | if (B == &ARM::SPR_8RegClass) |
| 243 | return &ARM::QPR_8RegClass; |
| 244 | return &ARM::QPR_VFP2RegClass; |
| 245 | } |
| 246 | |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 247 | if (A->getSize() == 32) { |
| 248 | if (B == &ARM::SPR_8RegClass) |
| 249 | return 0; // Do not allow coalescing! |
| 250 | return &ARM::QQPR_VFP2RegClass; |
| 251 | } |
| 252 | |
| 253 | assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); |
| 254 | return 0; // Do not allow coalescing! |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 255 | } |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 256 | case ARM::dsub_0: |
| 257 | case ARM::dsub_1: |
| 258 | case ARM::dsub_2: |
| 259 | case ARM::dsub_3: { |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 260 | // D sub-registers. |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 261 | if (A->getSize() == 16) { |
| 262 | if (B == &ARM::DPR_VFP2RegClass) |
| 263 | return &ARM::QPR_VFP2RegClass; |
| 264 | if (B == &ARM::DPR_8RegClass) |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 265 | return 0; // Do not allow coalescing! |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 266 | return A; |
| 267 | } |
| 268 | |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 269 | if (A->getSize() == 32) { |
| 270 | if (B == &ARM::DPR_VFP2RegClass) |
| 271 | return &ARM::QQPR_VFP2RegClass; |
| 272 | if (B == &ARM::DPR_8RegClass) |
| 273 | return 0; // Do not allow coalescing! |
| 274 | return A; |
| 275 | } |
| 276 | |
| 277 | assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); |
| 278 | if (B != &ARM::DPRRegClass) |
| 279 | return 0; // Do not allow coalescing! |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 280 | return A; |
| 281 | } |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 282 | case ARM::dsub_4: |
| 283 | case ARM::dsub_5: |
| 284 | case ARM::dsub_6: |
| 285 | case ARM::dsub_7: { |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 286 | // D sub-registers of QQQQ registers. |
| 287 | if (A->getSize() == 64 && B == &ARM::DPRRegClass) |
| 288 | return A; |
| 289 | return 0; // Do not allow coalescing! |
| 290 | } |
| 291 | |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 292 | case ARM::qsub_0: |
| 293 | case ARM::qsub_1: { |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 294 | // Q sub-registers. |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 295 | if (A->getSize() == 32) { |
| 296 | if (B == &ARM::QPR_VFP2RegClass) |
| 297 | return &ARM::QQPR_VFP2RegClass; |
| 298 | if (B == &ARM::QPR_8RegClass) |
| 299 | return 0; // Do not allow coalescing! |
| 300 | return A; |
| 301 | } |
| 302 | |
| 303 | assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); |
| 304 | if (B == &ARM::QPRRegClass) |
| 305 | return A; |
| 306 | return 0; // Do not allow coalescing! |
| 307 | } |
Jakob Stoklund Olesen | e00fa64 | 2010-05-25 00:15:15 +0000 | [diff] [blame] | 308 | case ARM::qsub_2: |
| 309 | case ARM::qsub_3: { |
Evan Cheng | 22c687b | 2010-05-14 02:13:41 +0000 | [diff] [blame] | 310 | // Q sub-registers of QQQQ registers. |
| 311 | if (A->getSize() == 64 && B == &ARM::QPRRegClass) |
| 312 | return A; |
| 313 | return 0; // Do not allow coalescing! |
Evan Cheng | b63387a | 2010-05-06 06:36:08 +0000 | [diff] [blame] | 314 | } |
| 315 | } |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 316 | return 0; |
| 317 | } |
| 318 | |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 319 | bool |
Bob Wilson | 91a74da | 2010-06-02 18:54:47 +0000 | [diff] [blame] | 320 | ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 321 | SmallVectorImpl<unsigned> &SubIndices, |
| 322 | unsigned &NewSubIdx) const { |
| 323 | |
| 324 | unsigned Size = RC->getSize() * 8; |
| 325 | if (Size < 6) |
| 326 | return 0; |
| 327 | |
| 328 | NewSubIdx = 0; // Whole register. |
| 329 | unsigned NumRegs = SubIndices.size(); |
| 330 | if (NumRegs == 8) { |
| 331 | // 8 D registers -> 1 QQQQ register. |
| 332 | return (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 333 | SubIndices[0] == ARM::dsub_0 && |
| 334 | SubIndices[1] == ARM::dsub_1 && |
| 335 | SubIndices[2] == ARM::dsub_2 && |
| 336 | SubIndices[3] == ARM::dsub_3 && |
| 337 | SubIndices[4] == ARM::dsub_4 && |
| 338 | SubIndices[5] == ARM::dsub_5 && |
| 339 | SubIndices[6] == ARM::dsub_6 && |
| 340 | SubIndices[7] == ARM::dsub_7); |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 341 | } else if (NumRegs == 4) { |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 342 | if (SubIndices[0] == ARM::qsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 343 | // 4 Q registers -> 1 QQQQ register. |
| 344 | return (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 345 | SubIndices[1] == ARM::qsub_1 && |
| 346 | SubIndices[2] == ARM::qsub_2 && |
| 347 | SubIndices[3] == ARM::qsub_3); |
| 348 | } else if (SubIndices[0] == ARM::dsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 349 | // 4 D registers -> 1 QQ register. |
| 350 | if (Size >= 256 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 351 | SubIndices[1] == ARM::dsub_1 && |
| 352 | SubIndices[2] == ARM::dsub_2 && |
| 353 | SubIndices[3] == ARM::dsub_3) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 354 | if (Size == 512) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 355 | NewSubIdx = ARM::qqsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 356 | return true; |
| 357 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 358 | } else if (SubIndices[0] == ARM::dsub_4) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 359 | // 4 D registers -> 1 QQ register (2nd). |
| 360 | if (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 361 | SubIndices[1] == ARM::dsub_5 && |
| 362 | SubIndices[2] == ARM::dsub_6 && |
| 363 | SubIndices[3] == ARM::dsub_7) { |
| 364 | NewSubIdx = ARM::qqsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 365 | return true; |
| 366 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 367 | } else if (SubIndices[0] == ARM::ssub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 368 | // 4 S registers -> 1 Q register. |
| 369 | if (Size >= 128 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 370 | SubIndices[1] == ARM::ssub_1 && |
| 371 | SubIndices[2] == ARM::ssub_2 && |
| 372 | SubIndices[3] == ARM::ssub_3) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 373 | if (Size >= 256) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 374 | NewSubIdx = ARM::qsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 375 | return true; |
| 376 | } |
| 377 | } |
| 378 | } else if (NumRegs == 2) { |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 379 | if (SubIndices[0] == ARM::qsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 380 | // 2 Q registers -> 1 QQ register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 381 | if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 382 | if (Size == 512) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 383 | NewSubIdx = ARM::qqsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 384 | return true; |
| 385 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 386 | } else if (SubIndices[0] == ARM::qsub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 387 | // 2 Q registers -> 1 QQ register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 388 | if (Size == 512 && SubIndices[1] == ARM::qsub_3) { |
| 389 | NewSubIdx = ARM::qqsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 390 | return true; |
| 391 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 392 | } else if (SubIndices[0] == ARM::dsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 393 | // 2 D registers -> 1 Q register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 394 | if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 395 | if (Size >= 256) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 396 | NewSubIdx = ARM::qsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 397 | return true; |
| 398 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 399 | } else if (SubIndices[0] == ARM::dsub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 400 | // 2 D registers -> 1 Q register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 401 | if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { |
| 402 | NewSubIdx = ARM::qsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 403 | return true; |
| 404 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 405 | } else if (SubIndices[0] == ARM::dsub_4) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 406 | // 2 D registers -> 1 Q register (3rd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 407 | if (Size == 512 && SubIndices[1] == ARM::dsub_5) { |
| 408 | NewSubIdx = ARM::qsub_2; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 409 | return true; |
| 410 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 411 | } else if (SubIndices[0] == ARM::dsub_6) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 412 | // 2 D registers -> 1 Q register (3rd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 413 | if (Size == 512 && SubIndices[1] == ARM::dsub_7) { |
| 414 | NewSubIdx = ARM::qsub_3; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 415 | return true; |
| 416 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 417 | } else if (SubIndices[0] == ARM::ssub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 418 | // 2 S registers -> 1 D register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 419 | if (SubIndices[1] == ARM::ssub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 420 | if (Size >= 128) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 421 | NewSubIdx = ARM::dsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 422 | return true; |
| 423 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 424 | } else if (SubIndices[0] == ARM::ssub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 425 | // 2 S registers -> 1 D register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 426 | if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { |
| 427 | NewSubIdx = ARM::dsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 428 | return true; |
| 429 | } |
| 430 | } |
| 431 | } |
| 432 | return false; |
| 433 | } |
| 434 | |
| 435 | |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 436 | const TargetRegisterClass * |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 437 | ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { |
Jim Grosbach | e11a8f5 | 2009-09-11 19:49:06 +0000 | [diff] [blame] | 438 | return ARM::GPRRegisterClass; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | /// getAllocationOrder - Returns the register allocation order for a specified |
| 442 | /// register class in the form of a pair of TargetRegisterClass iterators. |
| 443 | std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> |
| 444 | ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, |
| 445 | unsigned HintType, unsigned HintReg, |
| 446 | const MachineFunction &MF) const { |
| 447 | // Alternative register allocation orders when favoring even / odd registers |
| 448 | // of register pairs. |
| 449 | |
| 450 | // No FP, R9 is available. |
| 451 | static const unsigned GPREven1[] = { |
| 452 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, |
| 453 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 454 | ARM::R9, ARM::R11 |
| 455 | }; |
| 456 | static const unsigned GPROdd1[] = { |
| 457 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, |
| 458 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 459 | ARM::R8, ARM::R10 |
| 460 | }; |
| 461 | |
| 462 | // FP is R7, R9 is available. |
| 463 | static const unsigned GPREven2[] = { |
| 464 | ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, |
| 465 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, |
| 466 | ARM::R9, ARM::R11 |
| 467 | }; |
| 468 | static const unsigned GPROdd2[] = { |
| 469 | ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, |
| 470 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 471 | ARM::R8, ARM::R10 |
| 472 | }; |
| 473 | |
| 474 | // FP is R11, R9 is available. |
| 475 | static const unsigned GPREven3[] = { |
| 476 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, |
| 477 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 478 | ARM::R9 |
| 479 | }; |
| 480 | static const unsigned GPROdd3[] = { |
| 481 | ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, |
| 482 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, |
| 483 | ARM::R8 |
| 484 | }; |
| 485 | |
| 486 | // No FP, R9 is not available. |
| 487 | static const unsigned GPREven4[] = { |
| 488 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, |
| 489 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, |
| 490 | ARM::R11 |
| 491 | }; |
| 492 | static const unsigned GPROdd4[] = { |
| 493 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, |
| 494 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 495 | ARM::R10 |
| 496 | }; |
| 497 | |
| 498 | // FP is R7, R9 is not available. |
| 499 | static const unsigned GPREven5[] = { |
| 500 | ARM::R0, ARM::R2, ARM::R4, ARM::R10, |
| 501 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, |
| 502 | ARM::R11 |
| 503 | }; |
| 504 | static const unsigned GPROdd5[] = { |
| 505 | ARM::R1, ARM::R3, ARM::R5, ARM::R11, |
| 506 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 507 | ARM::R10 |
| 508 | }; |
| 509 | |
| 510 | // FP is R11, R9 is not available. |
| 511 | static const unsigned GPREven6[] = { |
| 512 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, |
| 513 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 |
| 514 | }; |
| 515 | static const unsigned GPROdd6[] = { |
| 516 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, |
| 517 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 |
| 518 | }; |
| 519 | |
| 520 | |
| 521 | if (HintType == ARMRI::RegPairEven) { |
| 522 | if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) |
| 523 | // It's no longer possible to fulfill this hint. Return the default |
| 524 | // allocation order. |
| 525 | return std::make_pair(RC->allocation_order_begin(MF), |
| 526 | RC->allocation_order_end(MF)); |
| 527 | |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 528 | if (!hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 529 | if (!STI.isR9Reserved()) |
| 530 | return std::make_pair(GPREven1, |
| 531 | GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); |
| 532 | else |
| 533 | return std::make_pair(GPREven4, |
| 534 | GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); |
| 535 | } else if (FramePtr == ARM::R7) { |
| 536 | if (!STI.isR9Reserved()) |
| 537 | return std::make_pair(GPREven2, |
| 538 | GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); |
| 539 | else |
| 540 | return std::make_pair(GPREven5, |
| 541 | GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); |
| 542 | } else { // FramePtr == ARM::R11 |
| 543 | if (!STI.isR9Reserved()) |
| 544 | return std::make_pair(GPREven3, |
| 545 | GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); |
| 546 | else |
| 547 | return std::make_pair(GPREven6, |
| 548 | GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); |
| 549 | } |
| 550 | } else if (HintType == ARMRI::RegPairOdd) { |
| 551 | if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) |
| 552 | // It's no longer possible to fulfill this hint. Return the default |
| 553 | // allocation order. |
| 554 | return std::make_pair(RC->allocation_order_begin(MF), |
| 555 | RC->allocation_order_end(MF)); |
| 556 | |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 557 | if (!hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 558 | if (!STI.isR9Reserved()) |
| 559 | return std::make_pair(GPROdd1, |
| 560 | GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); |
| 561 | else |
| 562 | return std::make_pair(GPROdd4, |
| 563 | GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); |
| 564 | } else if (FramePtr == ARM::R7) { |
| 565 | if (!STI.isR9Reserved()) |
| 566 | return std::make_pair(GPROdd2, |
| 567 | GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); |
| 568 | else |
| 569 | return std::make_pair(GPROdd5, |
| 570 | GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); |
| 571 | } else { // FramePtr == ARM::R11 |
| 572 | if (!STI.isR9Reserved()) |
| 573 | return std::make_pair(GPROdd3, |
| 574 | GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); |
| 575 | else |
| 576 | return std::make_pair(GPROdd6, |
| 577 | GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); |
| 578 | } |
| 579 | } |
| 580 | return std::make_pair(RC->allocation_order_begin(MF), |
| 581 | RC->allocation_order_end(MF)); |
| 582 | } |
| 583 | |
| 584 | /// ResolveRegAllocHint - Resolves the specified register allocation hint |
| 585 | /// to a physical register. Returns the physical register if it is successful. |
| 586 | unsigned |
| 587 | ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, |
| 588 | const MachineFunction &MF) const { |
| 589 | if (Reg == 0 || !isPhysicalRegister(Reg)) |
| 590 | return 0; |
| 591 | if (Type == 0) |
| 592 | return Reg; |
| 593 | else if (Type == (unsigned)ARMRI::RegPairOdd) |
| 594 | // Odd register. |
| 595 | return getRegisterPairOdd(Reg, MF); |
| 596 | else if (Type == (unsigned)ARMRI::RegPairEven) |
| 597 | // Even register. |
| 598 | return getRegisterPairEven(Reg, MF); |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | void |
| 603 | ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, |
| 604 | MachineFunction &MF) const { |
| 605 | MachineRegisterInfo *MRI = &MF.getRegInfo(); |
| 606 | std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); |
| 607 | if ((Hint.first == (unsigned)ARMRI::RegPairOdd || |
| 608 | Hint.first == (unsigned)ARMRI::RegPairEven) && |
| 609 | Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { |
| 610 | // If 'Reg' is one of the even / odd register pair and it's now changed |
| 611 | // (e.g. coalesced) into a different register. The other register of the |
| 612 | // pair allocation hint must be updated to reflect the relationship |
| 613 | // change. |
| 614 | unsigned OtherReg = Hint.second; |
| 615 | Hint = MRI->getRegAllocationHint(OtherReg); |
| 616 | if (Hint.second == Reg) |
| 617 | // Make sure the pair has not already divorced. |
| 618 | MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | /// hasFP - Return true if the specified function should have a dedicated frame |
| 623 | /// pointer register. This is true if the function has variable sized allocas |
| 624 | /// or if frame pointer elimination is disabled. |
| 625 | /// |
| 626 | bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 627 | // Mac OS X requires FP not to be clobbered for backtracing purpose. |
| 628 | if (STI.isTargetDarwin()) |
| 629 | return true; |
| 630 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 631 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Evan Cheng | b000d68 | 2010-08-09 22:32:45 +0000 | [diff] [blame] | 632 | // Always eliminate non-leaf frame pointers. |
| 633 | return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 634 | needsStackRealignment(MF) || |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 635 | MFI->hasVarSizedObjects() || |
| 636 | MFI->isFrameAddressTaken()); |
| 637 | } |
| 638 | |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 639 | bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 640 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 641 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 642 | |
| 643 | if (!EnableBasePointer) |
| 644 | return false; |
| 645 | |
| 646 | if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) |
| 647 | return true; |
| 648 | |
| 649 | // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited |
| 650 | // negative range for ldr/str (255), and thumb1 is positive offsets only. |
| 651 | // It's going to be better to use the SP or Base Pointer instead. When there |
| 652 | // are variable sized objects, we can't reference off of the SP, so we |
| 653 | // reserve a Base Pointer. |
| 654 | if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { |
| 655 | // Conservatively estimate whether the negative offset from the frame |
| 656 | // pointer will be sufficient to reach. If a function has a smallish |
| 657 | // frame, it's less likely to have lots of spills and callee saved |
| 658 | // space, so it's all more likely to be within range of the frame pointer. |
| 659 | // If it's wrong, the scavenger will still enable access to work, it just |
| 660 | // won't be optimal. |
| 661 | if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) |
| 662 | return false; |
| 663 | return true; |
| 664 | } |
| 665 | |
| 666 | return false; |
| 667 | } |
| 668 | |
| 669 | bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { |
| 670 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 671 | return (RealignStack && !AFI->isThumb1OnlyFunction()); |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 672 | } |
| 673 | |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 674 | bool ARMBaseRegisterInfo:: |
| 675 | needsStackRealignment(const MachineFunction &MF) const { |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 676 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Eric Christopher | d4c36ce | 2010-07-17 00:27:24 +0000 | [diff] [blame] | 677 | const Function *F = MF.getFunction(); |
Jim Grosbach | ad353c7 | 2009-11-09 22:32:03 +0000 | [diff] [blame] | 678 | unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
Jim Grosbach | fc63300 | 2010-09-03 18:28:19 +0000 | [diff] [blame] | 679 | bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || |
Eric Christopher | 697cba8 | 2010-07-17 00:33:04 +0000 | [diff] [blame] | 680 | F->hasFnAttr(Attribute::StackAlignment)); |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 681 | |
Eric Christopher | d4c36ce | 2010-07-17 00:27:24 +0000 | [diff] [blame] | 682 | return requiresRealignment && canRealignStack(MF); |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 683 | } |
| 684 | |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 685 | bool ARMBaseRegisterInfo:: |
| 686 | cannotEliminateFrame(const MachineFunction &MF) const { |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 687 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Bill Wendling | b92187a | 2010-05-14 21:14:32 +0000 | [diff] [blame] | 688 | if (DisableFramePointerElim(MF) && MFI->adjustsStack()) |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 689 | return true; |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 690 | return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() |
| 691 | || needsStackRealignment(MF); |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 692 | } |
| 693 | |
Evan Cheng | 542383d | 2009-07-28 06:24:12 +0000 | [diff] [blame] | 694 | /// estimateStackSize - Estimate and return the size of the frame. |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 695 | static unsigned estimateStackSize(MachineFunction &MF) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 696 | const MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 697 | int Offset = 0; |
| 698 | for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { |
| 699 | int FixedOff = -FFI->getObjectOffset(i); |
| 700 | if (FixedOff > Offset) Offset = FixedOff; |
| 701 | } |
| 702 | for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { |
| 703 | if (FFI->isDeadObjectIndex(i)) |
| 704 | continue; |
| 705 | Offset += FFI->getObjectSize(i); |
| 706 | unsigned Align = FFI->getObjectAlignment(i); |
| 707 | // Adjust to alignment boundary |
| 708 | Offset = (Offset+Align-1)/Align*Align; |
| 709 | } |
| 710 | return (unsigned)Offset; |
| 711 | } |
| 712 | |
Evan Cheng | 542383d | 2009-07-28 06:24:12 +0000 | [diff] [blame] | 713 | /// estimateRSStackSizeLimit - Look at each instruction that references stack |
| 714 | /// frames and return the stack size limit beyond which some of these |
Jim Grosbach | ce3e769 | 2010-01-06 23:45:18 +0000 | [diff] [blame] | 715 | /// instructions will require a scratch register during their expansion later. |
Evan Cheng | ee42fd3 | 2009-07-30 23:29:25 +0000 | [diff] [blame] | 716 | unsigned |
| 717 | ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 718 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 542383d | 2009-07-28 06:24:12 +0000 | [diff] [blame] | 719 | unsigned Limit = (1 << 12) - 1; |
Chris Lattner | b180d99 | 2009-07-28 18:48:43 +0000 | [diff] [blame] | 720 | for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { |
| 721 | for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); |
| 722 | I != E; ++I) { |
| 723 | for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { |
| 724 | if (!I->getOperand(i).isFI()) continue; |
Jakob Stoklund Olesen | 52c61ec | 2010-06-18 20:59:25 +0000 | [diff] [blame] | 725 | |
| 726 | // When using ADDri to get the address of a stack object, 255 is the |
| 727 | // largest offset guaranteed to fit in the immediate offset. |
| 728 | if (I->getOpcode() == ARM::ADDri) { |
| 729 | Limit = std::min(Limit, (1U << 8) - 1); |
| 730 | break; |
| 731 | } |
| 732 | |
| 733 | // Otherwise check the addressing mode. |
Jakob Stoklund Olesen | 535af4a | 2010-05-17 23:29:23 +0000 | [diff] [blame] | 734 | switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { |
| 735 | case ARMII::AddrMode3: |
| 736 | case ARMII::AddrModeT2_i8: |
| 737 | Limit = std::min(Limit, (1U << 8) - 1); |
| 738 | break; |
| 739 | case ARMII::AddrMode5: |
| 740 | case ARMII::AddrModeT2_i8s4: |
Chris Lattner | b180d99 | 2009-07-28 18:48:43 +0000 | [diff] [blame] | 741 | Limit = std::min(Limit, ((1U << 8) - 1) * 4); |
Jakob Stoklund Olesen | 535af4a | 2010-05-17 23:29:23 +0000 | [diff] [blame] | 742 | break; |
| 743 | case ARMII::AddrModeT2_i12: |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 744 | // i12 supports only positive offset so these will be converted to |
| 745 | // i8 opcodes. See llvm::rewriteT2FrameIndex. |
| 746 | if (hasFP(MF) && AFI->hasStackFrame()) |
| 747 | Limit = std::min(Limit, (1U << 8) - 1); |
Jakob Stoklund Olesen | 535af4a | 2010-05-17 23:29:23 +0000 | [diff] [blame] | 748 | break; |
| 749 | case ARMII::AddrMode6: |
| 750 | // Addressing mode 6 (load/store) instructions can't encode an |
| 751 | // immediate offset for stack references. |
Jim Grosbach | ce3e769 | 2010-01-06 23:45:18 +0000 | [diff] [blame] | 752 | return 0; |
Jakob Stoklund Olesen | 535af4a | 2010-05-17 23:29:23 +0000 | [diff] [blame] | 753 | default: |
| 754 | break; |
| 755 | } |
Chris Lattner | b180d99 | 2009-07-28 18:48:43 +0000 | [diff] [blame] | 756 | break; // At most one FI per instruction |
| 757 | } |
Evan Cheng | 542383d | 2009-07-28 06:24:12 +0000 | [diff] [blame] | 758 | } |
| 759 | } |
| 760 | |
| 761 | return Limit; |
| 762 | } |
| 763 | |
Chris Lattner | 1c55386 | 2010-07-22 21:14:33 +0000 | [diff] [blame] | 764 | static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, |
| 765 | const ARMBaseInstrInfo &TII) { |
| 766 | unsigned FnSize = 0; |
| 767 | for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); |
| 768 | MBBI != E; ++MBBI) { |
| 769 | const MachineBasicBlock &MBB = *MBBI; |
| 770 | for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); |
| 771 | I != E; ++I) |
| 772 | FnSize += TII.GetInstSizeInBytes(I); |
| 773 | } |
| 774 | return FnSize; |
| 775 | } |
| 776 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 777 | void |
| 778 | ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 779 | RegScavenger *RS) const { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 780 | // This tells PEI to spill the FP as if it is any other callee-save register |
| 781 | // to take advantage the eliminateFrameIndex machinery. This also ensures it |
| 782 | // is spilled in the order specified by getCalleeSavedRegs() to make it easier |
| 783 | // to combine multiple loads / stores. |
| 784 | bool CanEliminateFrame = true; |
| 785 | bool CS1Spilled = false; |
| 786 | bool LRSpilled = false; |
| 787 | unsigned NumGPRSpills = 0; |
| 788 | SmallVector<unsigned, 4> UnspilledCS1GPRs; |
| 789 | SmallVector<unsigned, 4> UnspilledCS2GPRs; |
| 790 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 6c7d3a1 | 2010-07-09 20:27:06 +0000 | [diff] [blame] | 791 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 792 | |
Anton Korobeynikov | 7cca606 | 2009-12-06 22:39:50 +0000 | [diff] [blame] | 793 | // Spill R4 if Thumb2 function requires stack realignment - it will be used as |
| 794 | // scratch register. |
| 795 | // FIXME: It will be better just to find spare register here. |
| 796 | if (needsStackRealignment(MF) && |
| 797 | AFI->isThumb2Function()) |
| 798 | MF.getRegInfo().setPhysRegUsed(ARM::R4); |
| 799 | |
Jim Grosbach | f49be7c | 2010-03-10 20:01:30 +0000 | [diff] [blame] | 800 | // Spill LR if Thumb1 function uses variable length argument lists. |
| 801 | if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) |
| 802 | MF.getRegInfo().setPhysRegUsed(ARM::LR); |
| 803 | |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 804 | // Spill the BasePtr if it's used. |
| 805 | if (hasBasePointer(MF)) |
| 806 | MF.getRegInfo().setPhysRegUsed(BasePtr); |
| 807 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 808 | // Don't spill FP if the frame can be eliminated. This is determined |
| 809 | // by scanning the callee-save registers to see if any is used. |
| 810 | const unsigned *CSRegs = getCalleeSavedRegs(); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 811 | for (unsigned i = 0; CSRegs[i]; ++i) { |
| 812 | unsigned Reg = CSRegs[i]; |
| 813 | bool Spilled = false; |
| 814 | if (MF.getRegInfo().isPhysRegUsed(Reg)) { |
| 815 | AFI->setCSRegisterIsSpilled(Reg); |
| 816 | Spilled = true; |
| 817 | CanEliminateFrame = false; |
| 818 | } else { |
| 819 | // Check alias registers too. |
| 820 | for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { |
| 821 | if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { |
| 822 | Spilled = true; |
| 823 | CanEliminateFrame = false; |
| 824 | } |
| 825 | } |
| 826 | } |
| 827 | |
Rafael Espindola | 20fae65 | 2010-06-02 17:54:50 +0000 | [diff] [blame] | 828 | if (!ARM::GPRRegisterClass->contains(Reg)) |
| 829 | continue; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 830 | |
Rafael Espindola | 20fae65 | 2010-06-02 17:54:50 +0000 | [diff] [blame] | 831 | if (Spilled) { |
| 832 | NumGPRSpills++; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 833 | |
Rafael Espindola | 20fae65 | 2010-06-02 17:54:50 +0000 | [diff] [blame] | 834 | if (!STI.isTargetDarwin()) { |
| 835 | if (Reg == ARM::LR) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 836 | LRSpilled = true; |
Rafael Espindola | 20fae65 | 2010-06-02 17:54:50 +0000 | [diff] [blame] | 837 | CS1Spilled = true; |
| 838 | continue; |
| 839 | } |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 840 | |
Rafael Espindola | 20fae65 | 2010-06-02 17:54:50 +0000 | [diff] [blame] | 841 | // Keep track if LR and any of R4, R5, R6, and R7 is spilled. |
| 842 | switch (Reg) { |
| 843 | case ARM::LR: |
| 844 | LRSpilled = true; |
| 845 | // Fallthrough |
| 846 | case ARM::R4: |
| 847 | case ARM::R5: |
| 848 | case ARM::R6: |
| 849 | case ARM::R7: |
| 850 | CS1Spilled = true; |
| 851 | break; |
| 852 | default: |
| 853 | break; |
| 854 | } |
| 855 | } else { |
| 856 | if (!STI.isTargetDarwin()) { |
| 857 | UnspilledCS1GPRs.push_back(Reg); |
| 858 | continue; |
| 859 | } |
| 860 | |
| 861 | switch (Reg) { |
| 862 | case ARM::R4: |
| 863 | case ARM::R5: |
| 864 | case ARM::R6: |
| 865 | case ARM::R7: |
| 866 | case ARM::LR: |
| 867 | UnspilledCS1GPRs.push_back(Reg); |
| 868 | break; |
| 869 | default: |
| 870 | UnspilledCS2GPRs.push_back(Reg); |
| 871 | break; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 872 | } |
| 873 | } |
| 874 | } |
| 875 | |
| 876 | bool ForceLRSpill = false; |
David Goodwin | f1daf7d | 2009-07-08 23:10:31 +0000 | [diff] [blame] | 877 | if (!LRSpilled && AFI->isThumb1OnlyFunction()) { |
Chris Lattner | 1c55386 | 2010-07-22 21:14:33 +0000 | [diff] [blame] | 878 | unsigned FnSize = GetFunctionSizeInBytes(MF, TII); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 879 | // Force LR to be spilled if the Thumb function size is > 2048. This enables |
| 880 | // use of BL to implement far jump. If it turns out that it's not needed |
| 881 | // then the branch fix up path will undo it. |
| 882 | if (FnSize >= (1 << 11)) { |
| 883 | CanEliminateFrame = false; |
| 884 | ForceLRSpill = true; |
| 885 | } |
| 886 | } |
| 887 | |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 888 | // If any of the stack slot references may be out of range of an immediate |
| 889 | // offset, make sure a register (or a spill slot) is available for the |
| 890 | // register scavenger. Note that if we're indexing off the frame pointer, the |
| 891 | // effective stack size is 4 bytes larger since the FP points to the stack |
Jim Grosbach | 6c7d3a1 | 2010-07-09 20:27:06 +0000 | [diff] [blame] | 892 | // slot of the previous FP. Also, if we have variable sized objects in the |
| 893 | // function, stack slot references will often be negative, and some of |
| 894 | // our instructions are positive-offset only, so conservatively consider |
Jim Grosbach | abf7bdf | 2010-08-04 22:46:09 +0000 | [diff] [blame] | 895 | // that case to want a spill slot (or register) as well. Similarly, if |
| 896 | // the function adjusts the stack pointer during execution and the |
| 897 | // adjustments aren't already part of our stack size estimate, our offset |
| 898 | // calculations may be off, so be conservative. |
Jim Grosbach | 6c7d3a1 | 2010-07-09 20:27:06 +0000 | [diff] [blame] | 899 | // FIXME: We could add logic to be more precise about negative offsets |
| 900 | // and which instructions will need a scratch register for them. Is it |
| 901 | // worth the effort and added fragility? |
Chandler Carruth | 68eec39 | 2010-07-10 12:06:22 +0000 | [diff] [blame] | 902 | bool BigStack = |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 903 | (RS && |
| 904 | (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= |
| 905 | estimateRSStackSizeLimit(MF))) |
Chandler Carruth | a7da3ac | 2010-08-05 03:04:21 +0000 | [diff] [blame] | 906 | || MFI->hasVarSizedObjects() |
| 907 | || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 908 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 909 | bool ExtraCSSpill = false; |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 910 | if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 911 | AFI->setHasStackFrame(true); |
| 912 | |
| 913 | // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. |
| 914 | // Spill LR as well so we can fold BX_RET to the registers restore (LDM). |
| 915 | if (!LRSpilled && CS1Spilled) { |
| 916 | MF.getRegInfo().setPhysRegUsed(ARM::LR); |
| 917 | AFI->setCSRegisterIsSpilled(ARM::LR); |
| 918 | NumGPRSpills++; |
| 919 | UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), |
| 920 | UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); |
| 921 | ForceLRSpill = false; |
| 922 | ExtraCSSpill = true; |
| 923 | } |
| 924 | |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 925 | if (hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 926 | MF.getRegInfo().setPhysRegUsed(FramePtr); |
| 927 | NumGPRSpills++; |
| 928 | } |
| 929 | |
| 930 | // If stack and double are 8-byte aligned and we are spilling an odd number |
| 931 | // of GPRs. Spill one extra callee save GPR so we won't have to pad between |
| 932 | // the integer and double callee save areas. |
| 933 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 934 | if (TargetAlign == 8 && (NumGPRSpills & 1)) { |
| 935 | if (CS1Spilled && !UnspilledCS1GPRs.empty()) { |
| 936 | for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { |
| 937 | unsigned Reg = UnspilledCS1GPRs[i]; |
David Goodwin | f1daf7d | 2009-07-08 23:10:31 +0000 | [diff] [blame] | 938 | // Don't spill high register if the function is thumb1 |
| 939 | if (!AFI->isThumb1OnlyFunction() || |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 940 | isARMLowRegister(Reg) || Reg == ARM::LR) { |
| 941 | MF.getRegInfo().setPhysRegUsed(Reg); |
| 942 | AFI->setCSRegisterIsSpilled(Reg); |
| 943 | if (!isReservedReg(MF, Reg)) |
| 944 | ExtraCSSpill = true; |
| 945 | break; |
| 946 | } |
| 947 | } |
| 948 | } else if (!UnspilledCS2GPRs.empty() && |
David Goodwin | f1daf7d | 2009-07-08 23:10:31 +0000 | [diff] [blame] | 949 | !AFI->isThumb1OnlyFunction()) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 950 | unsigned Reg = UnspilledCS2GPRs.front(); |
| 951 | MF.getRegInfo().setPhysRegUsed(Reg); |
| 952 | AFI->setCSRegisterIsSpilled(Reg); |
| 953 | if (!isReservedReg(MF, Reg)) |
| 954 | ExtraCSSpill = true; |
| 955 | } |
| 956 | } |
| 957 | |
| 958 | // Estimate if we might need to scavenge a register at some point in order |
| 959 | // to materialize a stack offset. If so, either spill one additional |
| 960 | // callee-saved register or reserve a special spill slot to facilitate |
Jim Grosbach | 3d6cb88 | 2009-09-24 23:52:18 +0000 | [diff] [blame] | 961 | // register scavenging. Thumb1 needs a spill slot for stack pointer |
| 962 | // adjustments also, even when the frame itself is small. |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 963 | if (BigStack && !ExtraCSSpill) { |
| 964 | // If any non-reserved CS register isn't spilled, just spill one or two |
| 965 | // extra. That should take care of it! |
| 966 | unsigned NumExtras = TargetAlign / 4; |
| 967 | SmallVector<unsigned, 2> Extras; |
| 968 | while (NumExtras && !UnspilledCS1GPRs.empty()) { |
| 969 | unsigned Reg = UnspilledCS1GPRs.back(); |
| 970 | UnspilledCS1GPRs.pop_back(); |
Bob Wilson | 1190c14 | 2010-05-13 19:58:24 +0000 | [diff] [blame] | 971 | if (!isReservedReg(MF, Reg) && |
| 972 | (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || |
| 973 | Reg == ARM::LR)) { |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 974 | Extras.push_back(Reg); |
| 975 | NumExtras--; |
| 976 | } |
| 977 | } |
| 978 | // For non-Thumb1 functions, also check for hi-reg CS registers |
| 979 | if (!AFI->isThumb1OnlyFunction()) { |
| 980 | while (NumExtras && !UnspilledCS2GPRs.empty()) { |
| 981 | unsigned Reg = UnspilledCS2GPRs.back(); |
| 982 | UnspilledCS2GPRs.pop_back(); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 983 | if (!isReservedReg(MF, Reg)) { |
| 984 | Extras.push_back(Reg); |
| 985 | NumExtras--; |
| 986 | } |
| 987 | } |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 988 | } |
| 989 | if (Extras.size() && NumExtras == 0) { |
| 990 | for (unsigned i = 0, e = Extras.size(); i != e; ++i) { |
| 991 | MF.getRegInfo().setPhysRegUsed(Extras[i]); |
| 992 | AFI->setCSRegisterIsSpilled(Extras[i]); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 993 | } |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 994 | } else if (!AFI->isThumb1OnlyFunction()) { |
| 995 | // note: Thumb1 functions spill to R12, not the stack. Reserve a slot |
| 996 | // closest to SP or frame pointer. |
| 997 | const TargetRegisterClass *RC = ARM::GPRRegisterClass; |
Jakob Stoklund Olesen | 657baec | 2010-02-24 22:43:17 +0000 | [diff] [blame] | 998 | RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), |
| 999 | RC->getAlignment(), |
| 1000 | false)); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1001 | } |
| 1002 | } |
| 1003 | } |
| 1004 | |
| 1005 | if (ForceLRSpill) { |
| 1006 | MF.getRegInfo().setPhysRegUsed(ARM::LR); |
| 1007 | AFI->setCSRegisterIsSpilled(ARM::LR); |
| 1008 | AFI->setLRIsSpilledForFarJump(true); |
| 1009 | } |
| 1010 | } |
| 1011 | |
| 1012 | unsigned ARMBaseRegisterInfo::getRARegister() const { |
| 1013 | return ARM::LR; |
| 1014 | } |
| 1015 | |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 1016 | unsigned |
David Greene | 3f2bf85 | 2009-11-12 20:49:22 +0000 | [diff] [blame] | 1017 | ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1018 | if (hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1019 | return FramePtr; |
| 1020 | return ARM::SP; |
| 1021 | } |
| 1022 | |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1023 | // Provide a base+offset reference to an FI slot for debug info. It's the |
| 1024 | // same as what we use for resolving the code-gen references for now. |
| 1025 | // FIXME: This can go wrong when references are SP-relative and simple call |
| 1026 | // frames aren't used. |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1027 | int |
Chris Lattner | 30c6b75 | 2010-01-26 23:15:09 +0000 | [diff] [blame] | 1028 | ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI, |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1029 | unsigned &FrameReg) const { |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1030 | return ResolveFrameIndexReference(MF, FI, FrameReg, 0); |
| 1031 | } |
| 1032 | |
| 1033 | int |
| 1034 | ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF, |
| 1035 | int FI, |
| 1036 | unsigned &FrameReg, |
| 1037 | int SPAdj) const { |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1038 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Chris Lattner | 30c6b75 | 2010-01-26 23:15:09 +0000 | [diff] [blame] | 1039 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1040 | int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1041 | int FPOffset = Offset - AFI->getFramePtrSpillOffset(); |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1042 | bool isFixed = MFI->isFixedObjectIndex(FI); |
| 1043 | |
Jim Grosbach | a37aa54 | 2009-11-22 20:05:32 +0000 | [diff] [blame] | 1044 | FrameReg = ARM::SP; |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1045 | Offset += SPAdj; |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1046 | if (AFI->isGPRCalleeSavedArea1Frame(FI)) |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1047 | return Offset - AFI->getGPRCalleeSavedArea1Offset(); |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1048 | else if (AFI->isGPRCalleeSavedArea2Frame(FI)) |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1049 | return Offset - AFI->getGPRCalleeSavedArea2Offset(); |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1050 | else if (AFI->isDPRCalleeSavedAreaFrame(FI)) |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1051 | return Offset - AFI->getDPRCalleeSavedAreaOffset(); |
| 1052 | |
| 1053 | // When dynamically realigning the stack, use the frame pointer for |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1054 | // parameters, and the stack/base pointer for locals. |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1055 | if (needsStackRealignment(MF)) { |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1056 | assert (hasFP(MF) && "dynamic stack realignment without a FP!"); |
| 1057 | if (isFixed) { |
| 1058 | FrameReg = getFrameRegister(MF); |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1059 | Offset = FPOffset; |
Jim Grosbach | 6b53834 | 2010-09-08 17:05:45 +0000 | [diff] [blame^] | 1060 | } else if (MFI->hasVarSizedObjects()) { |
| 1061 | assert(hasBasePointer(MF) && |
| 1062 | "VLAs and dynamic stack alignment, but missing base pointer!"); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1063 | FrameReg = BasePtr; |
Jim Grosbach | 6b53834 | 2010-09-08 17:05:45 +0000 | [diff] [blame^] | 1064 | } |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1065 | return Offset; |
| 1066 | } |
| 1067 | |
| 1068 | // If there is a frame pointer, use it when we can. |
| 1069 | if (hasFP(MF) && AFI->hasStackFrame()) { |
| 1070 | // Use frame pointer to reference fixed objects. Use it for locals if |
| 1071 | // there are VLAs (and thus the SP isn't reliable as a base). |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1072 | if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) { |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1073 | FrameReg = getFrameRegister(MF); |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1074 | Offset = FPOffset; |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1075 | } else if (MFI->hasVarSizedObjects()) { |
| 1076 | assert(hasBasePointer(MF) && "missing base pointer!"); |
| 1077 | // Use the base register since we have it. |
| 1078 | FrameReg = BasePtr; |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1079 | } else if (AFI->isThumb2Function()) { |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1080 | // In Thumb2 mode, the negative offset is very limited. Try to avoid |
| 1081 | // out of range references. |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1082 | if (FPOffset >= -255 && FPOffset < 0) { |
| 1083 | FrameReg = getFrameRegister(MF); |
| 1084 | Offset = FPOffset; |
| 1085 | } |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1086 | } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { |
| 1087 | // Otherwise, use SP or FP, whichever is closer to the stack slot. |
| 1088 | FrameReg = getFrameRegister(MF); |
| 1089 | Offset = FPOffset; |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1090 | } |
| 1091 | } |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1092 | // Use the base pointer if we have one. |
| 1093 | if (hasBasePointer(MF)) |
| 1094 | FrameReg = BasePtr; |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1095 | return Offset; |
| 1096 | } |
| 1097 | |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1098 | int |
Chris Lattner | 30c6b75 | 2010-01-26 23:15:09 +0000 | [diff] [blame] | 1099 | ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, |
| 1100 | int FI) const { |
Jim Grosbach | 50f8516 | 2009-11-22 02:32:29 +0000 | [diff] [blame] | 1101 | unsigned FrameReg; |
| 1102 | return getFrameIndexReference(MF, FI, FrameReg); |
| 1103 | } |
| 1104 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1105 | unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 1106 | llvm_unreachable("What is the exception register"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1107 | return 0; |
| 1108 | } |
| 1109 | |
| 1110 | unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 1111 | llvm_unreachable("What is the exception handler register"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1112 | return 0; |
| 1113 | } |
| 1114 | |
| 1115 | int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
| 1116 | return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); |
| 1117 | } |
| 1118 | |
| 1119 | unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 1120 | const MachineFunction &MF) const { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1121 | switch (Reg) { |
| 1122 | default: break; |
| 1123 | // Return 0 if either register of the pair is a special register. |
| 1124 | // So no R12, etc. |
| 1125 | case ARM::R1: |
| 1126 | return ARM::R0; |
| 1127 | case ARM::R3: |
Jim Grosbach | 6009751 | 2009-10-19 22:57:03 +0000 | [diff] [blame] | 1128 | return ARM::R2; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1129 | case ARM::R5: |
| 1130 | return ARM::R4; |
| 1131 | case ARM::R7: |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1132 | return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) |
| 1133 | ? 0 : ARM::R6; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1134 | case ARM::R9: |
| 1135 | return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; |
| 1136 | case ARM::R11: |
| 1137 | return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; |
| 1138 | |
| 1139 | case ARM::S1: |
| 1140 | return ARM::S0; |
| 1141 | case ARM::S3: |
| 1142 | return ARM::S2; |
| 1143 | case ARM::S5: |
| 1144 | return ARM::S4; |
| 1145 | case ARM::S7: |
| 1146 | return ARM::S6; |
| 1147 | case ARM::S9: |
| 1148 | return ARM::S8; |
| 1149 | case ARM::S11: |
| 1150 | return ARM::S10; |
| 1151 | case ARM::S13: |
| 1152 | return ARM::S12; |
| 1153 | case ARM::S15: |
| 1154 | return ARM::S14; |
| 1155 | case ARM::S17: |
| 1156 | return ARM::S16; |
| 1157 | case ARM::S19: |
| 1158 | return ARM::S18; |
| 1159 | case ARM::S21: |
| 1160 | return ARM::S20; |
| 1161 | case ARM::S23: |
| 1162 | return ARM::S22; |
| 1163 | case ARM::S25: |
| 1164 | return ARM::S24; |
| 1165 | case ARM::S27: |
| 1166 | return ARM::S26; |
| 1167 | case ARM::S29: |
| 1168 | return ARM::S28; |
| 1169 | case ARM::S31: |
| 1170 | return ARM::S30; |
| 1171 | |
| 1172 | case ARM::D1: |
| 1173 | return ARM::D0; |
| 1174 | case ARM::D3: |
| 1175 | return ARM::D2; |
| 1176 | case ARM::D5: |
| 1177 | return ARM::D4; |
| 1178 | case ARM::D7: |
| 1179 | return ARM::D6; |
| 1180 | case ARM::D9: |
| 1181 | return ARM::D8; |
| 1182 | case ARM::D11: |
| 1183 | return ARM::D10; |
| 1184 | case ARM::D13: |
| 1185 | return ARM::D12; |
| 1186 | case ARM::D15: |
| 1187 | return ARM::D14; |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 1188 | case ARM::D17: |
| 1189 | return ARM::D16; |
| 1190 | case ARM::D19: |
| 1191 | return ARM::D18; |
| 1192 | case ARM::D21: |
| 1193 | return ARM::D20; |
| 1194 | case ARM::D23: |
| 1195 | return ARM::D22; |
| 1196 | case ARM::D25: |
| 1197 | return ARM::D24; |
| 1198 | case ARM::D27: |
| 1199 | return ARM::D26; |
| 1200 | case ARM::D29: |
| 1201 | return ARM::D28; |
| 1202 | case ARM::D31: |
| 1203 | return ARM::D30; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1204 | } |
| 1205 | |
| 1206 | return 0; |
| 1207 | } |
| 1208 | |
| 1209 | unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, |
| 1210 | const MachineFunction &MF) const { |
| 1211 | switch (Reg) { |
| 1212 | default: break; |
| 1213 | // Return 0 if either register of the pair is a special register. |
| 1214 | // So no R12, etc. |
| 1215 | case ARM::R0: |
| 1216 | return ARM::R1; |
| 1217 | case ARM::R2: |
Jim Grosbach | 6009751 | 2009-10-19 22:57:03 +0000 | [diff] [blame] | 1218 | return ARM::R3; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1219 | case ARM::R4: |
| 1220 | return ARM::R5; |
| 1221 | case ARM::R6: |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1222 | return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) |
| 1223 | ? 0 : ARM::R7; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1224 | case ARM::R8: |
| 1225 | return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; |
| 1226 | case ARM::R10: |
| 1227 | return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; |
| 1228 | |
| 1229 | case ARM::S0: |
| 1230 | return ARM::S1; |
| 1231 | case ARM::S2: |
| 1232 | return ARM::S3; |
| 1233 | case ARM::S4: |
| 1234 | return ARM::S5; |
| 1235 | case ARM::S6: |
| 1236 | return ARM::S7; |
| 1237 | case ARM::S8: |
| 1238 | return ARM::S9; |
| 1239 | case ARM::S10: |
| 1240 | return ARM::S11; |
| 1241 | case ARM::S12: |
| 1242 | return ARM::S13; |
| 1243 | case ARM::S14: |
| 1244 | return ARM::S15; |
| 1245 | case ARM::S16: |
| 1246 | return ARM::S17; |
| 1247 | case ARM::S18: |
| 1248 | return ARM::S19; |
| 1249 | case ARM::S20: |
| 1250 | return ARM::S21; |
| 1251 | case ARM::S22: |
| 1252 | return ARM::S23; |
| 1253 | case ARM::S24: |
| 1254 | return ARM::S25; |
| 1255 | case ARM::S26: |
| 1256 | return ARM::S27; |
| 1257 | case ARM::S28: |
| 1258 | return ARM::S29; |
| 1259 | case ARM::S30: |
| 1260 | return ARM::S31; |
| 1261 | |
| 1262 | case ARM::D0: |
| 1263 | return ARM::D1; |
| 1264 | case ARM::D2: |
| 1265 | return ARM::D3; |
| 1266 | case ARM::D4: |
| 1267 | return ARM::D5; |
| 1268 | case ARM::D6: |
| 1269 | return ARM::D7; |
| 1270 | case ARM::D8: |
| 1271 | return ARM::D9; |
| 1272 | case ARM::D10: |
| 1273 | return ARM::D11; |
| 1274 | case ARM::D12: |
| 1275 | return ARM::D13; |
| 1276 | case ARM::D14: |
| 1277 | return ARM::D15; |
Evan Cheng | 8295d99 | 2009-07-22 05:55:18 +0000 | [diff] [blame] | 1278 | case ARM::D16: |
| 1279 | return ARM::D17; |
| 1280 | case ARM::D18: |
| 1281 | return ARM::D19; |
| 1282 | case ARM::D20: |
| 1283 | return ARM::D21; |
| 1284 | case ARM::D22: |
| 1285 | return ARM::D23; |
| 1286 | case ARM::D24: |
| 1287 | return ARM::D25; |
| 1288 | case ARM::D26: |
| 1289 | return ARM::D27; |
| 1290 | case ARM::D28: |
| 1291 | return ARM::D29; |
| 1292 | case ARM::D30: |
| 1293 | return ARM::D31; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1294 | } |
| 1295 | |
| 1296 | return 0; |
| 1297 | } |
| 1298 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1299 | /// emitLoadConstPool - Emits a load from constpool to materialize the |
| 1300 | /// specified immediate. |
| 1301 | void ARMBaseRegisterInfo:: |
| 1302 | emitLoadConstPool(MachineBasicBlock &MBB, |
| 1303 | MachineBasicBlock::iterator &MBBI, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1304 | DebugLoc dl, |
Evan Cheng | 3784453 | 2009-07-16 09:20:10 +0000 | [diff] [blame] | 1305 | unsigned DestReg, unsigned SubIdx, int Val, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1306 | ARMCC::CondCodes Pred, |
| 1307 | unsigned PredReg) const { |
| 1308 | MachineFunction &MF = *MBB.getParent(); |
| 1309 | MachineConstantPool *ConstantPool = MF.getConstantPool(); |
Dan Gohman | 46510a7 | 2010-04-15 01:51:59 +0000 | [diff] [blame] | 1310 | const Constant *C = |
Owen Anderson | 1d0be15 | 2009-08-13 21:58:54 +0000 | [diff] [blame] | 1311 | ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1312 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); |
| 1313 | |
Evan Cheng | 3784453 | 2009-07-16 09:20:10 +0000 | [diff] [blame] | 1314 | BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) |
| 1315 | .addReg(DestReg, getDefRegState(true), SubIdx) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1316 | .addConstantPoolIndex(Idx) |
| 1317 | .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); |
| 1318 | } |
| 1319 | |
| 1320 | bool ARMBaseRegisterInfo:: |
| 1321 | requiresRegisterScavenging(const MachineFunction &MF) const { |
| 1322 | return true; |
| 1323 | } |
Jim Grosbach | 41fff8c | 2009-10-21 23:40:56 +0000 | [diff] [blame] | 1324 | |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 1325 | bool ARMBaseRegisterInfo:: |
| 1326 | requiresFrameIndexScavenging(const MachineFunction &MF) const { |
Jim Grosbach | ca5dfb7 | 2009-10-28 17:33:28 +0000 | [diff] [blame] | 1327 | return true; |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 1328 | } |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1329 | |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 1330 | bool ARMBaseRegisterInfo:: |
| 1331 | requiresVirtualBaseRegisters(const MachineFunction &MF) const { |
| 1332 | return EnableLocalStackAlloc; |
| 1333 | } |
| 1334 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1335 | // hasReservedCallFrame - Under normal circumstances, when a frame pointer is |
| 1336 | // not required, we reserve argument space for call sites in the function |
| 1337 | // immediately on entry to the current function. This eliminates the need for |
| 1338 | // add/sub sp brackets around call sites. Returns true if the call frame is |
| 1339 | // included as part of the stack frame. |
| 1340 | bool ARMBaseRegisterInfo:: |
Eric Christopher | 72852a8 | 2010-07-20 06:52:21 +0000 | [diff] [blame] | 1341 | hasReservedCallFrame(const MachineFunction &MF) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1342 | const MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 1343 | unsigned CFSize = FFI->getMaxCallFrameSize(); |
| 1344 | // It's not always a good idea to include the call frame as part of the |
| 1345 | // stack frame. ARM (especially Thumb) has small immediate offset to |
| 1346 | // address the stack frame. So a large call frame can cause poor codegen |
| 1347 | // and may even makes it impossible to scavenge a register. |
| 1348 | if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 |
| 1349 | return false; |
| 1350 | |
| 1351 | return !MF.getFrameInfo()->hasVarSizedObjects(); |
| 1352 | } |
| 1353 | |
Jim Grosbach | 4642ad3 | 2010-02-22 23:10:38 +0000 | [diff] [blame] | 1354 | // canSimplifyCallFramePseudos - If there is a reserved call frame, the |
| 1355 | // call frame pseudos can be simplified. Unlike most targets, having a FP |
| 1356 | // is not sufficient here since we still may reference some objects via SP |
| 1357 | // even when FP is available in Thumb2 mode. |
| 1358 | bool ARMBaseRegisterInfo:: |
Eric Christopher | 72852a8 | 2010-07-20 06:52:21 +0000 | [diff] [blame] | 1359 | canSimplifyCallFramePseudos(const MachineFunction &MF) const { |
Jim Grosbach | 5f366af | 2010-02-24 02:15:43 +0000 | [diff] [blame] | 1360 | return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); |
Jim Grosbach | 4642ad3 | 2010-02-22 23:10:38 +0000 | [diff] [blame] | 1361 | } |
| 1362 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1363 | static void |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1364 | emitSPUpdate(bool isARM, |
| 1365 | MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 1366 | DebugLoc dl, const ARMBaseInstrInfo &TII, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1367 | int NumBytes, |
| 1368 | ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1369 | if (isARM) |
| 1370 | emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, |
| 1371 | Pred, PredReg, TII); |
| 1372 | else |
| 1373 | emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, |
| 1374 | Pred, PredReg, TII); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1375 | } |
| 1376 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1377 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1378 | void ARMBaseRegisterInfo:: |
| 1379 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 1380 | MachineBasicBlock::iterator I) const { |
| 1381 | if (!hasReservedCallFrame(MF)) { |
| 1382 | // If we have alloca, convert as follows: |
| 1383 | // ADJCALLSTACKDOWN -> sub, sp, sp, amount |
| 1384 | // ADJCALLSTACKUP -> add, sp, sp, amount |
| 1385 | MachineInstr *Old = I; |
| 1386 | DebugLoc dl = Old->getDebugLoc(); |
| 1387 | unsigned Amount = Old->getOperand(0).getImm(); |
| 1388 | if (Amount != 0) { |
| 1389 | // We need to keep the stack aligned properly. To do this, we round the |
| 1390 | // amount of space needed for the outgoing arguments up to the next |
| 1391 | // alignment boundary. |
| 1392 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 1393 | Amount = (Amount+Align-1)/Align*Align; |
| 1394 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1395 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 1396 | assert(!AFI->isThumb1OnlyFunction() && |
Jim Grosbach | cf453ee | 2010-02-23 17:16:27 +0000 | [diff] [blame] | 1397 | "This eliminateCallFramePseudoInstr does not support Thumb1!"); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1398 | bool isARM = !AFI->isThumbFunction(); |
| 1399 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1400 | // Replace the pseudo instruction with a new instruction... |
| 1401 | unsigned Opc = Old->getOpcode(); |
Jim Grosbach | 4c7628e | 2010-02-22 22:47:46 +0000 | [diff] [blame] | 1402 | int PIdx = Old->findFirstPredOperandIdx(); |
| 1403 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 1404 | ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1405 | if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { |
| 1406 | // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. |
| 1407 | unsigned PredReg = Old->getOperand(2).getReg(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1408 | emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1409 | } else { |
| 1410 | // Note: PredReg is operand 3 for ADJCALLSTACKUP. |
| 1411 | unsigned PredReg = Old->getOperand(3).getReg(); |
| 1412 | assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1413 | emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1414 | } |
| 1415 | } |
| 1416 | } |
| 1417 | MBB.erase(I); |
| 1418 | } |
| 1419 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1420 | int64_t ARMBaseRegisterInfo:: |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1421 | getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1422 | const TargetInstrDesc &Desc = MI->getDesc(); |
| 1423 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 1424 | int64_t InstrOffs = 0;; |
| 1425 | int Scale = 1; |
| 1426 | unsigned ImmIdx = 0; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1427 | switch (AddrMode) { |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1428 | case ARMII::AddrModeT2_i8: |
| 1429 | case ARMII::AddrModeT2_i12: |
| 1430 | // i8 supports only negative, and i12 supports only positive, so |
| 1431 | // based on Offset sign, consider the appropriate instruction |
| 1432 | InstrOffs = MI->getOperand(Idx+1).getImm(); |
| 1433 | Scale = 1; |
| 1434 | break; |
| 1435 | case ARMII::AddrMode5: { |
| 1436 | // VFP address mode. |
| 1437 | const MachineOperand &OffOp = MI->getOperand(Idx+1); |
Jim Grosbach | f78ee63 | 2010-08-25 19:11:34 +0000 | [diff] [blame] | 1438 | InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1439 | if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) |
| 1440 | InstrOffs = -InstrOffs; |
| 1441 | Scale = 4; |
| 1442 | break; |
| 1443 | } |
| 1444 | case ARMII::AddrMode2: { |
| 1445 | ImmIdx = Idx+2; |
| 1446 | InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); |
| 1447 | if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1448 | InstrOffs = -InstrOffs; |
| 1449 | break; |
| 1450 | } |
| 1451 | case ARMII::AddrMode3: { |
| 1452 | ImmIdx = Idx+2; |
| 1453 | InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); |
| 1454 | if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1455 | InstrOffs = -InstrOffs; |
| 1456 | break; |
| 1457 | } |
| 1458 | case ARMII::AddrModeT1_s: { |
| 1459 | ImmIdx = Idx+1; |
| 1460 | InstrOffs = MI->getOperand(ImmIdx).getImm(); |
| 1461 | Scale = 4; |
| 1462 | break; |
| 1463 | } |
| 1464 | default: |
| 1465 | llvm_unreachable("Unsupported addressing mode!"); |
| 1466 | break; |
| 1467 | } |
| 1468 | |
| 1469 | return InstrOffs * Scale; |
| 1470 | } |
| 1471 | |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1472 | /// needsFrameBaseReg - Returns true if the instruction's frame index |
| 1473 | /// reference would be better served by a base register other than FP |
| 1474 | /// or SP. Used by LocalStackFrameAllocation to determine which frame index |
| 1475 | /// references it should create new base registers for. |
| 1476 | bool ARMBaseRegisterInfo:: |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1477 | needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { |
| 1478 | for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { |
| 1479 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); |
| 1480 | } |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1481 | |
| 1482 | // It's the load/store FI references that cause issues, as it can be difficult |
| 1483 | // to materialize the offset if it won't fit in the literal field. Estimate |
| 1484 | // based on the size of the local frame and some conservative assumptions |
| 1485 | // about the rest of the stack frame (note, this is pre-regalloc, so |
| 1486 | // we don't know everything for certain yet) whether this offset is likely |
| 1487 | // to be out of range of the immediate. Return true if so. |
| 1488 | |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1489 | // We only generate virtual base registers for loads and stores, so |
| 1490 | // return false for everything else. |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1491 | unsigned Opc = MI->getOpcode(); |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1492 | switch (Opc) { |
| 1493 | case ARM::LDR: case ARM::LDRH: case ARM::LDRB: |
| 1494 | case ARM::STR: case ARM::STRH: case ARM::STRB: |
| 1495 | case ARM::t2LDRi12: case ARM::t2LDRi8: |
| 1496 | case ARM::t2STRi12: case ARM::t2STRi8: |
| 1497 | case ARM::VLDRS: case ARM::VLDRD: |
| 1498 | case ARM::VSTRS: case ARM::VSTRD: |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1499 | case ARM::tSTRspi: case ARM::tLDRspi: |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1500 | if (ForceAllBaseRegAlloc) |
| 1501 | return true; |
| 1502 | break; |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1503 | default: |
| 1504 | return false; |
| 1505 | } |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1506 | |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1507 | // Without a virtual base register, if the function has variable sized |
| 1508 | // objects, all fixed-size local references will be via the frame pointer, |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1509 | // Approximate the offset and see if it's legal for the instruction. |
| 1510 | // Note that the incoming offset is based on the SP value at function entry, |
| 1511 | // so it'll be negative. |
| 1512 | MachineFunction &MF = *MI->getParent()->getParent(); |
| 1513 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1514 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1515 | |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1516 | // Estimate an offset from the frame pointer. |
| 1517 | // Conservatively assume all callee-saved registers get pushed. R4-R6 |
| 1518 | // will be earlier than the FP, so we ignore those. |
| 1519 | // R7, LR |
| 1520 | int64_t FPOffset = Offset - 8; |
| 1521 | // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 |
| 1522 | if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) |
| 1523 | FPOffset -= 80; |
| 1524 | // Estimate an offset from the stack pointer. |
Jim Grosbach | c1dc78d | 2010-08-31 18:52:31 +0000 | [diff] [blame] | 1525 | // The incoming offset is relating to the SP at the start of the function, |
| 1526 | // but when we access the local it'll be relative to the SP after local |
| 1527 | // allocation, so adjust our SP-relative offset by that allocation size. |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1528 | Offset = -Offset; |
Jim Grosbach | c1dc78d | 2010-08-31 18:52:31 +0000 | [diff] [blame] | 1529 | Offset += MFI->getLocalFrameSize(); |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 1530 | // Assume that we'll have at least some spill slots allocated. |
| 1531 | // FIXME: This is a total SWAG number. We should run some statistics |
| 1532 | // and pick a real one. |
| 1533 | Offset += 128; // 128 bytes of spill slots |
| 1534 | |
| 1535 | // If there is a frame pointer, try using it. |
| 1536 | // The FP is only available if there is no dynamic realignment. We |
| 1537 | // don't know for sure yet whether we'll need that, so we guess based |
| 1538 | // on whether there are any local variables that would trigger it. |
| 1539 | unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 1540 | if (hasFP(MF) && |
| 1541 | !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { |
| 1542 | if (isFrameOffsetLegal(MI, FPOffset)) |
| 1543 | return false; |
| 1544 | } |
| 1545 | // If we can reference via the stack pointer, try that. |
| 1546 | // FIXME: This (and the code that resolves the references) can be improved |
| 1547 | // to only disallow SP relative references in the live range of |
| 1548 | // the VLA(s). In practice, it's unclear how much difference that |
| 1549 | // would make, but it may be worth doing. |
| 1550 | if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) |
| 1551 | return false; |
| 1552 | |
| 1553 | // The offset likely isn't legal, we want to allocate a virtual base register. |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 1554 | return true; |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1555 | } |
| 1556 | |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1557 | /// materializeFrameBaseRegister - Insert defining instruction(s) for |
| 1558 | /// BaseReg to be a pointer to FrameIdx before insertion point I. |
| 1559 | void ARMBaseRegisterInfo:: |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1560 | materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg, |
| 1561 | int FrameIdx, int64_t Offset) const { |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1562 | ARMFunctionInfo *AFI = |
| 1563 | I->getParent()->getParent()->getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1564 | unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : |
| 1565 | (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1566 | |
| 1567 | MachineInstrBuilder MIB = |
| 1568 | BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg) |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1569 | .addFrameIndex(FrameIdx).addImm(Offset); |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1570 | if (!AFI->isThumb1OnlyFunction()) |
| 1571 | AddDefaultCC(AddDefaultPred(MIB)); |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 1572 | } |
| 1573 | |
| 1574 | void |
| 1575 | ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, |
| 1576 | unsigned BaseReg, int64_t Offset) const { |
| 1577 | MachineInstr &MI = *I; |
| 1578 | MachineBasicBlock &MBB = *MI.getParent(); |
| 1579 | MachineFunction &MF = *MBB.getParent(); |
| 1580 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 1581 | int Off = Offset; // ARM doesn't need the general 64-bit offsets |
| 1582 | unsigned i = 0; |
| 1583 | |
| 1584 | assert(!AFI->isThumb1OnlyFunction() && |
| 1585 | "This resolveFrameIndex does not support Thumb1!"); |
| 1586 | |
| 1587 | while (!MI.getOperand(i).isFI()) { |
| 1588 | ++i; |
| 1589 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1590 | } |
| 1591 | bool Done = false; |
| 1592 | if (!AFI->isThumbFunction()) |
| 1593 | Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); |
| 1594 | else { |
| 1595 | assert(AFI->isThumb2Function()); |
| 1596 | Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); |
| 1597 | } |
| 1598 | assert (Done && "Unable to resolve frame index!"); |
| 1599 | } |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 1600 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1601 | bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, |
| 1602 | int64_t Offset) const { |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1603 | const TargetInstrDesc &Desc = MI->getDesc(); |
| 1604 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 1605 | unsigned i = 0; |
| 1606 | |
| 1607 | while (!MI->getOperand(i).isFI()) { |
| 1608 | ++i; |
| 1609 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); |
| 1610 | } |
| 1611 | |
| 1612 | // AddrMode4 and AddrMode6 cannot handle any offset. |
| 1613 | if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) |
| 1614 | return Offset == 0; |
| 1615 | |
| 1616 | unsigned NumBits = 0; |
| 1617 | unsigned Scale = 1; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1618 | bool isSigned = true; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1619 | switch (AddrMode) { |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1620 | case ARMII::AddrModeT2_i8: |
| 1621 | case ARMII::AddrModeT2_i12: |
| 1622 | // i8 supports only negative, and i12 supports only positive, so |
| 1623 | // based on Offset sign, consider the appropriate instruction |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1624 | Scale = 1; |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1625 | if (Offset < 0) { |
| 1626 | NumBits = 8; |
| 1627 | Offset = -Offset; |
| 1628 | } else { |
| 1629 | NumBits = 12; |
| 1630 | } |
| 1631 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1632 | case ARMII::AddrMode5: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1633 | // VFP address mode. |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1634 | NumBits = 8; |
| 1635 | Scale = 4; |
| 1636 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1637 | case ARMII::AddrMode2: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1638 | NumBits = 12; |
| 1639 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1640 | case ARMII::AddrMode3: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1641 | NumBits = 8; |
| 1642 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1643 | case ARMII::AddrModeT1_s: |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1644 | NumBits = 5; |
| 1645 | Scale = 4; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1646 | isSigned = false; |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1647 | break; |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1648 | default: |
| 1649 | llvm_unreachable("Unsupported addressing mode!"); |
| 1650 | break; |
| 1651 | } |
| 1652 | |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1653 | Offset += getFrameIndexInstrOffset(MI, i); |
Jim Grosbach | d4511e9 | 2010-08-31 18:49:31 +0000 | [diff] [blame] | 1654 | // Make sure the offset is encodable for instructions that scale the |
| 1655 | // immediate. |
| 1656 | if ((Offset & (Scale-1)) != 0) |
| 1657 | return false; |
| 1658 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1659 | if (isSigned && Offset < 0) |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1660 | Offset = -Offset; |
| 1661 | |
| 1662 | unsigned Mask = (1 << NumBits) - 1; |
| 1663 | if ((unsigned)Offset <= Mask * Scale) |
| 1664 | return true; |
Jim Grosbach | 74d803a | 2010-08-18 17:57:37 +0000 | [diff] [blame] | 1665 | |
| 1666 | return false; |
| 1667 | } |
| 1668 | |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1669 | void |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1670 | ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1671 | int SPAdj, RegScavenger *RS) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1672 | unsigned i = 0; |
| 1673 | MachineInstr &MI = *II; |
| 1674 | MachineBasicBlock &MBB = *MI.getParent(); |
| 1675 | MachineFunction &MF = *MBB.getParent(); |
| 1676 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1677 | assert(!AFI->isThumb1OnlyFunction() && |
Bob Wilson | a15de00 | 2009-09-18 21:42:44 +0000 | [diff] [blame] | 1678 | "This eliminateFrameIndex does not support Thumb1!"); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1679 | |
| 1680 | while (!MI.getOperand(i).isFI()) { |
| 1681 | ++i; |
| 1682 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1683 | } |
| 1684 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1685 | int FrameIndex = MI.getOperand(i).getIndex(); |
Jim Grosbach | a37aa54 | 2009-11-22 20:05:32 +0000 | [diff] [blame] | 1686 | unsigned FrameReg; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1687 | |
Jim Grosbach | e3ede5e | 2010-08-05 19:27:37 +0000 | [diff] [blame] | 1688 | int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1689 | |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 1690 | // Special handling of dbg_value instructions. |
| 1691 | if (MI.isDebugValue()) { |
| 1692 | MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); |
| 1693 | MI.getOperand(i+1).ChangeToImmediate(Offset); |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1694 | return; |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 1695 | } |
| 1696 | |
Evan Cheng | 48d8afa | 2009-11-01 21:12:51 +0000 | [diff] [blame] | 1697 | // Modify MI as necessary to handle as much of 'Offset' as possible |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1698 | bool Done = false; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1699 | if (!AFI->isThumbFunction()) |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1700 | Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1701 | else { |
| 1702 | assert(AFI->isThumb2Function()); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1703 | Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1704 | } |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1705 | if (Done) |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1706 | return; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1707 | |
| 1708 | // If we get here, the immediate doesn't fit into the instruction. We folded |
| 1709 | // as much as possible above, handle the rest, providing a register that is |
| 1710 | // SP+LargeImm. |
Daniel Dunbar | 19bb87d | 2009-08-28 08:08:22 +0000 | [diff] [blame] | 1711 | assert((Offset || |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1712 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || |
| 1713 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1714 | "This code isn't needed if offset already handled!"); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1715 | |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 1716 | unsigned ScratchReg = 0; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1717 | int PIdx = MI.findFirstPredOperandIdx(); |
| 1718 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 1719 | ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); |
| 1720 | unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1721 | if (Offset == 0) |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1722 | // Must be addrmode4/6. |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1723 | MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1724 | else { |
Jim Grosbach | ca5dfb7 | 2009-10-28 17:33:28 +0000 | [diff] [blame] | 1725 | ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1726 | if (!AFI->isThumbFunction()) |
| 1727 | emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, |
| 1728 | Offset, Pred, PredReg, TII); |
| 1729 | else { |
| 1730 | assert(AFI->isThumb2Function()); |
| 1731 | emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, |
| 1732 | Offset, Pred, PredReg, TII); |
| 1733 | } |
| 1734 | MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1735 | } |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1736 | } |
| 1737 | |
Jim Grosbach | 4371cda | 2009-11-04 23:20:40 +0000 | [diff] [blame] | 1738 | /// Move iterator past the next bunch of callee save load / store ops for |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1739 | /// the particular spill area (1: integer area 1, 2: integer area 2, |
| 1740 | /// 3: fp area, 0: don't care). |
| 1741 | static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, |
| 1742 | MachineBasicBlock::iterator &MBBI, |
David Goodwin | 5ff58b5 | 2009-07-24 00:16:18 +0000 | [diff] [blame] | 1743 | int Opc1, int Opc2, unsigned Area, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1744 | const ARMSubtarget &STI) { |
| 1745 | while (MBBI != MBB.end() && |
David Goodwin | 5ff58b5 | 2009-07-24 00:16:18 +0000 | [diff] [blame] | 1746 | ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && |
| 1747 | MBBI->getOperand(1).isFI()) { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1748 | if (Area != 0) { |
| 1749 | bool Done = false; |
| 1750 | unsigned Category = 0; |
| 1751 | switch (MBBI->getOperand(0).getReg()) { |
| 1752 | case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: |
| 1753 | case ARM::LR: |
| 1754 | Category = 1; |
| 1755 | break; |
| 1756 | case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: |
| 1757 | Category = STI.isTargetDarwin() ? 2 : 1; |
| 1758 | break; |
| 1759 | case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: |
| 1760 | case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: |
| 1761 | Category = 3; |
| 1762 | break; |
| 1763 | default: |
| 1764 | Done = true; |
| 1765 | break; |
| 1766 | } |
| 1767 | if (Done || Category != Area) |
| 1768 | break; |
| 1769 | } |
| 1770 | |
| 1771 | ++MBBI; |
| 1772 | } |
| 1773 | } |
| 1774 | |
| 1775 | void ARMBaseRegisterInfo:: |
| 1776 | emitPrologue(MachineFunction &MF) const { |
| 1777 | MachineBasicBlock &MBB = MF.front(); |
| 1778 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 1779 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1780 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1781 | assert(!AFI->isThumb1OnlyFunction() && |
Jim Grosbach | cf453ee | 2010-02-23 17:16:27 +0000 | [diff] [blame] | 1782 | "This emitPrologue does not support Thumb1!"); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1783 | bool isARM = !AFI->isThumbFunction(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1784 | unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); |
| 1785 | unsigned NumBytes = MFI->getStackSize(); |
| 1786 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
Chris Lattner | c7f3ace | 2010-04-02 20:16:16 +0000 | [diff] [blame] | 1787 | DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1788 | |
| 1789 | // Determine the sizes of each callee-save spill areas and record which frame |
| 1790 | // belongs to which callee-save spill areas. |
| 1791 | unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; |
| 1792 | int FramePtrSpillFI = 0; |
| 1793 | |
Bob Wilson | c8ce2d4 | 2009-09-25 16:34:46 +0000 | [diff] [blame] | 1794 | // Allocate the vararg register save area. This is not counted in NumBytes. |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1795 | if (VARegSaveSize) |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1796 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1797 | |
| 1798 | if (!AFI->hasStackFrame()) { |
| 1799 | if (NumBytes != 0) |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1800 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1801 | return; |
| 1802 | } |
| 1803 | |
| 1804 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 1805 | unsigned Reg = CSI[i].getReg(); |
| 1806 | int FI = CSI[i].getFrameIdx(); |
| 1807 | switch (Reg) { |
| 1808 | case ARM::R4: |
| 1809 | case ARM::R5: |
| 1810 | case ARM::R6: |
| 1811 | case ARM::R7: |
| 1812 | case ARM::LR: |
| 1813 | if (Reg == FramePtr) |
| 1814 | FramePtrSpillFI = FI; |
| 1815 | AFI->addGPRCalleeSavedArea1Frame(FI); |
| 1816 | GPRCS1Size += 4; |
| 1817 | break; |
| 1818 | case ARM::R8: |
| 1819 | case ARM::R9: |
| 1820 | case ARM::R10: |
| 1821 | case ARM::R11: |
| 1822 | if (Reg == FramePtr) |
| 1823 | FramePtrSpillFI = FI; |
| 1824 | if (STI.isTargetDarwin()) { |
| 1825 | AFI->addGPRCalleeSavedArea2Frame(FI); |
| 1826 | GPRCS2Size += 4; |
| 1827 | } else { |
| 1828 | AFI->addGPRCalleeSavedArea1Frame(FI); |
| 1829 | GPRCS1Size += 4; |
| 1830 | } |
| 1831 | break; |
| 1832 | default: |
| 1833 | AFI->addDPRCalleeSavedAreaFrame(FI); |
| 1834 | DPRCSSize += 8; |
| 1835 | } |
| 1836 | } |
| 1837 | |
| 1838 | // Build the new SUBri to adjust SP for integer callee-save spill area 1. |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1839 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 1840 | movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1841 | |
Bob Wilson | c8ce2d4 | 2009-09-25 16:34:46 +0000 | [diff] [blame] | 1842 | // Set FP to point to the stack slot that contains the previous FP. |
| 1843 | // For Darwin, FP is R7, which has now been stored in spill area 1. |
| 1844 | // Otherwise, if this is not Darwin, all the callee-saved registers go |
| 1845 | // into spill area 1, including the FP in R11. In either case, it is |
| 1846 | // now safe to emit this assignment. |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1847 | bool HasFP = hasFP(MF); |
| 1848 | if (HasFP) { |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1849 | unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1850 | MachineInstrBuilder MIB = |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1851 | BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1852 | .addFrameIndex(FramePtrSpillFI).addImm(0); |
| 1853 | AddDefaultCC(AddDefaultPred(MIB)); |
| 1854 | } |
| 1855 | |
| 1856 | // Build the new SUBri to adjust SP for integer callee-save spill area 2. |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1857 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1858 | |
| 1859 | // Build the new SUBri to adjust SP for FP callee-save spill area. |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 1860 | movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1861 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1862 | |
| 1863 | // Determine starting offsets of spill areas. |
| 1864 | unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); |
| 1865 | unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; |
| 1866 | unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1867 | if (HasFP) |
Bob Wilson | 436e6e7 | 2010-03-04 21:42:36 +0000 | [diff] [blame] | 1868 | AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + |
| 1869 | NumBytes); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1870 | AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); |
| 1871 | AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); |
| 1872 | AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); |
| 1873 | |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1874 | movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1875 | NumBytes = DPRCSOffset; |
| 1876 | if (NumBytes) { |
Jim Grosbach | c5848f4 | 2009-11-04 22:41:00 +0000 | [diff] [blame] | 1877 | // Adjust SP after all the callee-save spills. |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1878 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1879 | if (HasFP) |
| 1880 | AFI->setShouldRestoreSPFromFP(true); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1881 | } |
| 1882 | |
| 1883 | if (STI.isTargetELF() && hasFP(MF)) { |
| 1884 | MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - |
| 1885 | AFI->getFramePtrSpillOffset()); |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1886 | AFI->setShouldRestoreSPFromFP(true); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1887 | } |
| 1888 | |
| 1889 | AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); |
| 1890 | AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); |
| 1891 | AFI->setDPRCalleeSavedAreaSize(DPRCSSize); |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 1892 | |
| 1893 | // If we need dynamic stack realignment, do it here. |
| 1894 | if (needsStackRealignment(MF)) { |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 1895 | unsigned MaxAlign = MFI->getMaxAlignment(); |
| 1896 | assert (!AFI->isThumb1OnlyFunction()); |
Anton Korobeynikov | 7cca606 | 2009-12-06 22:39:50 +0000 | [diff] [blame] | 1897 | if (!AFI->isThumbFunction()) { |
| 1898 | // Emit bic sp, sp, MaxAlign |
| 1899 | AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, |
| 1900 | TII.get(ARM::BICri), ARM::SP) |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 1901 | .addReg(ARM::SP, RegState::Kill) |
| 1902 | .addImm(MaxAlign-1))); |
Anton Korobeynikov | 7cca606 | 2009-12-06 22:39:50 +0000 | [diff] [blame] | 1903 | } else { |
| 1904 | // We cannot use sp as source/dest register here, thus we're emitting the |
| 1905 | // following sequence: |
| 1906 | // mov r4, sp |
| 1907 | // bic r4, r4, MaxAlign |
| 1908 | // mov sp, r4 |
| 1909 | // FIXME: It will be better just to find spare register here. |
Jakob Stoklund Olesen | e9912dc | 2009-12-22 18:49:55 +0000 | [diff] [blame] | 1910 | BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) |
Anton Korobeynikov | 7cca606 | 2009-12-06 22:39:50 +0000 | [diff] [blame] | 1911 | .addReg(ARM::SP, RegState::Kill); |
| 1912 | AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, |
| 1913 | TII.get(ARM::t2BICri), ARM::R4) |
| 1914 | .addReg(ARM::R4, RegState::Kill) |
| 1915 | .addImm(MaxAlign-1))); |
| 1916 | BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) |
| 1917 | .addReg(ARM::R4, RegState::Kill); |
| 1918 | } |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1919 | |
| 1920 | AFI->setShouldRestoreSPFromFP(true); |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 1921 | } |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1922 | |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 1923 | // If we need a base pointer, set it up here. It's whatever the value |
| 1924 | // of the stack pointer is at this point. Any variable size objects |
| 1925 | // will be allocated after this, so we can still use the base pointer |
| 1926 | // to reference locals. |
| 1927 | if (hasBasePointer(MF)) { |
| 1928 | if (isARM) |
| 1929 | BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr) |
| 1930 | .addReg(ARM::SP) |
| 1931 | .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); |
| 1932 | else |
| 1933 | BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr) |
| 1934 | .addReg(ARM::SP); |
| 1935 | } |
| 1936 | |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1937 | // If the frame has variable sized objects then the epilogue must restore |
| 1938 | // the sp from fp. |
| 1939 | if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects()) |
| 1940 | AFI->setShouldRestoreSPFromFP(true); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1941 | } |
| 1942 | |
| 1943 | static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { |
| 1944 | for (unsigned i = 0; CSRegs[i]; ++i) |
| 1945 | if (Reg == CSRegs[i]) |
| 1946 | return true; |
| 1947 | return false; |
| 1948 | } |
| 1949 | |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1950 | static bool isCSRestore(MachineInstr *MI, |
Jim Grosbach | 764ab52 | 2009-08-11 15:33:49 +0000 | [diff] [blame] | 1951 | const ARMBaseInstrInfo &TII, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1952 | const unsigned *CSRegs) { |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1953 | return ((MI->getOpcode() == (int)ARM::VLDRD || |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 1954 | MI->getOpcode() == (int)ARM::LDR || |
| 1955 | MI->getOpcode() == (int)ARM::t2LDRi12) && |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1956 | MI->getOperand(1).isFI() && |
| 1957 | isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); |
| 1958 | } |
| 1959 | |
| 1960 | void ARMBaseRegisterInfo:: |
Evan Cheng | 293f8d9 | 2009-07-27 18:31:40 +0000 | [diff] [blame] | 1961 | emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1962 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 1963 | assert(MBBI->getDesc().isReturn() && |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1964 | "Can only insert epilog into returning blocks"); |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 1965 | unsigned RetOpcode = MBBI->getOpcode(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1966 | DebugLoc dl = MBBI->getDebugLoc(); |
| 1967 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1968 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1969 | assert(!AFI->isThumb1OnlyFunction() && |
Jim Grosbach | cf453ee | 2010-02-23 17:16:27 +0000 | [diff] [blame] | 1970 | "This emitEpilogue does not support Thumb1!"); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1971 | bool isARM = !AFI->isThumbFunction(); |
| 1972 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1973 | unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); |
| 1974 | int NumBytes = (int)MFI->getStackSize(); |
| 1975 | |
| 1976 | if (!AFI->hasStackFrame()) { |
| 1977 | if (NumBytes != 0) |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1978 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1979 | } else { |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 1980 | // Unwind MBBI to point to first LDR / VLDRD. |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1981 | const unsigned *CSRegs = getCalleeSavedRegs(); |
| 1982 | if (MBBI != MBB.begin()) { |
| 1983 | do |
| 1984 | --MBBI; |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1985 | while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); |
| 1986 | if (!isCSRestore(MBBI, TII, CSRegs)) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1987 | ++MBBI; |
| 1988 | } |
| 1989 | |
| 1990 | // Move SP to start of FP callee save spill area. |
| 1991 | NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + |
| 1992 | AFI->getGPRCalleeSavedArea2Size() + |
| 1993 | AFI->getDPRCalleeSavedAreaSize()); |
| 1994 | |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1995 | // Reset SP based on frame pointer only if the stack frame extends beyond |
| 1996 | // frame pointer stack slot or target is ELF and the function has FP. |
| 1997 | if (AFI->shouldRestoreSPFromFP()) { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1998 | NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; |
Evan Cheng | ac09680 | 2010-08-10 19:30:19 +0000 | [diff] [blame] | 1999 | if (NumBytes) { |
| 2000 | if (isARM) |
| 2001 | emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, |
| 2002 | ARMCC::AL, 0, TII); |
| 2003 | else |
| 2004 | emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, |
| 2005 | ARMCC::AL, 0, TII); |
| 2006 | } else { |
| 2007 | // Thumb2 or ARM. |
| 2008 | if (isARM) |
| 2009 | BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) |
| 2010 | .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); |
| 2011 | else |
| 2012 | BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) |
| 2013 | .addReg(FramePtr); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2014 | } |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 2015 | } else if (NumBytes) |
| 2016 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2017 | |
| 2018 | // Move SP to start of integer callee save spill area 2. |
Jim Grosbach | e516549 | 2009-11-09 00:11:35 +0000 | [diff] [blame] | 2019 | movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 2020 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2021 | |
| 2022 | // Move SP to start of integer callee save spill area 1. |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 2023 | movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 2024 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2025 | |
| 2026 | // Move SP to SP upon entry to the function. |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 2027 | movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 2028 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2029 | } |
| 2030 | |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 2031 | if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || |
| 2032 | RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { |
| 2033 | // Tail call return: adjust the stack pointer and jump to callee. |
| 2034 | MBBI = prior(MBB.end()); |
| 2035 | MachineOperand &JumpTarget = MBBI->getOperand(0); |
| 2036 | |
| 2037 | // Jump to label or value in register. |
| 2038 | if (RetOpcode == ARM::TCRETURNdi) { |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 2039 | BuildMI(MBB, MBBI, dl, |
Dale Johannesen | 7835f1f | 2010-07-08 01:18:23 +0000 | [diff] [blame] | 2040 | TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)). |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 2041 | addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), |
| 2042 | JumpTarget.getTargetFlags()); |
| 2043 | } else if (RetOpcode == ARM::TCRETURNdiND) { |
Dale Johannesen | 1041680 | 2010-06-18 20:44:28 +0000 | [diff] [blame] | 2044 | BuildMI(MBB, MBBI, dl, |
| 2045 | TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)). |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 2046 | addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), |
| 2047 | JumpTarget.getTargetFlags()); |
| 2048 | } else if (RetOpcode == ARM::TCRETURNri) { |
Dale Johannesen | 6470a11 | 2010-06-15 22:08:33 +0000 | [diff] [blame] | 2049 | BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)). |
| 2050 | addReg(JumpTarget.getReg(), RegState::Kill); |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 2051 | } else if (RetOpcode == ARM::TCRETURNriND) { |
Dale Johannesen | 6470a11 | 2010-06-15 22:08:33 +0000 | [diff] [blame] | 2052 | BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). |
| 2053 | addReg(JumpTarget.getReg(), RegState::Kill); |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 2054 | } |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 2055 | |
| 2056 | MachineInstr *NewMI = prior(MBBI); |
Dale Johannesen | 6470a11 | 2010-06-15 22:08:33 +0000 | [diff] [blame] | 2057 | for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) |
Dale Johannesen | 51e28e6 | 2010-06-03 21:09:53 +0000 | [diff] [blame] | 2058 | NewMI->addOperand(MBBI->getOperand(i)); |
| 2059 | |
| 2060 | // Delete the pseudo instruction TCRETURN. |
| 2061 | MBB.erase(MBBI); |
| 2062 | } |
| 2063 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2064 | if (VARegSaveSize) |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 2065 | emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 2066 | } |
| 2067 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 2068 | #include "ARMGenRegisterInfo.inc" |