Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f64a7d49a0cdc8587f5b79bb2ac7be5fe56c1746 / . / lib / Target / ARM / ARMISelLowering.h
blob: 05d7d5f1cf145eb2c8219c003336fccd7e3019df [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]18#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]19#include "llvm/Target/TargetLowering.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]20#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]21#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]22#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]23#include <vector>
24
25namespace llvm {
26 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]27
28 namespace ARMISD {
29 // ARM Specific DAG Nodes
30 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]31 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]33
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]36 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]37
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]38 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]39 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]40 CALL_NOLINK, // Function call with branch not branch-and-link.
41 tCALL, // Thumb function call.
42 BRCOND, // Conditional branch.
43 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]44 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]45 RET_FLAG, // Return with a flag operand.
46
47 PIC_ADD, // Add with a PC operand and a PIC label.
48
49 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]50 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]51 CMPFP, // ARM VFP compare instruction, sets FPSCR.
52 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
53 FMSTAT, // ARM fmstat instruction.
54 CMOV, // ARM conditional move instructions.
55 CNEG, // ARM conditional negate instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]56
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]57 BCC_i64,
58
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]59 RBIT, // ARM bitreverse instruction
60
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]61 FTOSI, // FP to sint within a FP register.
62 FTOUI, // FP to uint within a FP register.
63 SITOF, // sint to FP within a FP register.
64 UITOF, // uint to FP within a FP register.
65
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]66 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
67 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
68 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]69
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]70 VMOVRRD, // double to two gprs.
71 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]72
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]73 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
74 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]75
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]76 TC_RETURN, // Tail call return pseudo.
77
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]78 THREAD_POINTER,
79
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]80 DYN_ALLOC, // Dynamic allocation on the stack.
81
Jim Grosbach3728e962009-12-10 00:11:09 +0000[diff] [blame]82 MEMBARRIER, // Memory barrier
83 SYNCBARRIER, // Memory sync barrier
84
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]85 VCEQ, // Vector compare equal.
86 VCGE, // Vector compare greater than or equal.
87 VCGEU, // Vector compare unsigned greater than or equal.
88 VCGT, // Vector compare greater than.
89 VCGTU, // Vector compare unsigned greater than.
90 VTST, // Vector test bits.
91
92 // Vector shift by immediate:
93 VSHL, // ...left
94 VSHRs, // ...right (signed)
95 VSHRu, // ...right (unsigned)
96 VSHLLs, // ...left long (signed)
97 VSHLLu, // ...left long (unsigned)
98 VSHLLi, // ...left long (with maximum shift count)
99 VSHRN, // ...right narrow
100
101 // Vector rounding shift by immediate:
102 VRSHRs, // ...right (signed)
103 VRSHRu, // ...right (unsigned)
104 VRSHRN, // ...right narrow
105
106 // Vector saturating shift by immediate:
107 VQSHLs, // ...left (signed)
108 VQSHLu, // ...left (unsigned)
109 VQSHLsu, // ...left (signed to unsigned)
110 VQSHRNs, // ...right narrow (signed)
111 VQSHRNu, // ...right narrow (unsigned)
112 VQSHRNsu, // ...right narrow (signed to unsigned)
113
114 // Vector saturating rounding shift by immediate:
115 VQRSHRNs, // ...right narrow (signed)
116 VQRSHRNu, // ...right narrow (unsigned)
117 VQRSHRNsu, // ...right narrow (signed to unsigned)
118
119 // Vector shift and insert:
120 VSLI, // ...left
121 VSRI, // ...right
122
123 // Vector get lane (VMOV scalar to ARM core register)
124 // (These are used for 8- and 16-bit element types only.)
125 VGETLANEu, // zero-extend vector extract element
126 VGETLANEs, // sign-extend vector extract element
127
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]128 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]129 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]130 VMVNIMM,
131
132 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]133 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]134 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]135
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]136 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]137 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]138 VREV64, // reverse elements within 64-bit doublewords
139 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]140 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]141 VZIP, // zip (interleave)
142 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]143 VTRN, // transpose
144
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]145 // Operands of the standard BUILD_VECTOR node are not legalized, which
146 // is fine if BUILD_VECTORs are always lowered to shuffles or other
147 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
148 // operands need to be legalized. Define an ARM-specific version of
149 // BUILD_VECTOR for this purpose.
150 BUILD_VECTOR,
151
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]152 // Floating-point max and min:
153 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]154 FMIN,
155
156 // Bit-field insert
157 BFI
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]158 };
159 }
160
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]161 /// Define some predicates that are used for node matching.
162 namespace ARM {
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]163 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
164 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
165 /// instruction, returns its 8-bit integer representation. Otherwise,
166 /// returns -1.
167 int getVFPf32Imm(const APFloat &FPImm);
168 int getVFPf64Imm(const APFloat &FPImm);
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]169 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]170 }
171
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]172 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]173 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]174
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]175 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]176 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]177 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]178
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]179 virtual unsigned getJumpTableEncoding(void) const;
180
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]181 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]182
183 /// ReplaceNodeResults - Replace the results of node with an illegal result
184 /// type with new values built out of custom code.
185 ///
186 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]187 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]188
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]189 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]190
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]191 virtual const char *getTargetNodeName(unsigned Opcode) const;
192
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]193 virtual MachineBasicBlock *
194 EmitInstrWithCustomInserter(MachineInstr *MI,
195 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]196
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]197 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
198 /// unaligned memory accesses. of the specified type.
199 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
200 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
201
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]202 /// isLegalAddressingMode - Return true if the addressing mode represented
203 /// by AM is legal for this target, for a load/store of the specified type.
204 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]205 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]206
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]207 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]208 /// icmp immediate, that is the target has icmp instructions which can
209 /// compare a register against the immediate without having to materialize
210 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]211 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]212
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]213 /// getPreIndexedAddressParts - returns true by value, base pointer and
214 /// offset pointer and addressing mode by reference if the node's address
215 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]216 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
217 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]218 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]219 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]220
221 /// getPostIndexedAddressParts - returns true by value, base pointer and
222 /// offset pointer and addressing mode by reference if this node can be
223 /// combined with a load / store to form a post-indexed load / store.
224 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]225 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]226 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]227 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]228
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]229 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]230 const APInt &Mask,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]231 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]232 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]233 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]234 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]235
236
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]237 ConstraintType getConstraintType(const std::string &Constraint) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]238 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]239 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]240 EVT VT) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]241 std::vector<unsigned>
242 getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]243 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]244
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]245 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
246 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
247 /// true it means one of the asm constraint of the inline asm instruction
248 /// being processed is 'm'.
249 virtual void LowerAsmOperandForConstraint(SDValue Op,
250 char ConstraintLetter,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]251 std::vector<SDValue> &Ops,
252 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]253
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]254 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]255 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]256 }
257
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]258 /// getRegClassFor - Return the register class that should be used for the
259 /// specified value type.
260 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
261
Bill Wendlingb4202b82009-07-01 18:50:55 +0000[diff] [blame]262 /// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +0000[diff] [blame]263 virtual unsigned getFunctionAlignment(const Function *F) const;
264
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]265 /// createFastISel - This method returns a target specific FastISel object,
266 /// or null if the target does not support "fast" ISel.
267 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
268
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]269 Sched::Preference getSchedulingPreference(SDNode *N) const;
270
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]271 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]272 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]273
274 /// isFPImmLegal - Returns true if the target can instruction select the
275 /// specified FP immediate natively. If false, the legalizer will
276 /// materialize the FP immediate as a load from a constant pool.
277 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
278
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]279 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]280 std::pair<const TargetRegisterClass*, uint8_t>
281 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]282
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]283 private:
284 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
285 /// make the right decision when generating code for different targets.
286 const ARMSubtarget *Subtarget;
287
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]288 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]289 ///
290 unsigned ARMPCLabelIndex;
291
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]292 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
293 void addDRTypeForNEON(EVT VT);
294 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]295
296 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]297 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]298 SDValue Chain, SDValue &Arg,
299 RegsToPassVector &RegsToPass,
300 CCValAssign &VA, CCValAssign &NextVA,
301 SDValue &StackPtr,
302 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]303 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]304 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]305 SDValue &Root, SelectionDAG &DAG,
306 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]307
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]308 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
309 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]310 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
311 DebugLoc dl, SelectionDAG &DAG,
312 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]313 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]314 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]315 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]316 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]317 const ARMSubtarget *Subtarget) const;
318 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
319 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
320 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
321 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]322 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]323 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]324 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]325 SelectionDAG &DAG) const;
326 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
327 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
328 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
329 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]330 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]331 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]332 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
333 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
334 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
335 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]336
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]337 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]338 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]339 const SmallVectorImpl<ISD::InputArg> &Ins,
340 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]341 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]342
343 virtual SDValue
344 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]345 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]346 const SmallVectorImpl<ISD::InputArg> &Ins,
347 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]348 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]349
350 virtual SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000[diff] [blame]351 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]352 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +0000[diff] [blame]353 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]354 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]355 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]356 const SmallVectorImpl<ISD::InputArg> &Ins,
357 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]358 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]359
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
361 /// for tail call optimization. Targets which want to do tail call
362 /// optimization should implement this function.
363 bool IsEligibleForTailCallOptimization(SDValue Callee,
364 CallingConv::ID CalleeCC,
365 bool isVarArg,
366 bool isCalleeStructRet,
367 bool isCallerStructRet,
368 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]369 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]370 const SmallVectorImpl<ISD::InputArg> &Ins,
371 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]372 virtual SDValue
373 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]374 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]375 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]376 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]377 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]378
379 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]380 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
381 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
382 SelectionDAG &DAG, DebugLoc dl) const;
383
384 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]385
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]386 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
387 MachineBasicBlock *BB,
388 unsigned Size) const;
389 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
390 MachineBasicBlock *BB,
391 unsigned Size,
392 unsigned BinOpcode) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]393
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]394 };
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]395
396 namespace ARM {
397 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
398 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]399}
400
401#endif // ARMISELLOWERING_H