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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 3144687df78731ac4ddbc716a24b951678a73f57 / . / lib / Target / ARM / ARMISelLowering.h
blob: b544b5eee2baa8ce2c42b4d28020163205e34920 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]18#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]19#include "llvm/Target/TargetLowering.h"
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame^]20#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]21#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]22#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]23#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]24#include <vector>
25
26namespace llvm {
27 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]28
29 namespace ARMISD {
30 // ARM Specific DAG Nodes
31 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]32 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]34
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]38
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]39 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]40 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]41 CALL_NOLINK, // Function call with branch not branch-and-link.
42 tCALL, // Thumb function call.
43 BRCOND, // Conditional branch.
44 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]46 RET_FLAG, // Return with a flag operand.
47
48 PIC_ADD, // Add with a PC operand and a PIC label.
49
50 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]51 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]52 CMPFP, // ARM VFP compare instruction, sets FPSCR.
53 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
54 FMSTAT, // ARM fmstat instruction.
55 CMOV, // ARM conditional move instructions.
56 CNEG, // ARM conditional negate instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]57
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]58 BCC_i64,
59
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]60 RBIT, // ARM bitreverse instruction
61
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]62 FTOSI, // FP to sint within a FP register.
63 FTOUI, // FP to uint within a FP register.
64 SITOF, // sint to FP within a FP register.
65 UITOF, // uint to FP within a FP register.
66
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]70
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]71 VMOVRRD, // double to two gprs.
72 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]73
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]74 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
75 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]76
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]77 TC_RETURN, // Tail call return pseudo.
78
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]79 THREAD_POINTER,
80
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]81 DYN_ALLOC, // Dynamic allocation on the stack.
82
Jim Grosbach3728e962009-12-10 00:11:09 +0000[diff] [blame]83 MEMBARRIER, // Memory barrier
84 SYNCBARRIER, // Memory sync barrier
85
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]86 VCEQ, // Vector compare equal.
87 VCGE, // Vector compare greater than or equal.
88 VCGEU, // Vector compare unsigned greater than or equal.
89 VCGT, // Vector compare greater than.
90 VCGTU, // Vector compare unsigned greater than.
91 VTST, // Vector test bits.
92
93 // Vector shift by immediate:
94 VSHL, // ...left
95 VSHRs, // ...right (signed)
96 VSHRu, // ...right (unsigned)
97 VSHLLs, // ...left long (signed)
98 VSHLLu, // ...left long (unsigned)
99 VSHLLi, // ...left long (with maximum shift count)
100 VSHRN, // ...right narrow
101
102 // Vector rounding shift by immediate:
103 VRSHRs, // ...right (signed)
104 VRSHRu, // ...right (unsigned)
105 VRSHRN, // ...right narrow
106
107 // Vector saturating shift by immediate:
108 VQSHLs, // ...left (signed)
109 VQSHLu, // ...left (unsigned)
110 VQSHLsu, // ...left (signed to unsigned)
111 VQSHRNs, // ...right narrow (signed)
112 VQSHRNu, // ...right narrow (unsigned)
113 VQSHRNsu, // ...right narrow (signed to unsigned)
114
115 // Vector saturating rounding shift by immediate:
116 VQRSHRNs, // ...right narrow (signed)
117 VQRSHRNu, // ...right narrow (unsigned)
118 VQRSHRNsu, // ...right narrow (signed to unsigned)
119
120 // Vector shift and insert:
121 VSLI, // ...left
122 VSRI, // ...right
123
124 // Vector get lane (VMOV scalar to ARM core register)
125 // (These are used for 8- and 16-bit element types only.)
126 VGETLANEu, // zero-extend vector extract element
127 VGETLANEs, // sign-extend vector extract element
128
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]129 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]130 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]131 VMVNIMM,
132
133 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]134 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]135 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]136
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]137 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]138 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]139 VREV64, // reverse elements within 64-bit doublewords
140 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]141 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]142 VZIP, // zip (interleave)
143 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]144 VTRN, // transpose
145
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]146 // Operands of the standard BUILD_VECTOR node are not legalized, which
147 // is fine if BUILD_VECTORs are always lowered to shuffles or other
148 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
149 // operands need to be legalized. Define an ARM-specific version of
150 // BUILD_VECTOR for this purpose.
151 BUILD_VECTOR,
152
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]153 // Floating-point max and min:
154 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]155 FMIN,
156
157 // Bit-field insert
158 BFI
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]159 };
160 }
161
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]162 /// Define some predicates that are used for node matching.
163 namespace ARM {
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]164 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
165 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
166 /// instruction, returns its 8-bit integer representation. Otherwise,
167 /// returns -1.
168 int getVFPf32Imm(const APFloat &FPImm);
169 int getVFPf64Imm(const APFloat &FPImm);
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]170 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]171 }
172
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]173 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]174 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]175
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]176 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]177 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]178 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]179
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]180 virtual unsigned getJumpTableEncoding(void) const;
181
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]182 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]183
184 /// ReplaceNodeResults - Replace the results of node with an illegal result
185 /// type with new values built out of custom code.
186 ///
187 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]188 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]189
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]190 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]191
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]192 virtual const char *getTargetNodeName(unsigned Opcode) const;
193
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]194 virtual MachineBasicBlock *
195 EmitInstrWithCustomInserter(MachineInstr *MI,
196 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]197
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]198 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
199 /// unaligned memory accesses. of the specified type.
200 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
201 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
202
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]203 /// isLegalAddressingMode - Return true if the addressing mode represented
204 /// by AM is legal for this target, for a load/store of the specified type.
205 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]206 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]207
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]208 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]209 /// icmp immediate, that is the target has icmp instructions which can
210 /// compare a register against the immediate without having to materialize
211 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]212 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]213
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]214 /// getPreIndexedAddressParts - returns true by value, base pointer and
215 /// offset pointer and addressing mode by reference if the node's address
216 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]217 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
218 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]219 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]220 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]221
222 /// getPostIndexedAddressParts - returns true by value, base pointer and
223 /// offset pointer and addressing mode by reference if this node can be
224 /// combined with a load / store to form a post-indexed load / store.
225 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]226 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]227 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]228 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]229
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]230 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]231 const APInt &Mask,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]232 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]233 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]234 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]235 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]236
237
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]238 ConstraintType getConstraintType(const std::string &Constraint) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]239 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]240 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]241 EVT VT) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]242 std::vector<unsigned>
243 getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]244 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]245
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]246 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
247 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
248 /// true it means one of the asm constraint of the inline asm instruction
249 /// being processed is 'm'.
250 virtual void LowerAsmOperandForConstraint(SDValue Op,
251 char ConstraintLetter,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]252 std::vector<SDValue> &Ops,
253 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]254
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]255 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]256 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]257 }
258
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]259 /// getRegClassFor - Return the register class that should be used for the
260 /// specified value type.
261 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
262
Bill Wendlingb4202b82009-07-01 18:50:55 +0000[diff] [blame]263 /// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +0000[diff] [blame]264 virtual unsigned getFunctionAlignment(const Function *F) const;
265
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]266 /// createFastISel - This method returns a target specific FastISel object,
267 /// or null if the target does not support "fast" ISel.
268 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
269
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]270 Sched::Preference getSchedulingPreference(SDNode *N) const;
271
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame^]272 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
273 MachineFunction &MF) const;
274
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]275 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]276 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]277
278 /// isFPImmLegal - Returns true if the target can instruction select the
279 /// specified FP immediate natively. If false, the legalizer will
280 /// materialize the FP immediate as a load from a constant pool.
281 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
282
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]283 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]284 std::pair<const TargetRegisterClass*, uint8_t>
285 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]286
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]287 private:
288 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
289 /// make the right decision when generating code for different targets.
290 const ARMSubtarget *Subtarget;
291
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame^]292 const TargetRegisterInfo *RegInfo;
293
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]294 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]295 ///
296 unsigned ARMPCLabelIndex;
297
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]298 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
299 void addDRTypeForNEON(EVT VT);
300 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]301
302 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]303 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]304 SDValue Chain, SDValue &Arg,
305 RegsToPassVector &RegsToPass,
306 CCValAssign &VA, CCValAssign &NextVA,
307 SDValue &StackPtr,
308 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]309 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]310 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]311 SDValue &Root, SelectionDAG &DAG,
312 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]313
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]314 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
315 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]316 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
317 DebugLoc dl, SelectionDAG &DAG,
318 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]319 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]320 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]321 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]322 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]323 const ARMSubtarget *Subtarget) const;
324 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
325 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
326 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
327 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]328 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]329 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]330 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]331 SelectionDAG &DAG) const;
332 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
333 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
334 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
335 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]336 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]337 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]338 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
339 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
340 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
341 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]342
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]343 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]344 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]345 const SmallVectorImpl<ISD::InputArg> &Ins,
346 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]347 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]348
349 virtual SDValue
350 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]351 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]352 const SmallVectorImpl<ISD::InputArg> &Ins,
353 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]354 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]355
356 virtual SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000[diff] [blame]357 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]358 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +0000[diff] [blame]359 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]360 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]361 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]362 const SmallVectorImpl<ISD::InputArg> &Ins,
363 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]364 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]365
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]366 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
367 /// for tail call optimization. Targets which want to do tail call
368 /// optimization should implement this function.
369 bool IsEligibleForTailCallOptimization(SDValue Callee,
370 CallingConv::ID CalleeCC,
371 bool isVarArg,
372 bool isCalleeStructRet,
373 bool isCallerStructRet,
374 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]375 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]376 const SmallVectorImpl<ISD::InputArg> &Ins,
377 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]378 virtual SDValue
379 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]380 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]381 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]382 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]383 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]384
385 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]386 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
387 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
388 SelectionDAG &DAG, DebugLoc dl) const;
389
390 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]391
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]392 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
393 MachineBasicBlock *BB,
394 unsigned Size) const;
395 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
396 MachineBasicBlock *BB,
397 unsigned Size,
398 unsigned BinOpcode) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]399
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]400 };
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]401
402 namespace ARM {
403 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
404 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]405}
406
407#endif // ARMISELLOWERING_H